Patent Grant
7812804
1. Field of the Invention
The present invention relates to a drive circuit of a display device and to a display device, and more particularly to a drive circuit suitable for liquid crystal display devices with a dot inversion drive.
2. Description of the Related Art
Liquid crystal displays are employed as displays for various lightweight and thin electronic devices with low power consumption, such as cellular phones. As liquid crystal displays, a simple matrix type and an active matrix type (AMLCD: Active Matrix Liquid crystal display) using active elements such as TFTs (Thin Film Transistors) in a pixel circuit are known.
In the conventional liquid crystal display, the polarity of the voltage applied from the data lines 4 to the pixels via TFT (referred to hereinbelow as “pixel voltage”) is inverted at prescribed periods. In other words, the pixels are AC driven. The term “polarity” used herein indicates whether the pixel voltage is positive or negative with respect to a voltage of a common electrode (com voltage) as a reference. Such a drive method is employed to inhibit the degradation of liquid-crystal material. For example, a dot inversion drive method in which the polarity of pixel voltage is inverted every adjacent data line and scanning line so that the polarity is different for the adjacent pixels, as shown in
The positive polarity drive circuit comprises a level shift circuit P 65 for level shifting the picture signal to the positive side with respect to the com voltage and the positive polarity D/A conversion circuit 67. The negative polarity drive circuit comprises a level shift circuit N 66 for level shifting the picture signal to the negative side with respect to the con voltage and the negative polarity D/A conversion circuit 68. A com voltage of 5 V, a positive polarity voltage of from 5V to 10V, and a negative polarity voltage of from 0V to 5V are disclosed as examples of each voltage setting. In this case, the con voltage, the voltage of the data line drive circuit, and the voltage of the scanning line drive are generated by the power source circuit 58.
It has now been discovered that, however, this conventional drive circuit has several drawbacks. The first of them is the increase of circuitry scale. A level shift circuit is provided in each drive circuit corresponding to each data line. If the difference between the voltage inputted into the level shift circuit and the voltage to which the level is shifted is large, the circuitry scale is increased. Furthermore, in the level shift circuit, if the power source voltage is high, it is necessary to increase the breakdown voltage of the elements constituting the circuit. Accordingly, the gate oxide film Tox is made thick, the gate length L and gate width W are increased, and the distance between the elements is increased. As a result, the circuit surface area is increased.
Further, in the conventional drive circuit (
Further, in the conventional drive circuit, the signals for every two adjacent signals is switched to a positive or negative level shift circuit 65, 66 after the digital picture signal of one scanning line has been latched in parallel in the data latch circuit 63. Therefore, the number of required switching circuits 64 for switching the digital picture signals is also n×m.
The second drawback is the large power consumption. If the com voltage is 5V, the high level voltage of about 10 V of positive polarity is generated in the power source circuit, as a result, the efficiency of the power source circuit decreases and power consumption increases. A charge pump structure composed of a plurality of capacitors and switches is employed in the power source circuit, and if a voltage of 10V is generated from 2.5V, the power source efficiency is from about 60% to 70%. The switches have a parasitic capacitor, and the power is consumed by this parasitic capacitor, thereby decreasing the efficiency. For example, when the voltage is increased from 2.5V to 5V, the efficiency is 80%, and when the voltage is increased from 5 V to 10 V, the efficiency is similarly 80%, however, for the increase from 2.5 V to 10 V, the efficiency is 80%×80%=64%. If the power source voltage used for drive is high, then the number of voltage increase steps is increased, the efficiency of the power source circuit is decreased, and power consumption is increased.
According to one aspect of the invention, there is provided a drive circuit for a display apparatus outputting analog picture signals in parallel produced based on serial input digital picture signals. The drive circuit comprises a level shift circuit level shifting voltage levels of serially inputted digital picture signals, a D/A conversion circuit producing analog picture signals based on the digital picture signals level shifted by the level shift circuit, and an expansion circuit connected at an output side of the D/A conversion circuit or between the level shift circuit and the D/A conversion circuit for expanding and holding in parallel serially inputted picture signals and outputting the picture signals in parallel. Arranging the level shift circuit preceding to the D/A conversion circuit and the expansion circuit allows reduction of the circuit scale.
According to another aspect of the invention, there is provided a display apparatus comprising a display panel having a plurality of pixels and a drive circuit providing analog picture signals controlling brightness of the pixels. The drive circuit comprises a level shift circuit level shifting voltage levels of serially inputted digital picture signals, a D/A conversion circuit producing analog picture signals based on the digital picture signals level shifted by the level shift circuit, an expansion circuit connected at an output side of the D/A conversion circuit or between the level shift circuit and the D/A conversion circuit for expanding and holding in parallel serially inputted picture signals and outputting the picture signals in parallel.
According to another aspect of the invention, there is provided a drive circuit for a display apparatus outputting a positive polarity analog picture signal and a negative polarity analog picture signal with respect to a reference voltage to data lines of the display apparatus. The drive circuit comprises a positive polarity drive circuit formed in a first continuous area on a substrate for outputting the positive polarity analog picture signal, a negative polarity drive circuit formed in a second continuous area different from the first continuous area on the substrate for outputting the negative polarity analog picture signal, and a switching circuit formed in a third continuous area different from the first and the second continuous areas on the substrate and switching the positive polarity analog picture signal from the positive polarity drive circuit and the negative polarity analog picture signal from the negative polarity drive circuit. This element arrangement of invention allows the reduction of chip size.
According to another aspect of the invention, there is provided a display apparatus comprising a display panel having a plurality of pixels and a drive circuit providing the display panel with a positive polarity analog picture signal and a negative polarity analog picture signal with respect to a reference voltage. The drive circuit comprises a positive drive circuit, a negative drive circuit and a switching circuit. The positive drive circuit is formed in a first continuous area on a substrate, processes positive polarity digital picture signals, and D/A converts the positive polarity digital picture signals to output positive polarity analog picture signals. The negative drive circuit is formed in a second continuous area different from the first area on a substrate, processes negative polarity digital picture signals and D/A converts the negative polarity digital picture signals to output negative polarity analog picture signals. The switching circuit switches outputs from the positive drive circuit and negative drive circuit.
According to another aspect of the invention, there is provided a drive circuit for a display apparatus outputting a positive polarity analog picture signal and a negative polarity analog picture signal with respect to a reference voltage to a data line of the display apparatus. The drive circuit comprises a positive polarity drive circuit outputting the positive polarity analog picture signal, a negative polarity drive circuit outputting the negative polarity analog picture signal, a switching circuit switching the positive polarity analog picture signal and the negative polarity analog picture signal to provide to the data line, a positive polarity pre-charge switch, formed between the positive polarity drive circuit and the switching circuit, capable of pre-charging the data line to a positive polarity pre-charge voltage before an analog signal provided to the data line is changed from the positive polarity to the negative polarity, and a negative polarity pre-charge switch, formed between the negative polarity drive circuit and the switching circuit, capable of pre-charging the data line to a negative polarity pre-charge voltage before an analog signal provided to the data line is changed from the negative polarity to the positive polarity. Since the positive and negative drive circuits have the pre-charge switch respectively, it is possible to fabricate the pre-charge switches of medium-voltage elements for reduction of circuit scale.
According to another aspect of the invention, there is provided a drive circuit for a display apparatus D/A converting an digital picture to provide an analog picture signal to a data line of the display apparatus. The drive circuit comprises a positive polarity drive circuit outputting the positive polarity analog picture signal with respect to system ground voltage, a negative polarity drive circuit outputting the negative polarity analog picture signal with respect to the system ground voltage, and a power supply circuit generating a DC voltage different from the system ground within between a high voltage of the positive polarity drive circuit and a low voltage of the negative polarity drive circuit to provide to a common electrode of the display apparatus. The common voltage allows the compensation for the feed-through error.
The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:
An analog picture signal for controlling the brightness (quantity of transmitted light) of the pixel is supplied from the data line to the display electrode, and a com voltage (DC voltage) is supplied to the common electrode. Furthermore, the liquid crystal display comprises a data line drive circuit 1 for driving the data lines 4, a scanning line drive circuit 2 for driving the scanning lines 5, a control circuit 7 for controlling the data line drive circuit 1 and scanning line drive circuit 2, and a power source circuit 8 for supplying voltage to the control circuit 7, data line drive circuit 1, and scanning line drive circuit 2. The high-voltage voltage of the power source voltage supplied to the power source circuit 8 is a VDC and a low-voltage voltage is a system ground GND.
Signals inputted into the data line drive circuit 1 include a digital picture signal Dx (abbreviated hereinbelow as picture signal Dx), a clock signal CLK, a horizontal start signal STH, a latch signal STB, and a polarity signal POL. The desired timing signals are generated form those signals in the signal processing circuit 31, to control the below-described data latch signals 13, 23 or switching circuit 33. Furthermore, the signal processing circuit 31 comprises a clock generation circuit 3161 shown in
As for the picture signal Dx in a 64-gradation (6 bit) color liquid crystal display, a signal of 1 display element (3 pixels) consisting of a total 18 bit of DR (DR00, DR01, DR02, DR03, DR04, DR05), DG (DG00, DG01, DG02, DG03, DG04, DG05), DB (DB00, DB01, DB02, DB03, DB04, DB05), is inputted synchronously with the clock signal CLK. The explanation below will be provided with respect to a case where the picture signal Dx is of 6 bit for each R, G and B. This number is not limiting, and the picture signal Dx may be of 7 bit or more and of 5 bit and less.
If a digital picture signal that will be inputted into the data line drive circuit 1 is inputted for each 1 display element (3 pixels, 18 bit), when the number of pixels is QVGA (240 RGB×320), the clock frequency of the data line drive circuit 1 is (frame frequency)×(number of pixels)=60 Hz×320×240=about 4.6 MHz. Even if in VGA whose pixel number (480 RGB×640) is 4 times of QVGA, if the picture signal is imputed into the data line drive circuit 1 is for every two display elements (36 bit), then the sufficient clock frequency will be 9.2 MHz.
The horizontal start signal STH is inputted into the shift register circuits 11, 21, and sampling signals synchronized with the clock signal CLK are successively generated in the shift register circuits 11, 21. The shift register circuit is composed of a plurality of flip-flop circuits. The picture signals Dx successively inputted synchronously with the clock signal CLK are latched in the data register circuits 12, 22 in accordance with the sampling signals. The picture signals Dx latched in the data register circuits 12, 22 are outputted in parallel into the data latch circuits 13, 23 in response to the input of the latch signal STB and latched in the data latch circuits 13, 23. The data latch circuits 13, 23 are connected to the D/A conversion circuits 14, 24 and supply positive polarity signals and negative polarity signals to each data line via the switching circuit 33 that selects alternately a positive polarity signal and a negative polarity signal in accordance with the polarity signal POL.
The data line drive circuit 1 in accordance with the present invention simultaneously outputs analog picture signals of different polarity into adjacent lines. The data line drive circuit 1 comprises a positive polarity drive circuit 10 for supplying an analog picture signal of positive polarity and a negative polarity drive circuit 20 for supplying an analog picture signal of negative polarity, and the positive polarity or negative polarity signal is selected and outputted into the data line by the switching circuit 33. Here, the positive polarity and negative polarity indicate a positive or negative side of the pixel voltage in the case where the voltage (com voltage) of the liquid crystal common electrode of the liquid crystal is taken as a reference voltage.
The present invention is particularly relates to a driver circuit providing analog signals to data lines. The operation voltage of the positive polarity drive circuit 10 is from VPL to VPH and the operation voltage of the negative polarity drive circuit 20 is from VNL to VLH. The reference voltage of the dive circuit driving data lines is the system GND (0V) and the com voltage is also the system GND. When VPL and VNH are the same as GND, VPL and VNH may be short circuited to GND. If the following relationships are valid: VPH>VPL, VPH>VNH, VNH>VNL, VPL>VNL, then the VNH and VPL may be different voltages. Hereinafter, for simplifying the explanation, it is assumed in the explanation of this embodiment 1 that VPL=VNH=GND, VPH=5V, VNL=−5V. Furthermore, if the operation is conducted at a liquid crystal threshold voltage of about 3V, then the VPH may be 3V and VNL may be −3V. Or if the feed-through error due to a parasitic capacitor of a TFT is taken into account, VPH may be 6V and VNL may be −4V, or VPH may be 4V and VNL may be −6V.
The positive polarity drive circuit 10 comprises at least a positive polarity D/A conversion circuit 14 and a positive polarity gradation voltage generation circuit 15. In the present embodiment, the positive polarity drive circuit 10 further comprises a positive polarity shift register circuit 11, a positive polarity register circuit 12 that is a latch circuit, and a positive polarity data latch circuit 13. The operation voltage of each circuit is GND to VPH. The negative polarity drive circuit 20 comprises at least a negative polarity D/A conversion circuit 24 and a negative polarity gradation voltage generation circuit 25. It also further comprises a negative polarity shift register circuit 2121, a negative polarity register circuit 22 that is a latch circuit a negative polarity register circuit 22, and a negative polarity data latch circuit 23. The operation voltage of each circuit is VNL to GND.
The signal processing circuit 31 operates at VSS to VDD (2.5V). Therefore, a level shift circuit 32 is provided between the signal processing circuit 31 and the positive polarity drive circuit 10 and negative polarity drive circuit 20. If the low-level voltage VSS of the signal processing circuit 31 may be short circuited to GND, or the VSS may be a voltage different from GND. Hereinafter, in the embodiment 1, it is assumed that VSS is the same as GND for simplifying the explanation.
The level shift circuit 32 comprises the below-described positive polarity level shift circuit 321 and negative polarity level shift circuit 322 correspondingly to the signal generated in the signal processing circuit 31 and also a high-voltage level shift circuit 323. The signals to be inputted into the positive polarity drive circuit 10 and negative polarity drive circuit 20 are inputted after being level shifted to respective operation voltages with the positive polarity level shift circuit 321 and negative polarity level shift circuit 322. For example, as for the CK3 signal generated from the clock signal CLK, the CK3_P signal with a level shifted to the positive polarity side is inputted into the positive polarity drive circuit 10 and the CK3_N signal with a level shifted to the negative polarity side is inputted into the negative polarity drive circuit 20. As for the other signals such as a start signal STH, similarly, the signal_P and signal_N are inputted into the positive polarity drive circuit 10 and negative polarity drive circuit 20, respectively. The signal controlling the switching circuit 33 is (VPH-VNL). Therefore, the signal is inputted via the high-voltage level shift circuit 323. Here, the voltage of the signal controlling the switching circuit 33 may be a voltage equal to or higher than the VPH and may be a voltage equal to or lower than the VNL.
The level shift circuit 32 will be described below in greater detail. The circuit shown in
The operation of the positive polarity level shift circuit 321 will be described below. For the sake of simplicity, the output of a node P2 with respect to the input of a node Q or node QB will be explained. When the “H” level, that is, a VDD voltage is inputted into the node Q, the N channel transistor 3214 becomes active, and the node P1 assumes GND, that is, a “L” level. Therefore, the P channel transistor 3213 becomes active and the node P2 assumes VPH. Conversely, when an “L” level, that is, GND, is inputted into the node Q, because the node QB is at a “HH” level at this time, the N channel transistor 3215 become active. Therefore, the node P2 assumes GND. The signal that was thus outputted according to the input signal is outputted to the outside by an inverter 3216 via a delay circuit 3211.
The negative polarity level shift circuit 322 is a level shift circuit of a two-stage structure, where the level shifter of the first stage provides for VNL-VDD shift, and the level shifter of the second stage provides for VNL-GND shift. The first stage comprises a serial circuit of the P channel transistor 3221 and N channel transistor 3223 and a serial circuit of the P channel transistor 3222 and N channel transistor 3224, which are connected between the VDD and VNL. The input from the outside is inputted into the gate of the P channel transistor 3221 or P channel transistor 3222 on the high-voltage side, and a signal is outputted from the intermediate node P4 of the P channel transistor 3222 and N channel transistor 3224 in one serial circuit. The gate of the N channel transistor 3223 or N channel transistor 3224 is connected to the intermediate node P3 or P4 of the other serial circuit. The signals of different polarity from the outside are inputted from the nodes QB, Q into the gate of each P channel transistor connected to the high-voltage side.
In the second stage, the outputs from the first stage are inputted into gates of the N channel transistor 3227 or N channel transistor 3228 connected to the low-voltage side. The output of the second stage is outputted to the outside via the inverter 3229. The circuit configuration of the second stage is identical to that of the level shifter 3211 of the positive polarity level shift circuit, though the power source voltage is different. Thus, the second stage comprises a serial circuit of the P channel transistor 3225 and N channel transistor 3227 and a serial circuit of the P channel transistor 3226 and N channel transistor 3228, those circuits being connected between GND and VNL.
The operation of the negative polarity level shift circuit 322 will be described below. First, the output of the node P3 and node P4 corresponding to the node Q or node QB will be explained. When a “H” level, that is, VDD is inputted into the node Q, because the node QB is an “L” level, that is, at GND, the P channel transistor 3222 becomes active. Therefore, the node P4 assumes VDD, that is, “H” level. As a result, the N channel transistor 3223 becomes active, and the node P3 assumes VNL, that is, “L” level. Conversely, when “L” level, that is, GND is inputted to the node Q, the P channel transistor 3221 becomes active and the node P3 assumes VDD, that is, “H” level. Therefore, the N channel transistor 3224 becomes active and the node P4 assumes VNL, that is, “L” level.
The output of the node P6 relating to node P4 will be explained below. When the node P4 is at “H” level, that is, VDD, the N channel transistor 3227 becomes active and the node P5 assumes VNL, that is, “L” level. As a result, the P channel transistor 3226 becomes active and the node P6 assumes GND. Conversely, when the node P4 is at “L” level, that is, VNL, the node P3 assumes “H” level. As a result, the N channel transistor 3228 becomes active. Therefore, node P6 assumes VNL.
The negative polarity level shift circuit 322, which has a two-stage configuration, has a long delay time. Therefore, as described above, the delay circuit 3221 may be provided so as to obtain a delay time in the positive polarity level shift circuit 321 equal to that in the negative polarity level shift circuit. Although, the level shift can be also conducted by using a converter, it is not always suitable for liquid crystal displays and other portable electronic devices as a stationary current flow in the converter and power consumption therein is high.
The high-voltage level shift circuit 323 is shown in greater detail in
When color display is conducted, one display element is composed of three pixels (dots) of RGB. Therefore, the three dots of RGB constitute a unit of display color. In the dot reverse drive system, as shown in
The operation of each switch will be explained below by using the timing chart shown in
First, data lines R1 and G1 will be explained as an example in order to simplify the explanation. When a polarity signal POL is “L” in the (k−1)-th horizontal period, the picture signal switching circuit 314 is in the switch state shown in
When the polarity signal POL is “H” in the (k−1)-th horizontal period, the picture signal switching circuit 314 is in a switch state shown in
Though the explanation above was with respect to the data lines R1 and G1, the positive polarity or negative polarity signal corresponding to the picture signals DB1 and DR2 are outputted to the data line B1 and data line R2, and the positive polarity or negative polarity signal corresponding to the picture signals DG2 and DB2 is outputted to the data line G2 and data line B2. Each signal processing operation is identical to the operation explained with respect to the above-described R1 and G1.
In the period in which the latch signal STB is “H”, the pre-charge switch 333 is switched ON, the switches 331 and 332 are switched OFF and the output terminals are short circuited to the VM. The VM is a medium voltage of VPH and VNL, however, if the medium voltage of VPH and VNL is GND, then short circuiting may be conducted to GND. The terminals are thus short circuited and the supply of voltage exceeding the breakdown voltage to the D/A conversion circuits is prevented.
More specifically, if we assume that a positive polarity signal was supplied to the data line in the (k−1)-th horizontal period, then a negative polarity signal is supplied by the negative polarity D/A conversion circuit 24 in the k-th horizontal period, however, the data line holds the voltage of positive polarity. Therefore, the voltage exceeding the breakdown voltage is instantaneously supplied to the negative polarity D/A conversion circuit 24. As a result, in the most unfavorable case, the negative polarity D/A conversion circuit composed of medium voltage elements will be destroyed. Accordingly, the data lines are pre-charged to VM and then the data lines are driven by the negative polarity D/A conversion circuit 24 so as to prevent the application of voltage exceeding the voltage breakdown to the negative polarity D/A conversion circuit 24. The same is applied to the positive polarity D/A conversion circuit.
In the present embodiment, the picture signals that were level shifted to a positive polarity and negative polarity are inputted into the positive polarity drive circuit 10 and negative polarity drive circuit 20. Therefore, the level shift circuit corresponding to each data line, as in the conventional systems, is unnecessary. The number of level shift circuits for conducting level shift at the stage prior to inputting the signals generated in the signal processing circuit 31 into the positive polarity drive circuit 10 and negative polarity drive circuit 20 is equal to the number of control signals multiplied by two and becomes 40×2=80 at least for one clock signal CLK, one start signal STH, picture signals D×36, one latch signal STB, and one polarity signal POL. In the conventional data line drive circuits, when the number of pixels was QVGA (240 RGB×320), the number of the level shift circuits was equal to the product of the number of data lines and the bit number, n, of the picture signals and, therefore, 240×3×6=4320 circuits were required. By contrast, in accordance with the present invention, this number can be reduced to 80/4320=about 1/54.
Further, in the conventional switching circuit 64, the number of switching circuits was a product of the number of data lines and the bit number of picture signals. However, in accordance with the present invention, the number of switching circuits in the picture signal switching circuit 314 is equal to the bit number of picture signal. Therefore, the number of switching circuits is reduced to 1/(number of data lines). Furthermore, in accordance with the present invention, even if the number of pixels changes, the number of level shift circuits does not change. Therefore, the above-described effect increases with the increase in the number of pixels.
In accordance with the present invention, the elements such as transistors in the shift register circuit, data register circuit, and data latch units increase in size. Therefore, the element surface area of those circuit units increases. However, because the effect obtained due to elimination of the switching circuit A and level shift circuit with a large element surface area is much larger, the chip surface area can be reduced.
In the present embodiment, the con voltage was considered as a low-level voltage of the power source circuit or GND. As a result, a circuit for generating the com voltage is unnecessary. Therefore, the circuitry scale of the power source circuit 8 can be reduced. In the power source circuit 8, VDC1 voltage (2.5V) is generated based on supplied the VDC voltage, 2×VDC1 (VDD2) is generated with a voltage step-up circuit, and VPH is generated from VDD2. −2×VDC1 (VSS2) is obtained from the 2×VDC1 by inverting with a diode, a switch, and a capacitor. VNL is generated from VSS2. In the conventional system, a two-stage voltage increase was used for generating 5V from 2.5V and then generating 10V from 5V. However, in accordance with the present invention, because the com voltage is set to GND, one-stage voltage increase from 2.5V to 5V is conducted. Therefore, the power source efficiency is 80% and better than 64% of the conventional system. As a result, power consumption is reduced.
An example of fabricating the data line drive circuit 1 in accordance with the present invention with a semiconductor fabrication apparatus will be explained hereinbelow. In accordance with the present invention, an example of manufacturing by a diffusion process of a low-voltage element (2.5 V), medium-voltage element (5 V), and high-voltage element (10V) will be explained. The voltages in the parentheses hereinabove are merely example voltages, and other voltages may be employed as long as it is satisfied that low voltage<medium voltage<high voltage.
In the device elements such as transistors in semiconductor circuits, the element surface area is known to increase with the increase in voltage. The following relationship is valid between the minimum gate length Lmin, gate width Wmin, and gate oxide film thickness Tox: Lmin (2.5 V)<Lmin (5 V)<Lmin (10 V), Wmin (2.5 V)<Wmin (5 V)<Wmin (10 V), Tox (2.5 V)<Tox (5 V)<Tox (10 V). Therefore, the chip size can be reduced by employing a circuit configuration in which the employment of high-voltage elements is reduced to a minimum. In the present embodiment, the high-voltage elements are formed only in parts of the switching circuit 33 and level shift circuit 32 and the chip size can be reduced.
In the present embodiment, the signal processing circuit 31 was fabricated from low-voltage elements, the positive polarity drive circuit 10 and negative polarity drive circuit 20 were fabricated from medium-voltage elements, and parts of the switching circuit 33 and level shift circuit 32 were fabricated from high-voltage elements. When the threshold voltage of liquid crystals is as low as 3 V, the signal processing circuit 31, positive polarity drive circuit, and negative polarity drive circuit may be fabricated from medium-voltage (3 V) elements and parts of the switching circuit 33 and level shift circuit 32 may be fabricated form high-voltage (6 V) elements.
The substrate (P-sub) voltage is at a minimum voltage VNL=−5V, the signal processing circuit 31 is fabricated on the N-well-4, the positive polarity drive circuit 10 is fabricated on the N-well-3, the negative polarity drive circuit 20 is fabricated on the N-well-2, and parts of the switching circuit 33 and level shift circuit 32 are fabricated on the P-sub and N-well-1. In the semiconductor circuit device, device elements other than transistors, for example, resistors, capacitors, and diodes are present, and voltage resistance of those elements is also ensured.
As shown in
The spacing between N-well of different voltages has to be several tens of microns and, as shown in
In the arrangement shown in
In the arrangement shown in
In Embodiment 1, the signal generated by the signal processing circuit 31 is inputted into the positive polarity drive circuit 10 and negative polarity drive circuit 20 via the level shift circuit 32, however, because the inputted signal is a level-shifted voltage, the consumption of power in the picture signal bus is increased. However, as shown in
The data inversion circuit 315 comprises a circuit for latching and comparing previous data with next data for each picture signal, a circuit for inverting the picture signal according to the comparison results, and a circuit for generating a video inverted signal INV. The data inversion circuit 315, according to the majority operation, compares the previous data and data subsequent thereto and sets the image inverted signal INV to 0 when more than half of bits are inverted and sets the image inverted signal INV to 1 when the number of inverted bits is equal to or less than half. Further, in the present embodiment, the circuits of the initial stage of the data register circuits 12, 22 are exclusive logical circuits.
For example, when the picture signal is a 6-bit signal, if the previous data is 000011 and the next data is 111111, the picture signal with 4 bits of the 6 bits is inverted. Therefore, power consumption is inhibited by inverting 2 bits and obtaining 000000, rather than by inverting 4 bits and obtaining 111111. Accordingly, the video inverted signal INV is set to 0 and the picture signal inputted into the positive polarity level shift circuit 321 or negative polarity level shift circuit 322 is inverted to 000000 and inputted into the positive polarity data register circuit 12 or negative polarity data register circuit 22. Further, the picture signal is inverted to 111111 and latched according to the video inverted signal INV in the positive polarity data register circuit 12 or negative polarity data register circuit 22.
If the previous data is 000011 and the next data is 110011, only a picture signal of 2 bits of the 6 bits is inverted. Therefore, the procedure is inverted with respect to the above-described one. The video inverted signal INV is set to 1 and the picture signals inputted into the positive polarity level shift circuit 321 or negative polarity level shift circuit 322 is inputted “as is” as 110011. The picture signal is latched as 110011 according to the video inverted signal INV in the positive polarity data register circuit 12 or negative polarity data register circuit 22.
The consumed power is cv2f (c: capacitance, v: voltage amplitude, f: frequency). The capacitance c is almost doubled by changing the data register circuits from low-voltage elements to high-voltage elements. Furthermore, the voltage amplitude v is also doubled from 2.5V to 5V. Therefore, power consumption is increased by a maximum factor of 8. However, when 3 bits of the 6 bits are inverted with the data inversion circuit 315, the maximum power consumption is reduced to a four-fold increase. In the case of the same color over the entire screen, e.g., white color or black color, the picture signal does not change. Therefore, the power consumption is 0. With a 1-bit checked pattern, only the video inverted signal INV is inverted. Therefore, the power consumption is increased by a facture of 8/6=1.3. With the text information, a large number of black symbols are present against the white background. Therefore, the maximum increase factor is not more than about 1.3. Moreover, from the standpoint of the entire liquid crystal display device, the entire power consumption is that for driving the data lines 4 and scanning lines 5 and that in the D/A conversion circuits of the data line drive circuits, and the power consumption in the picture signal bus is at maximum less than 10% based on the entire power consumption. For this reason, even if the power consumption of the picture signal bus is increased by a factor of 1.3, the increase for the entire device is less than 3%. Setting the com voltage to GND improves the efficiency of the power source circuit of the drive system from 64% to 80%. Therefore, power consumption is reduced despite the cancellation.
With such a circuitry, the level shift circuit of the first stage and the level shift circuit of the second stage are fabricated on different N-well.
In Embodiments 1 through 3, the pre-charge switch 333 was provided after the switch 331 and switch 332 that are switching circuit. Therefore, one pre-charge switch 333 handles both a positive polarity voltage and a negative polarity voltage. As a result, the pre-charge switch 333 must be configured with high-voltage elements. In the present embodiment, a positive polarity pre-charge switch and negative polarity pre-charge switch are provided between the positive polarity drive circuit and the switching circuit and between the negative polarity drive circuit and the switching circuit, respectively, so that the pre-charge switches can be fabricated from medium-voltage elements by preparing pre-charge circuits for positive polarity and negative polarity and the circuit scale can be further reduced. In the present embodiment, some components have a location different from that explained in Embodiment 1 by using
Further, each state shown in
As described above, before the switch 331 and switch 332 are switched OFF, the pre-charge switch 145 and pre-charge switch 245 are switched ON. As a result, the voltage applied to the output terminals (data lines) of the D/A conversion circuit 14 and D/A conversion circuit 24 is short circuited to the VPL or VNH, respectively (pre-charging). Therefore, the control is so conducted that the voltage exceeding the breakdown voltage is not applied to the D/A conversion circuit 14 and D/A conversion circuit 24. Because the pre-charge switch 145 and pre-charge switch 245 may correspond to the positive polarity and negative polarity voltage, respectively, they can be fabricated from medium-voltage elements rather than high-voltage elements and the circuitry scale can be reduced. Further, the VPL and VNH can be at a system GND.
In Embodiments 1 through 4, the digital picture signals that were inputted in serial are expanded and held as digital signals in parallel with the data register circuits and data latch circuits. In the present embodiment, an example will be explained in which the digital picture signals that were inputted in serial are converted into analog picture signals and those analog picture signals are expanded and held in sample and hold circuits to drive the data lines. With such a configuration, the number of data lines (n data lines were required in the case of n-bit digital signals) can be reduced to one analog data line. Therefore, the number of data lines can be decreased and, therefore, the circuitry scale can be reduced.
The switches 161, 261, capacitors 162, 262, and amplifiers 163, 263 are fabricated from medium-voltage elements. The switches 161, 261 are switched by the sampling signal SMP imputed from the shift register circuits 11, 21. Furthermore, the switches 334, 335, 336 constituting the switching circuit 33 are fabricated from high-voltage elements. The switch 334 outputs a positive polarity analog picture signal, the switch 335 outputs a negative polarity analog picture signal, and the switch 336 is pre-charged to GND so that a voltage exceeding the operation voltage is not applied to the positive polarity amplifier 163 and negative polarity amplifier 263. In Embodiments 1 thorough 4, the switching circuit 33 selected the positive polarity and negative polarity analog picture signals by being commonly used by the two output terminals, however, in the present embodiment, swatches 334, 335, 336 are provided for each output terminal.
The problem associated with the above-described configuration, in which two amplifiers (voltage followers) 163, 263 are connected to one output terminal, is that thin vertical lines are displayed due to the variation of the offset voltage of the amplifier. For this reason, the offset voltage of the amplifier has to be cancelled between the frames. Accordingly, a switching circuit for switching differential inputs (inverted input, non-inverted input) shown in
The input switching circuit 1631 comprises four switches 1631a-d, and the input signal to the differential amplification stage 1632 and feedback from the output are connected to one respective transistor of the differential pair. In the configuration shown in the figure, the switches 1631b, d are switched ON, the switches 1631a, c are switched OFF, the input signal is inputted into the NMOS transistor 1632b, and the output is feedback supplied to the NMOS transistor 1632a. The switch 1636a of the switching circuit 1636 is ON, the switch 1636b is OFF, the switch 1633a of the output switching circuit 1633 is ON, and the switch 1633b is OFF. When the input switching circuit 1631 is switched and the differential input is switched, all the switches of the output switching circuit 1633 and switching circuit 1636 are switched. Thus, the variation of the offset voltage of the amplifier can be prevented by switching the differential input.
The positive polarity D/A conversion circuit 17 and negative polarity D/A conversion circuit 27, as shown in
The latch circuit 317 comprises latch elements corresponding to each latch element of the latch circuit 316, and the output from the latch circuit 316 is latched by the latch circuit 317 according to CK3. The latch circuit 317 latches at the same time the picture signals of the first display element (DR1, DG1, DB1) and the picture signals of the second display element (DR2, DG2, DB2). Other structural elements are identical to the elements that have already been explained. Because the data line drive circuit device in accordance with the present invention is of a dot inversion system, the polarity of the adjacent output terminals is inverted. This is made possible by the sampling signal SMP that is inputted from the shift register circuits 11, 21 and level shift circuit 32 to the sample and hold circuits 16, 26. As shown in
In
In the example shown in
When the number of pixels is large, it is preferred that the number of D/A conversion circuit elements be increased as shown in
Similarly, the negative polarity D/A conversion circuit 27 comprises two D/A conversion circuit elements correspondingly to each RGB. More specifically, it comprises an amplifier 2711 and a decoder 2741 and an amplifier 1722 and a decoder 2742 for the R. The outputs of the amplifier 2711 and amplifier 2712 are selectively outputted to the outside by the switching circuit 277. Furthermore, there are provided an amplifier 2721 and a decoder 2751 and an amplifier 2722 and a decoder 2752 for G. The outputs of the amplifier 2721 and amplifier 2722 are selectively outputted to the outside by the switching circuit 278. Furthermore, there are provided an amplifier 2731 and a decoder 2761 and an amplifier 2732 and a decoder 2762 corresponding thereto for B. The outputs of the amplifier 2731 and amplifier 2732 are selectively outputted to the outside by the switching circuit 279. The connection relationship of each amplifier and output line follows the rule similar to that of the D/A conversion circuit 17.
For example, in the case where a signal is outputted to the X1 line, the signals (R1_P, G1_N, B1_P, R1_N, G1_P, B1_N, R2_P, G2_N, B2_P, R2_N, G2_P, B2_N) are outputted into the (Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9, Y10, Y11, Y12), respectively. When the polarity is inverted for each line or each frame, the P, N of output polarity of each terminal is switched. In other words, the signals (R1_N, G1_P, B1_N, R1_P, G1_N, B1_P, R2_N, G2_P, B2_N, R2_P, G2_N, B2_P) are outputted into the (Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9, Y10, Y11, Y12), respectively. Switching of the outputs to each line is determined by each switching circuit. Thus, in one line, two D/A conversion circuit elements of the same polarity and same color output the signals alternately. The offset voltage of the amplifier can be dispersed in time and the occurrence of display defects can be prevented by preparing a plurality of D/A conversion circuit elements of the same color and same polarity and providing the switching circuits so that the D/A conversion circuit elements alternately output signals in the same line. Three or more D/A conversion circuit elements can be provided for each same polarity and same color. In this case, too, the D/A conversion circuit elements output the signals in turn (cyclically). At this time, the differential input (inverted input, non-inverted input) may be changed in each amplifier, as shown in
The timing chart is shown in
When a positive polarity analog picture signal is outputted from Y1 and a negative polarity analog picture signal is outputted from Y2 as the X1 line in the first period shown in
Switching from the first period to the second period is conducted according to the sampling signal SMP. Synchronization with the sampling signal SMP may be also conducted with respect to pre-charging with the switch 336. If switching is conducted to the second period, as shown in
Furthermore, the pre-charging voltage was set to a system ground GND, however, it may be also the low-level voltage VPL of the positive polarity drive circuit or a high-level voltage VNH of the negative polarity drive circuit, rather than the system ground GND.
In the present embodiment, the following was set: VPL=VNH=GND. With such a configuration, analog picture signals, rather that n-bit digital picture signals, can be used. Though the number of data lines (data buses) of the n-bit digital picture signals is n, if the D/A conversion is conducted, then analog picture signals on a line are obtained. Therefore, power consumption of the D/A conversion circuits for driving the data lines is 1/n compared to the processing of digital picture signals. Furthermore, because the number of data lines is decreased, the circuitry scale can be reduced.
As described hereinabove, with the present embodiment, it is possible to provide a data line drive circuit device for a liquid crystal display device in which the circuitry scale and power consumption are further decreased.
In this embodiment, an example will be described in which the con voltage is set to a voltage value different from GND intentionally, considering the feed-through error occurred at a TFT element. The feed-through error is an error which occurs due to a parasitic capacitor of a gate electrode and through which the variation of the input signal to the gate electrode affects the output signal. Specifically, when the TFT element is changed to the hold state, a scanning signal inputted to the gate electrode from the scanning line 5 affects the voltage of the pixel electrode.
The voltage of a pixel electrode changes according to scanning line voltage variation due to a parasitic capacitor between the gate electrode and the drain electrode (pixel electrode) of a TFT element. This voltage change is the feed-through error. While the reference voltage of the drive circuit and the con voltage are GND in the embodiment 1 through embodiment 5, the com voltage is, when considering the feed-through error, set to a voltage value different from GND to compensate the feed-through error.
Here, since the value of the feed-through error varies from panel to panel, it is necessary to adjust the com voltage for every panel. Since the feed-through error tends to occur at the negative side for N-type TFT elements, the reference voltage of the drive circuit is set to GND and the com voltage is set to a DC voltage which is lower than GND and higher than the low voltage of the negative drive circuit. On the other hand, since the feed-through error tends to occur at the positive side for P-type TFT elements, the reference voltage of the drive circuit is set to GND and the com voltage is set to a DC voltage which is higher than GND and lower than the high voltage of the positive drive circuit. These settings allow the com voltage to compensate the feed-through error occurred at the TFT element. The operation voltages of the data line drive circuit 1 are adjusted in accordance with the con voltage.
For N-type TFT elements, the feed-through error is −1V, the con voltage is −1V, VPH is 5V, VNL is −5V, for example. For N-type TFT elements, the feed-through error is −1V, the com voltage is 1V, VPH is 5V, VNL is −5V, for example. The adjusting amount of the con voltage for the feed-through error is in ±2V range, for example. As most liquid crystal displays uses N-type TFT elements, the liquid crystal display with N-type TFT elements will be described below as an example.
The con voltage is generated by the com voltage generation circuit 9. The con voltage generation circuit 9 may be configured using a simple circuit consisting of a resistor divider circuit connected between GND and VNL and bypass capacitors connected at nodes between the resistors. The con voltage can be adjusted by changing the resistance of the resistor divider circuit.
As describe above, this embodiment can provide a data line drive circuit for a LCD capable of compensating the affection of the feed-through error and limiting the increase of the circuit scale.
It is apparent that the present invention is not limited to the above embodiment and it may be modified and changed without departing from the scope and spirit of the invention. For example, the present invention was explained hereinabove with respect to a data line drive circuit as an example and each circuit can be fabricated on a silicon substrate, a glass substrate, or a plastic substrate.
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