Drive Circuit for Generating a Delay Drive Signal

Abstract

A drive circuit includes a drive unit coupling with data lines for receiving at least one clock signal and a first enable signal to generate a drive signal to drive data lines, and a delay unit electrically coupled with the drive unit for receiving the clock signal and the first enable signal and generating a second enable signal falling subsequent to the first enable signal in a predetermined time interval.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects and many of the attendant advantages of this invention are more readily appreciated and better understood by referencing the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

FIG. 1 is a top view of a liquid crystal display;

FIG. 2 is a schematic diagram of a scan signal delay phenomenon;

FIG. 3 illustrates a drive waveform for resolving the scan signal delay phenomenon;

FIG. 4 illustrates a top view of a liquid crystal display according to the present invention;

FIG. 5 illustrates a relationship diagram of the data signal and the scan signal of the present invention;

FIG. 6 illustrates the enable signal waveform generated by one of the column direction drive integrated circuits after this drive integrated circuit is triggered by a start signal from its previous stage drive integrated circuit;

FIG. 7 illustrates the schematic circuit structure of the column direction drive integrated circuit according to the present invention;

FIG. 8 is a detailed circuit diagram of the delay control circuit;

FIG. 9 illustrates a detailed circuit diagram of the delay control circuit according to another embodiment; and

FIG. 10 illustrates a schematic diagram of this delay control circuit 900 being integrated into a drive integrated circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 4 illustrates a top view of a liquid crystal display according to an embodiment of the present invention. The liquid crystal display comprises a panel 400 formed in a substrate (not shown in this figure), row direction drive integrated circuits Y1, Y2 . . . Yn, column direction drive integrated circuits X1, X2 . . . Xn, a timing controller 404, a gray level voltage generator 406 and a DC to DC converter 408. The row direction drive integrated circuits Y1, Y2 . . . Yn are used to generate scan signals to drive scan lines. The column direction drive integrated circuits X1, X2 . . . Xn are used to generate data signals to drive data lines. The timing controller 404 is used to generate a standard timing to the row direction drive integrated circuits Y1, Y2 . . . Yn and the column direction drive integrated circuits X1, X2 . . . Xn. The gray level voltage generator 406 is used to generate a gray level voltage. This gray level voltage is supplied to the column direction drive integrated circuits X1, X2 . . . Xn. The DC/DC converter 408 provides power to the the row direction drive integrated circuits Y1, Y2 . . . Yn, the column direction drive integrated circuits X1, X2 . . . Xn and the gray level voltage generator 406.

The power generated by the DC/DC converter 408, the gray level voltage generated by the gray level voltage generator 406 and the standard timing generated by the timing controller 404 are sequentially, cascade type, transferred to the column direction drive integrated circuits X1, X2 . . . Xn to display image in the panel 400.

According to the present invention, a time difference can adjust among the data signals in the column direction. This time difference is used to compensate the delay of the scan signal in a scan line. Such compensation may prevent the transistors connected to adjacent scan lines are turned on together. This compensation method is described in the following. FIG. 5 illustrates a relationship diagram of the data signal and the scan signal of the present invention.

As shown in FIG. 3, a signal 301 is used to cause a time difference between two scan signals from two adjacent scan lines. Such time difference of scan signals may prevent the two transistors respectively connected to the remote end of one scan line and connected to the remote end of an adjacent scan line being turned on together.

FIG. 5 illustrates a relationship diagram between the scan signal and the data signal according to the present invention. Only two trigger signals 501 and 502 are illustrated in this figure. The two trigger signals 501 and 502 are used to trigger the first column direction drive integrated circuits X1 and the last column direction drive integrated circuits Xn respectively. Therefore, a time difference exists between the two data signals that are generated by the two drive integrated circuits respectively. It is noticed that a lot of trigger signals still exist between the two trigger signals 501 and 502 to trigger the other column direction drive integrated circuits.

FIG. 6 illustrates the enable signal waveform generated by one of the column direction drive integrated circuits after this drive integrated circuit is triggered by a enable signal from its previous stage drive integrated circuit. This enable signal is transferred to and triggers the next stage of the drive integrated circuit. Please refer to the FIG. 6 and FIG. 4 together. According to the present invention, each signal is sequentially transferred to the column direction drive integrated circuits X1, X2 . . . Xn. Therefore, the enable signals are also sequentially generated by the column direction drive integrated circuits X1, X2 . . . Xn. The waveform 600 is a standard clock signal generated by the timing controller 404. The signal W1 is a enable signal for the column direction drive integrated circuits X1 to charge or discharge the storage capacitor. After the drive integrated circuits X1 receives the enable signal W1, a enable signal W2 that falls behind the enable signal W1 is generated by the drive integrated circuits X1. The enable signal W2 is used to enable the column direction drive integrated circuits X2 to charge or discharge the storage capacitor. After the drive integrated circuits X2 receives the enable signal W2, a enable signal W3 that falls behind the enable signal W2 is generated by the drive integrated circuits X2. The enable signal W3 is used to enable the column direction drive integrated circuits X3. The rest may be deduced by analogy. The interval between any two adjacent start signals may be set by users to match the delay of the scan signals.

Referring to FIG. 5 again, the scan signal in the starting side of a scan line is the scan signal 503. The scan signal in the remote end of a scan line is scan signal 504. A time difference exists between the two scan signals 503 and 504. In this present invention, two corresponding column direction drive integrated circuits are respectively triggered based on this time difference. In an embodiment, the enable signal 501 is used to trigger the first column direction drive integrated circuits X1 for generating corresponding data signals. The column direction drive integrated circuits Xn-1 generates the enable signal 502. This enable signal 502 is used to trigger the last column direction drive integrated circuits Xn for generating the data signal 505 as shown in this FIG. 5.

According to this embodiment, the data signals generated by the column direction drive integrated circuits match the delay of the scan signal. That is the timing to turn on the thin film transistors connected with this scan line and the timing to send out the data signal from the column direction drive integrated circuits are the same. Therefore, the data signal may completely charge the storage capacitor through the corresponding thin film transistor. Such a method may resolve the problem of the storage capacitor being insufficiently charged because the connected thin film transistor is not turned on completely. On the other hand, the column direction drive integrated circuits are sequentially triggered. The timing for turning on the transistors may match the timing for triggering the corresponding column direction drive integrated circuit. Therefore, the storage capacitors may be completedly charged. In other words, it is not necessary to wait for a long interval to send the scan signal to the next scan line to prevent the transistors connected to the adjacent scan line being turned on together. Therefore, the interval between two scan signals respectively being sent to two adjacent scan lines is reduced.

On the other hand, a large instant current from a power source is happened when enable all the column direction drive integrated circuits on the panel in an instant. Such large inrush currents may cause the power source to have a large voltage drop. Such a large voltage drop may cause the voltage divider to divide mistake gray level voltage. However, the method provided by the present invention can also resolve the foregoing problem. By sequentially enable the column direction drive integrated circuits to drive the data line, it is not necessary to provide a large instant current from the power source.

FIG. 7 illustrates the schematic circuit structure of the column direction drive integrated circuit 70 according to the present invention. The column direction drive integrated circuit 70 includes a drive unit 700 and a delay control circuit 710. The drive unit 700 is used to output drive signals Y1, Y2 . . . Yn to the data lines connected with the column direction drive integrated circuit 70. The delay control circuit 710 is used to generate the enable signal to the next stage column direction drive integrated circuit 70. According to the present invention, the enable signal is delayed for a predetermined interval by the delay control circuit 710. Then, this delayed enable signal is transferred to and triggers the next stage column direction drive integrated circuit.

The drive unit 700 includes a shift register 701, a data register 702, a data latch 703, a voltage transformer 704, A D/A converter 705 and an output buffer 706. The digital display signal from the RGB pins 707 is sent to and stored in the data register 702. The timing for storing each pixel data is based on the clock signal. The shift register 701 controls the pixel data stored in the data register 702. When the the pixel data fills up the data register 702, a drive signal from the pin 708 turn on the data latch 703. In one embodiment, if the drive unit 700 is the column direction drive integrated circuit X1, the drive signal is the drive signal W1 in FIG. 6. After the data latch 703 is turned on, the pixel data is transferred to the voltage transformer 704 to amplifier the voltage swing. Then, this pixel data is transferred to the D/A converter 705 to convert to an analog signal based on the reference voltage sent from the pin 709. Finally, the analog signal is used to drive the panel through the output buffer 706.

In a prefer embodiment of the present invention, an additional delay control circuit 710 is embedded in the column direction drive integrated circuit 70, as shown in FIG. 7, to couple with the drive unit 700. The delay control circuit 710 is used to generate a delay drive signal. According to the present invention, a control signal from the pin 711 is used to control the delay control circuit 710. This control signal may control the delay control circuit 710 to generate a delay drive signal based on the clock signal from the pin 712 and the enable signal from the pin 708. The delay enable signal is outputted from the pin 713.

FIG. 8 is a detailed circuit diagram of the delay control circuit 710. The delay control circuit 710 includes a control circuit 7101 and a delay device 7012. The delay device 7102 includes a delay circuit 7103 and switches S₁, S₂, S₃ . . . S₂^P coupled with the delay circuit 7103. The control circuit 7101 is controlled by a control signal from the pin 711 of the column direction drive integrated circuit. This control signal may control the control circuit 7101 to output switch signals O₁, O₂, O₃ . . . O₂^P to switch the switches S₁, S₂, S₃ . . . S₂^P respectively. The delay device 7102 receives the clock signal from the pin 712 and the enable signal from the pin 708 of the column direction drive integrated circuit. The delay device 7102 generates a delay enable signal based on the clock signal, the enable signal and the switch of the switches S₁, S₂, S₃ . . . S₂^P. This delay enable signal is outputted from the pin 713. The delay time of the delay enable signal is related to the clock signal. In an embodiment, the control signals from the pin 711 is formed by different voltages. For example, the number of the different voltages is P. In this case, the control circuit may generate 2^P switch signals to switch the switches S₁, S₂, S₃ . . . S₂^P of the delay device 7102 to set the delay time of the delay enable signal. This delay time is a multiple of the period of the clock signal. The control circuit 7101 is a multiplexer in an embodiment.

It is noticed that, in the foregoing embodiment, the setting of the delay time is based on the drive integrated circuit. In another embodiment, the setting of the delay time is also based on the signal data line or based on a plurality of data lines.

FIG. 9 illustrates a detailed circuit diagram of the delay control circuit 900 according to another embodiment. In this embodiment, the setting of the delay time is based on a plurality of data lines. A column direction drive integrated circuit may drive n data lines. This delay control circuit 900 has m delay devices 7102. The number m is less than the number n. Each delay device 7102 may receive the clock signal from the pin 712 of the column direction drive integrated circuit. The first delay device 7102 receives the enable signal from the pin 708. As described in the foregoing paragraph, this enable signal is delayed to form a delay enable signal 9011. This delay enable signal 9011 is outputted from the first delay device to the next delay device. The rest may be deduced by analogy to respectively generate the delay enable signal 9012, . . . 901m to the output buffer 706. This delay enable signal 901m not only transfers to the output buffer 706 but also transfers to the next stage drive integrated circuit as a enable signal.

FIG. 10 illustrates a schematic diagram of this delay control circuit 900 being integrated into a drive integrated circuit. Please refer to the FIG. 9 and FIG. 10. These enable signals 9012, . . . 901m generated by the delay control circuit 900 are transferred to the output buffer 706 to generate corresponding drive signals to the data lines.

Accordingly, in one embodiment of the present invention, the data lines are sequentially driven by the drive signals generated by the column direction drive integrated circuits. That is, the drive signals are sequentially generated to match the scan signal delay in a scan line. Therefore, the timing to turn on the thin film transistors connected with this scan line and the timing to send out the data signal from the column direction drive integrated circuits are the same. Therefore, the data signal in the data line may completely charge the corresponding storage capacitor through the thin film transistor. Therefore, it is not necessary to use a long interval between two scan signals to ensure the transistors respectively connected to adjacent two scan lines not being turned on together.

A control signal is issued to control the delay control circuit to determine the delay time of the output signal. The delay time is related to the clock signal.

As is understood by a person skilled in the art, the foregoing descriptions of the preferred embodiment of the present invention are an illustration of the present invention rather than a limitation thereof. Various modifications and similar arrangements are included within the spirit and scope of the appended claims. The scope of the appended claims should be accorded to the broadest interpretation so as to encompass all such modifications and similar structures.

Claims

1. A drive circuit for driving a liquid crystal display having a plurality of data lines, comprising: a drive unit, electrically coupled with the data lines, for receiving at least one clock signal and a first enable signal to generate a drive signal to drive the liquid crystal display; anda delay unit, electrically coupled with the drive unit, for receiving the clock signal and the first enable signal and for generating a second enable signal in response to a control signal subsequent to the first enable signal in a predetermined time interval.

2. The drive circuit of claim 1, wherein the drive unit comprises: a shift register;a data register, electrically coupled with the shift register, for storing pixel data;a data latch, electrically coupled with the data register, for latching the pixel data transferred from the data register;a digital-to-analog (D/A) converter, electrically coupled with the data latch, for converting the pixel data to an analog signal; andan output buffer, electrically coupled with the D/A converter, for receiving the analog signal to drive the liquid crystal display.

3. The drive circuit of claim 1, wherein the delay unit comprises: a control circuit for receiving the control signal to generate a plurality of switch signals; andat least one delay device, electrically coupled with the control circuit, for receiving the clock signal, the first enable signal, and the switch signals, wherein delay device comprises a plurality of switches and a delay circuit related to a predetermined delay time, and the switch signals are adopted to switch the switches to select a delay time for outputting the second enable signal.

4. The drive circuit of claim 3, wherein the control circuit comprises a multiplexer.

5. The drive circuit of claim 3, wherein the delay time is a multiple of the period of the clock signal.

6. A circuit structure for driving a liquid crystal panel having a plurality of data lines, comprising: a plurality of drive circuits electrically coupled with the data lines, wherein the drive circuits are located in one side of the liquid crystal panel and connected in series, each drive circuit comprising: a drive unit, electrically coupled with the data lines, for receiving a clock signal and a first enable signal to generate a drive signal to drive the liquid crystal panel; anda delay unit, electrically coupled with the drive unit, for receiving the clock signal and the first enable signal and for generating a second enable signal subsequent to the first enable signal in an interval.

7. The circuit structure of claim 6, wherein the drive unit comprises: a shift register;a data register, electrically coupled with the shift register, for storing pixel data;a data latch, electrically coupled with the data register, for latching the pixel data transferred from the data register;a digital-to-analog (D/A) converter, electrically coupled with the data latch, for converting the pixel data to an analog signal; andan output buffer, electrically coupled with the D/A converter, for receiving the analog signal to drive the data lines.

8. The circuit structure of claim 6, wherein the delay unit comprises: a control circuit for receiving the control signal to generate a plurality of switch signals; andat least one delay device, coupled with the control circuit, for receiving the clock signal, the first enable signal and the switch signals, wherein the delay device comprises a plurality of switches and a delay circuit related to a predetermined delay time, and the switch signals switch the switches to select a delay time for outputting the second start signal.

9. The circuit structure of claim 8, wherein the control circuit comprises a multiplexer.

10. The circuit structure of claim 8, wherein the delay time is a multiple of the period of the clock signal.

11. A method for driving a liquid crystal panel having a plurality of scan lines, a plurality of data lines, and a plurality of pixels spatially arranged in a matrix, wherein each pixel unit includes a thin film transistor having a gate electrode electrically connected to a scan line, and a source electrode electrically connected to a data line, the method comprising: sequentially driving the scan lines; anddriving the data lines, wherein in each pixel unit the scan line and the data line are driving simultaneously.