Patent Grant
8098226
The present invention relates to a pulse processing circuit typically used for a driver (drive circuit) for driving a display apparatus.
An i-th shift register circuit SR is connected to the OUTB of a level shifter LS in the same stage via its SB, and connected to the Q of the (i+2)-th shift register circuit SR (the second adjacent shift register circuit to the right of the figure) via its R, and also connected to an EN terminal of a level shifter LS provided in a (i+1)-th shift register circuit SR (the adjacent shift register circuit to the right of the figure) via its Q.
Further, the pulse processing circuit 905 includes a delay circuit corresponding to each shift register circuit SR. The buffer 920 includes a pre-charge buffer circuit BuP and a sampling buffer circuit BuS corresponding to each shift register circuit SR.
The pre-charge buffer circuit BuP outputs a pre-charge pulse, and the sampling buffer circuit BuS outputs a sampling pulse. For example, corresponding to the i-th shift register circuit SRb, the pulse processing circuit 905 includes a delay circuit 906 and a delay circuit 910, the pre-charge buffer circuit BuS includes an inverter circuit 918P which is a cascade two-stage circuit and an inverter 919P, and the sampling buffer BuS includes an inverter circuit 918S which is a cascade two-stage circuit and an inverter 919S. Note that, each of the delay circuits 906 and 910 is a cascade four-stage circuit. Note that, the inverter circuit 918P, the inverter circuit 918S, and the delay circuits 906 and 910 each have a single input terminal and a single output terminal.
The input of the delay circuit 906 is connected to the OUTB of the level shifter LSa (provided in the (i−1)-th shift register circuit SRa), and the output of the delay circuit 906 is connected to the input of the inverter circuit 918P and the input of the inverter 919P. Further, the input of the delay circuit 910 is connected to the Q of the flip-flop SR-FFb (provided in the i-th shift register circuit SRb), and the output of the delay circuit 910 is connected to the input of the inverter circuit 918s and the input of the inverter 919s. Here, as shown in
In general, the output of the shift register circuit SR has a blunt rise or a blunt return fall due to characteristic of the material transistor.
The following discusses a conventional structure with reference to
The present invention was made in view of the foregoing problems, and an object is to provide a particular structure and a method for a pulse generation circuit provided in a drive circuit or the like of a display apparatus, which can ensure high accuracy of pulse generation.
In order to attain the foregoing object, a drive circuit for a display apparatus according to the present invention comprises: a shift register; and a pulse generation circuit for generating a drive pulse signal using an output pulse signal generated in the shift register, wherein the pulse generation circuit forms (defines) a pulse-starting edge and a pulse-termination edge of the drive pulse signal using a rise or a fall of pulse resulting from activation of the output pulse signal.
Examples of the drive pulse signal include a pre-charge pulse and a sampling pulse.
The shift register includes plural stages of shift register circuit, each of which includes a flip-flop (such as a set-reset type flip-flop). Further, each shift register circuit may include a level shifter or various logic circuits. The output pulse signal is outputted from the output Q or the level shifter of the flip-flop provided in the shift register circuit.
Therefore, by constituting the shift register to generate pulses so that a rise of pulse resulting from activation of the output pulse signal is sharper than a subsequent fall of pulse, or a fall of pulse resulting from activation of the output pulse signal is sharper than a return rise of pulse (the design focusing more on the pulse-starting edge), the pulse width of the pre-charge pulse can be highly-accurately set. In this way, the problem of a decrease in driving (pre-charge or sampling) period due to uneven transistor characteristic, or inadequate driving timing (pre-charge or sampling timing) can be solved. On this account, display quality of the display apparatus is improved.
The drive circuit for a display apparatus according to the present invention may be arranged so that the drive pulse signal is generated from first and second output pulse signals, and the pulse-starting edge of the drive pulse signal is formed of the first output pulse signal, and the pulse-termination edge of the drive pulse signal is formed of the second output pulse signal.
The drive circuit for a display apparatus according to the present invention may be arranged so that the drive circuit for a display apparatus as set forth in claim 3, wherein the drive pulse signal is generated for each stage of the shift register, the first output pulse signal forming the pulse-starting edge of the drive pulse signal for a given stage is generated within the same stage or a preceding stage, and the second output pulse signal forming the pulse-termination edge of the drive pulse signal for a given stage is generated within the same stage or a later stage.
The drive circuit for a display apparatus according to the present invention may be arranged so that the pulse generation circuit includes a level shifter having an input terminal and a control terminal, the level shifter carries out level shift of a pulse signal fetched through the input terminal before outputting the pulse signal when the control terminal has a first potential, the level shifter outputs a signal of a certain potential when the control terminal has a second potential, the first output pulse signal being supplied to the input terminal and the second output pulse signal being supplied to the control terminal. In this case, the first and second output pulse signals may be respectively supplied to the input terminal and the control terminal via a level shift circuit which carries out level shift of a signal supplied thereto before outputting the signal. Further, the first and second output pulse signals may be respectively supplied to the input terminal and the control terminal via a delay circuit.
The drive circuit for a display apparatus according to the present invention may be arranged so that the pulse generation circuit includes a logic circuit, and the first and second output pulse signals are supplied to the logic circuit. In this case, the first and second output pulse signals may be respectively supplied to the logic circuit via a level shift circuit which carries out level shift of a signal supplied thereto before outputting the signal. Further, the first and second output pulse signals may be respectively supplied to the logic circuit via a delay circuit.
The drive circuit for a display apparatus according to the present invention may be arranged so that the drive pulse signal is a pre-charge pulse signal, and the first output pulse signal forming the pulse-starting edge of the pre-charge pulse signal is generated in a stage preceding to the given stage, and the second output pulse signal forming the pulse-starting edge of the pre-charge pulse signal is generated within the same stage.
The drive circuit for a display apparatus according to the present invention may be arranged so that the drive pulse signal is a sampling pulse signal, and the first output pulse signal forming the pulse-starting edge of the sampling pulse signal is generated within the same stage, and the second output pulse signal forming the pulse-starting edge of the sampling pulse signal is generated in a stage later than the given stage.
A drive circuit for a display apparatus according to the present invention comprises: a shift register; a pre-charge pulse generation circuit for generating a pre-charge pulse signal using an output pulse signal from the shift register; and a sampling pulse generation circuit for generating a sampling pulse signal using an output pulse signal from the shift register, wherein: the pre-charge pulse generation circuit forms a pulse-starting edge and a pulse-termination edge of the pre-charge pulse signal using a rise of pulse or a fall of pulse resulting from activation of the output pulse signal, and the sampling pulse generation circuit forms a pulse-starting edge and a pulse-termination edge of the sampling pulse signal using a rise of pulse or a fall of pulse resulting from activation of the output pulse signal.
The drive circuit for a display apparatus according to the present invention is preferably arranged so that the shift register is structured to generate pulses so that a rise of pulse resulting from activation of the output pulse signal is sharper than a return fall of pulse, or a fall of pulse resulting from activation of the output pulse signal is sharper than a return rise of pulse.
The drive circuit for a display apparatus according to the present invention may be arranged so that the pre-charge pulse generation circuit includes either a logic circuit, or a level shifter which carries out level shift of a pulse signal fetched through an input terminal before outputting the pulse signal when a control terminal has a first potential, the level shifter outputting a signal of a certain potential when the control terminal has a second potential, the sampling pulse generation circuit includes either a logic circuit, or a level shifter which carries out level shift of a pulse signal fetched through an input terminal before outputting the pulse signal when a control terminal has a first potential, the level shifter outputting a signal of a certain potential when the control terminal has a second potential.
The drive circuit for a display apparatus according to the present invention may be arranged so that the pre-charge pulse signal is generated from two output pulse signals, one of which forms the pulse-starting edge of the pre-charge pulse signal while the other forms the pulse-termination edge of the pre-charge pulse signal, the sampling pulse signal is also generated from two output pulse signals, one of which forms the pulse-starting edge of the sampling pulse signal while the other forms the pulse-termination edge of the sampling pulse signal.
The drive circuit for a display apparatus according to the present invention may be arranged so that the pre-charge pulse signal and the sampling pulse signal are generated for each stage of the shift register, the output pulse signal forming the pulse-starting edge of the pre-charge pulse signal for a given stage is generated in a stage preceding to the given stage, and the output pulse signal forming the pulse-termination edge of the pre-charge pulse signal for a given stage is generated within the same stage, the output pulse signal forming the pulse-starting edge of the sampling pulse signal for a given stage is generated within the same stage, and the output pulse signal forming the pulse-termination edge of the sampling pulse signal for a given stage is generated in a stage later than the given stage.
The drive circuit for a display apparatus according to the present invention may be arranged so that the pre-charge pulse generation circuit includes a first NOR circuit supplied with an output pulse signal generated in a stage preceding to the given stage and an output pulse signal generated in the given stage, the sampling pulse generation circuit includes (i) a NAND circuit supplied with an inversion pulse signal of an output of the first NOR circuit and an output pulse signal generated in the given stage, and (ii) a second NOR circuit supplied with an output of the NAND circuit and an output pulse signal generated in a stage later than the given stage.
A drive circuit for a display apparatus according to the present invention comprises: a shift register; and a pulse generation circuit for generating a drive pulse signal using an output pulse signal from the shift register, wherein the pulse generation circuit forms a pulse-starting edge and a pulse-termination edge of the drive pulse signal using a subsequent fall of the output pulse signal which has risen as being activated or a subsequent rise of the output pulse signal which has fallen as being activated. In this case, the shift register is structured to generate pulses so that a rise of pulse resulting from activation of the output pulse signal is sharper than a return fall of pulse, or a fall of pulse resulting from activation of the output pulse signal is sharper than a return rise of pulse.
A drive circuit for a display apparatus according to the present invention comprises: a shift register constituted of a plurality of stages, for driving a display apparatus which carries out writing of data into a data signal line and pre-charging of a predetermined data signal line at a stage later than said data signal line, wherein: each stage of the shift register outputs a pulse signal, the shift register generates a rise of a pre-charge pulse for pre-charging an n-th data signal line, in response to a fall of a pulse signal outputted from a stage preceding to the n-th stage of the shift register as a result of activation of the pulse signal, and generates a fall of the pre-charge pulse in response to a rise of a pulse signal outputted from a stage later than the n-th stage of the shift register as a result of activation of the pulse signal. In this case, the drive circuit may generate a rise of a sampling pulse for writing data into an n-th data signal line, in response to the return fall of the pre-charge pulse.
A drive circuit for a display apparatus according to the present invention comprises: a shift register constituted of a plurality of stages, for driving a display apparatus which carries out writing of data into a data signal line and pre-charging of a predetermined data signal line at a stage later than said data signal line, wherein: each stage of the shift register outputs a pulse signal, the shift register generates a rise of a sampling pulse for writing data into an n-th data signal line which corresponds to an n-th stage of the shift register, in response to a rise of the pulse signal outputted from the n-th stage of the shift register as a result of activation of the pulse signal, and generates a fall of the sampling pulse in response to a rise of a pulse signal outputted from a stage later than the n-th stage of the shift register as a result of activation of the pulse signal.
A pulse generation method according to the present invention is a method for generating a drive pulse signal using an output pulse signal generated in a shift register, wherein a pulse-starting edge and a pulse-termination edge of the drive pulse signal are formed using a rise or a fall of pulse resulting from activation of the output pulse signal.
The pulse generation method according to the present invention is preferably arranged so that the output pulse signal is structured such that a rise of pulse resulting from activation of the output pulse signal is sharper than a subsequent fall of pulse, or a fall of pulse resulting from activation of the output pulse signal is sharper than a return rise of pulse.
A display apparatus according to the present comprises the foregoing drive circuit for a display apparatus.
As described, according to the drive circuit for a display apparatus of the present invention, both of the pulse-starting edge and the pulse-termination edge of the drive pulse signal (such as a pre-charge pulse or a sampling pulse) are formed by a rise or a fall of pulse resulting from activation of the output pulse signal. Therefore, by constituting the shift register to generate pulses so that a rise of pulse resulting from activation of the output pulse signal is sharper than a return fall of pulse, or a fall of pulse resulting from activation of the output pulse signal is sharper than a subsequent rise of pulse, the pulse width of the pre-charge pulse can be highly-accurately set. In this way, the problem of a decrease in driving (pre-charge or sampling) period due to uneven transistor characteristic, or inadequate driving timing (pre-charge or sampling timing) can be solved. On this account, display quality of the display apparatus is improved.
a) A circuit diagram showing a structure of a level shifter LSy.
b) A circuit diagram showing another structure of the level shifter LSy.
a) A circuit diagram showing a structure of a level shifter LSx.
b) A circuit diagram showing another structure of the level shifter LSx.
The display panel 1 includes a sampling circuit block 30, that is made up of analog switches ASW, provided for the respective source bus lines SL for sampling video signals, and control signal processing circuits (sampling buffer etc.) for the switches. The source driver outputs signals (sampling pulse) indicating ON/OFF state of the sampling switch ASW for each group consisting of RGB source bus lines SL. Each of RGB lines has an individual video signal transmission line, allowing simultaneous but individual sampling for RGB from the switches ASW; however, in this example, a signal is fetched from a common video signal transmission line to the all sampling switches ASW of RGB for the sake of convenience. Note that, the sampling switches ASW may be controlled by a common sampling pulse as a control signal for all groups, or by different pulses for the respective groups.
In a horizontal period, for example, the source bus lines SL of R sequentially fetch externally supplied video signals DATA by turning on, by the sampling pulses, the analog switches ASW (R1), . . . , ASW (Ri−1), ASW (Ri), ASW (Ri+1) . . . (in this order), that are connected to the source bus line SL of R. In this manner, the externally supplied video signals DATA are written into the source bus lines SL.
The following explains a structure of the source driver 2 for outputting sampling signals to the analog switches ASW (1), . . . , (i−1), (i), (i+1), . . . in this order.
The shift register 904 includes a large number of shift register stages (circuits) SR. Among them, an (i−1)-th shift register circuit SRa, an i-th shift register circuit SRb, an (i+1)-th shift register circuit SRc, and an (i+2)-th shift register circuit SRd are discussed here. Each shift register circuit SR includes a flip-flop SR-FF and a level shifter LS. The level shifter LS serves to carry out level shift of clocks (CK and CKB), which are fetched when the EN terminal is active, and outputs the results through an OUTB. The flip-flop SR-FF is a set-reset type flip-flop having an input SB (set bar), a reset R, and outputs Q and QB.
A flip-flop SR-FF of each i-th shift register circuit SR is connected to the OUTB of the level shifter LS in the same stage via its SB, and connected to the Q of the (i+2)-th shift register circuit SR (the second adjacent shift register circuit to the right of the figure) via its R, and also connected to an EN terminal of a level shifter LS provided in a (i+1)-th shift register circuit SR (the adjacent shift register circuit to the right of the figure) via its Q.
The shift register circuit SRa includes a level shifter LSa and a flip-flop SR-FFa, the shift register circuit SRb includes a level shifter LSb and a flip-flop SR-FFb, the shift register circuit SRc includes a level shifter LSc and a flip-flop SR-FFc, and the shift register circuit SRd includes a level shifter LSd and a flip-flop SR-FFd.
Further, the pulse processing circuit 5 includes two delay circuits, two level shifters, and a NAND with two inputs corresponding to each shift register circuit SR. The buffer 20 includes a pre-charge buffer circuit BuP and a sampling buffer circuit BuS corresponding to each shift register circuit SR. The pre-charge buffer circuit BuP outputs a pre-charge pulse, and the sampling buffer circuit BuS outputs a sampling pulse. Note that, each NAND is a general circuit for outputting a result of logical multiplication, and serves to output “No”. In this embodiment, the polarity of the output is determined for the sake of convenience.
In the source driver 2 according to the present embodiment, for example, corresponding to the i-th shift register circuit SRb, the pulse processing circuit 5 includes a level shifter LSx, a level shifter LSy, a delay circuit 6, delay circuit 9, and a NAND7. The delay circuit 6 is constituted of a cascade four-stage inverter, and the delay circuit 9 is constituted of a cascade two-stage inverter. The delay circuits 6 and 9 each have a single input terminal and a single output terminal. Further, corresponding to each i-th shift register circuit SRb, the buffer 20 includes an inverter circuit 18P and an inverter 19P serving as a sampling buffer BuS. The inverter circuits 18P and 18S are each constituted of a cascade two-stage inverter having a single input terminal and a single output terminal.
The level shifter LSy has the structure shown in
b) shows another structure of the level shifter LSy. As shown in the figure, this level shifter LSy is a voltage-driven-type level shifter constituted of four transistors, including a p-type TFTs 21 and 23, n-type TFTs 24 and 25, and an inverter 25. The gate of the TFT21 is connected to an input terminal IN. The input terminal of the inverter 25 is also connected to the input terminal IN. The output terminal of the inverter 25 is connected to the gate of the TFT 23. The sources of the TFTs 21 and 23 are connected to a high-level power source terminal V(High), and the sources of the TFTs 22 and 24 are connected to a low-level power source terminal V(Low). The drain of the TFT21 is connected to the drain of the TFT23. The drain of the TFT23 and the drain of the TFT24 are connected to each other, and the junction is further connected to the output terminal OUT. The gate of the TFT22 is connected to the junction between the TFT23 and the TFT24. The gate of the TFT24 is connected to the junction between the TFT21 and the TFT22.
Further, the level shifter LSx includes a structure shown in
b) shows another structure of a level shifter LSx. This level shifter is a voltage-driven-type level shifter, and includes p-type TFTs 41, 43, 45 and 47, n-type TFTs 42, 44 and 46, analog switches 48 and 49, and inverters 50, 51 and 52. The input terminal INB is connected to the gate of the TFT42 and the drain of the TFT45 via the analog switch 48. The input terminal INB is connected to the gate of the TFT44 and the drain of the TFT46 via a sequence of the inverter 51 and the analog switch 49. An enable terminal ENB is connected to the gate of the TFT46, and also connected to the gates of the p-type TFT of the analog switch 48 and the p-type TFT of the analog switch 49. Further, the enable terminal ENB is connected to the gates of the TFT45 and 47 via an inverter 50, and also connected to the gates of n-type TFT of the analog switch 48 and the n-type TFT of the analog switch 49. The sources of the TFTs 41, 43, 45 and 47 are connected to the power source Vdd, and the sources of the TFT42 and 44 are connected to the power source Vssd. The source of the TFT46 is connected to the power source Vss. the gates of the TFTs 41 and 43 are connected to each other, and the junction is connected to the drain of the TFT41. The drains of the TFT41 and the drain of the TFT42 are connected to each other. The drain of the TFT43 and the drain of the TFT44 are connected to each other, and the junction is connected to the input terminal of the inverter 52 and also connected to the drain of the TFT47. The output terminal of the inverter 52 is connected to the output terminal OUT.
Though the input terminal is pulled up in the structure of the present embodiment, the input terminal of the inverter 51 may be pulled down to inverse the polarity of the sampling pulse. This is the same for the other embodiments described later.
The level shifter LSx generates a pre-charge pulse for operating the sampling circuit block 30 using a pulse supplied to the gate of the input terminal INB, and outputs the pre-charge pulse through the output terminal OUT. This signal is supplied to the gates of the n-type TFT and the p-type TFT of the analog switch ASW provided in the sampling circuit block 30 via the pre-charge buffer circuit BuP. This gate signal is also supplied to one of the input terminals of the NAND7. The NAND7 generates a sampling pulse for driving the sampling circuit block 30 using a pulse supplied to an input terminal, and outputs the sampling pulse through the output terminal.
Back to
The following describes an operation of the source driver shown in
First, when the SCK becomes “L” at t1, the output terminal OUTB of the level shifter LSa becomes “L(active)” (falls) with a delay. The delay is caused by an internal delay of the level shifter LSa. When the output terminal OUTB of the level shifter LSa becomes “L(active)”, the output of the delay circuit 6 also becomes “L(active)” (falls) with a delay. The delay is caused by the delay circuit 6. When the output of the delay circuit 6 becomes “L(active)”, the INB terminal of the level shifter LSx becomes “L”, and the ENB terminal also becomes “L”. As a result, the output terminal OUT of the level shifter LSx becomes “H(active)” (rises), delayed from the activation of the delay circuit 6 (the delay is caused by an internal delay of the level shifter LSx). At this time, the level shifter LSx starts outputting the pre-charge pulse. In this manner, the output pulse of the level shifter LSa serves as a source pulse for generating a pre-charge pulse (for forming a pulse-starting edge).
Next, when the output Q of the SR-FFb becomes “H(active)” at t2, the ENB terminal of the level shifter LSx becomes “H”, and the input from its INB terminal is blocked. As a result, the OUT terminal of the level shifter LSx outputs “L”, delayed from the activation of the SR-FFb (the delay is caused by internal delays of the delay circuit 9 and the level shifter LSx). At this time, the level shifter LSx finishes the output of pre-charge pulse. In this manner, the output pulse Q(i) of the flip-flop SR-FFb serves as a source pulse for generating a pre-charge pulse (for forming a pulse-termination edge).
When the OUT terminal of the level shifter LSx becomes “L” again, the output of the inverter circuit 19 becomes “H”. As a result, the output of the NAND7 becomes “H(active)”, delayed from the turning of the output of the inverter circuit 19 into “H” again (the delay is caused by the NAND7). At this time, the NAND7 starts outputting the sampling pulse. The provision of NAND7 thus keeps an interval between the pre-charge pulse and the sampling pulse.
Next, when the output Q of the flip-flop SR-FFc becomes “H” at t3, the output Q of the flip-flop SR-FFb is reset and becomes “L” again. Consequently, the output OUT of the level shifter LSy becomes “L(inactive)” again, delayed from this resetting of the flip-flop SR-FFb. This delay is caused by an internal delay of the level shifter LSy. When the output OUT of the level shifter LSy becomes “L(inactive)”, one of the inputs of the NAND7 becomes “L”, and the output of the NAND7 becomes “L”. At this time, the NAND7 finishes the output of sampling pulse.
In this manner, the pre-charge pulse (output pulse from the OUT of the level shifter LSx) is generated by the two source pulses, namely, the pulse outputted from the level shifter LSa, and the pulse outputted from the flip-flop SR-FFb. The fall (activation) of the pulse outputted from the level shifter LSa forms a pulse-starting edge, and the rise (activation) of the pulse outputted from the flip-flop SR-FFb forms a pulse-termination edge. Therefore, by providing a sharp rise or fall of pulse in response to activation of the source pulses (that is, the return pulse is blunt), the pulse width of the pre-charge pulse can be highly-accurately set. In this way, the problem of a decrease in pre-charge period due to uneven transistor characteristic, or inadequate timing of pre-charge can be solved. On this account, display quality of the display apparatus is improved.
By thus designing the delay circuits 6 and 9 so that the pulse-starting edge and the pulse-termination edge of the pre-charge pulse are formed at rapid timings (or deleted if not required), the width of the pre-charge pulse (pre-charge period) can be set to a desired length with high accuracy.
Alternatively, the pulse processing circuit 5 may have the structure shown in
The delay circuit 6 is constituted of a cascade four-stage inverter, and includes a single input terminal and a single output terminal. The IN terminal of the level shifter LSy1 is connected to the OUTB of the level shifter LSa (provided in the (i−1)-th shift register circuit SRa), and the OUT terminal of the level shifter LSy1 is connected to the input of the delay circuit 6. The output of the delay circuit 6 is connected to one of the inputs of the NOR8. The IN terminal of the level shifter LSy2 is connected to the output Q of the i-th flip-flop SR-FFb (provided in the shift register circuit SRb), and the OUT terminal is connected to the other input of the NOR8 and one of the inputs of the NAND7. The output of the NOR8 is connected to the input of the inverter circuit 18P and the input of the inverter 19P. Further, the output of the inverter 19P is connected to the other input of the NAND7, and the output of the NAND7 is connected to the input of the inverter circuit 18S and the input of the inverter 19S.
Also in this structure of
In this way, the pre-charge pulse (output pulse from the NOR8) is generated by the two source pulses, namely, the pulse outputted from the level shifter LSa, and the pulse outputted from the flip-flop SR-FFb. The fall (activation) of the pulse outputted from the level shifter LSa forms a pulse-starting edge, and the rise (activation) of the pulse outputted from the flip-flop SR-FFb forms a pulse-termination edge. Therefore, by providing a sharp rise or fall of pulse in response to activation of the source pulses (that is, the return pulse is blunt), the pulse width of the pre-charge pulse can be highly-accurately set. In this way, the problem of a decrease in pre-charge period due to uneven transistor characteristic, or inadequate timing of pre-charge can be solved. On this account, display quality of the display apparatus 1 is improved.
Note that, in
Alternatively, the pulse processing circuit 5 may have the structure shown in
The output of the inverter 19P is connected to the other input of the NAND7. The output of the NAND7 is connected to the input of the inverter circuit 18S and the input of the inverter 19S.
As shown in the figure, the source driver 102 includes a shift register 104, a pulse processing circuit 105, and a buffer 120. The shift register 104 includes a large number of shift register stages (circuits) SR. Among them, an (i−1)-th shift register circuit SRa, an i-th shift register circuit SRb, an (i+1)-th shift register circuit SRc, and an (i+2)-th shift register circuit SRd are discussed here. Each shift register circuit SR includes a flip-flop SR-FF, a level shifter LS, a NAND with two inputs, and an inverter. The level shifter LS serves to carry out level shift of clocks (CK and CKB), which are fetched when the EN terminal is active, and outputs the results through an OUTB. The flip-flop SR-FF is a set-reset type flip-flop having an input SB (set bar), a reset R, and outputs Q and QB.
In each shift register circuit SR, the input of the inverter INV is connected to the output Q of a flip-flop SR-FF in the same stage, and the output of the inverter INV is connected to one of the inputs of the NAND. The other input of the NAND is connected to the output Q of the flip-flop SR-FF (provided in the shift register circuit SR) to the left, and the output (of the NAD) is connected to the ENB of the level shifter LS in the same stage. The flip-flop SR-FF is connected to the OUTB of the level shifter LS in the same stage via its SB, and connected via its R to the Q of the shift register circuit SR to the right, and also connected via its Q to the input of the NAND (referred to as a NAD in the figure as appropriate) provided in the shift register circuit SR to the right.
The shift register circuit SRa includes a NANDa (NADa), an inverter INVa, a level shifter LSa and a flip-flop SR-FFa. The shift register circuit SRb includes a NANDb (NADb), an inverter INVb, a level shifter LSb and a flip-flop SR-FFb. The shift register circuit SRc includes a NAND(NAD)c, an inverter INVc, a level shifter LSc and a flip-flop SR-FFc. The shift register circuit SRd includes a NAND(NAD)d, an inverter INVd, a level shifter LSd and a flip-flop SR-FFd.
Further, the pulse processing circuit 105 includes a single delay circuits, two level shifters, and a NAND with two inputs corresponding to each shift register circuit SR. The buffer 120 includes a pre-charge buffer circuit BuP and a sampling buffer circuit BuS corresponding to each shift register circuit SR. The pre-charge buffer circuit BuP outputs a pre-charge pulse, and the sampling buffer circuit BuS outputs a sampling pulse. Note that, each NAND is a general circuit for outputting a result of logical multiplication, and serves to output “No”. In this embodiment, the polarity of the output is determined for the sake of convenience.
In the source driver 102 according to the present embodiment, for example, corresponding to the i-th shift register circuit SRb, the pulse processing circuit 105 includes a level shifter LSx, a level shifter LSy, a delay circuit 106, and a NAND107. The delay circuit 106 is constituted of a cascade four-stage inverter, and has a single input terminal and a single output terminal. Further, corresponding to an i-th shift register circuit SRb, the buffer 120 includes an inverter circuit 118P and an inverter 119P serving as a pre-charge buffer circuit BuS, and an inverter circuit 118S and an inverter 119S as a sampling buffer BuS. Each of these inverter circuits has a single input terminal and a single output terminal. Note that, the logical circuit 188 constituted of a NADb and an inverter INVb is a general circuit for outputting a result of logical multiplication, and serves to output “No”. In this embodiment, the polarity of the output is determined for the sake of convenience. This is the same for the other embodiments described later.
The input of the delay circuit 106 is connected to the output of the NANDa (provided in the (i−1)-th shift register circuit SRa), and the output of the delay circuit 106 is connected to the INB terminal of the level shifter LSx. The output Q of the i-th flip-flop SR-FFb is connected to the IN terminal of the level shifter LSy and the ENB terminal of the level shifter LSx. The OUT terminal of the level shifter LSx is connected to the input of the inverter circuit 118P and the input of the inverter 119P. Further, the output of the inverter 119P is connected to one of the inputs of the NAND107, and the other input of the NAND107 is connected to the OUT terminal of the level shifter LSy. The output of the NAND107 is connected to the input of the inverter circuit 118S and the input of the inverter 119S.
Also in the present embodiment, the pre-charge pulse (output pulse from the level shifter LSx) is generated by the two source pulses, namely, the pulse outputted from the flip-flop SR-FFa, and the pulse outputted from the flip-flop SR-FFb. The fall (activation) of the pulse outputted from the flip-flop SR-FFa forms a pulse-starting edge, and the rise (activation) of the pulse outputted from the flip-flop SR-FFb forms a pulse-termination edge. Therefore, by constituting the shift register 104 to be capable of providing a sharp rise/fall (activation) of the source pulses (that is, the return pulse is blunt), the pulse width of the pre-charge pulse can be highly-accurately set. In this way, the problem of a decrease in pre-charge period due to uneven transistor characteristic, or inadequate timing of pre-charge can be solved. On this account, display quality of the display apparatus 1 is improved.
Alternatively, the pulse processing circuit 105 may have the structure shown in
Also in the structure of
Note that, in
As shown in the figure, the shift register 202 includes a large number of shift register stages (circuits) SR. Among them, an (i−1)-th shift register circuit SRa, an i-th shift register circuit SRb, an (i+1)-th shift register circuit SRc, and an (i+2)-th shift register circuit SRd are discussed here. Each shift register circuit SR includes a flip-flop SR-FF and a NAND with two inputs. The flip-flop SR-FF is a set-reset type flip-flop having an input SB (set bar), a reset R, and outputs Q and QB.
A flip-flop SR-FF of each shift register circuit SR is connected to either of SCK or SCKB depending on whether it resides in an-odd number stage or an even-number stage via one of the inputs of the NAND. The other input of the NAND is connected to the output Q of the flip-flop SR-FF (provided in the shift register circuit SR) to the left, and the output (of the NAD) is connected to the input SB of the flip-flop SR-FF in the same stage. The flip-flop SR-FF is connected to the Q of the shift register circuit SR (the second adjacent shift register circuit SR to the right of the figure) via its reset R, and also connected via its Q to the NAND of the shift register circuit SR to the right. Note that, the NAD circuit in synchronism with the clock is a circuit for outputting a result of logical multiplication, and serves to output “No”. In this embodiment, the polarity of the output is determined for the sake of convenience. The circuit NAD uses an output signal from the flip-flop SR-FF in the preceding stage and a source clock which is an input signal externally supplied to process a logic for outputting a signal in synchronism with a clock signal or a clock. The logic may be logical addition, logical multiplication, a composite logic of addition/multiplication, or a logic element such as an analog switch.
The shift register circuit SRa includes a NANDa and a flip-flop SR-FFa, the shift register circuit SRb includes a NANDb and a flip-flop SR-FFb, the shift register circuit SRc includes a NANDc and a flip-flop SR-FFc, and the shift register circuit SRd includes a NANDd and a flip-flop SR-FFd.
Further, the pulse processing circuit 205 includes a delay circuit, two level shifters, and a NAND with two inputs corresponding to each shift register circuit SR. The buffer 220 includes a pre-charge buffer circuit BuP and a sampling buffer circuit BuS corresponding to each shift register circuit SR. The pre-charge buffer circuit BuP outputs a pre-charge pulse, and the sampling buffer circuit BuS outputs a sampling pulse. Note that, each NAND is a general circuit for outputting a result of logical multiplication, and serves to output “No”.
In the source driver 202 according to the present embodiment, a pulse processing circuit 205 of an i-th shift register circuit SR includes a level shifter LSx, a level shifter LSy, a delay circuit 206, and a NAND 207. The delay circuit 106 is constituted of a cascade four-stage inverter, and includes a single input terminal and a single output terminal. Further, corresponding to each i-th shift register circuit SRb, the buffer 220 includes an inverter circuit 218P and an inverter 219P serving as a pre-charge buffer circuit BuS, and an inverter circuit 218S and an inverter 219S serving as a sampling buffer BuS. The inverter circuits 218P and 218S are each constituted of a cascade two-stage inverter having a single input terminal and a single output terminal.
The input of the delay circuit 206 is connected to the output of the NANDa (provided in the (i−1)-th shift register circuit SRa), and the output of the delay circuit 206 is connected to the INB terminal of the level shifter LSx. The output Q of the i-th flip-flop SR-FFb is connected to the IN terminal of the level shifter LSy and the ENB terminal of the level shifter LSx. The OUT terminal of the level shifter LSx is connected to the input of the inverter circuit 218P and the input of the inverter 219P. Further, the output of the inverter 219P is connected to one of the inputs of the NAND207, and the other input of the NAND207 is connected to the OUT terminal of the level shifter LSy. The output of the NAND207 is connected to the input of the inverter circuit 218S and the input of the inverter 219S.
Also in the present embodiment, the pre-charge pulse (output pulse from the level shifter LSx) is generated by the two source pulses, namely, the pulse outputted from the flip-flop SR-FFa, and the pulse outputted from the flip-flop SR-FFb. The fall (activation) of the pulse outputted from the flip-flop SR-FFa forms a pulse-starting edge, and the rise (activation) of the pulse outputted from the flip-flop SR-FFb forms a pulse-termination edge. Therefore, by constituting the shift register 104 to be capable of providing a sharp rise/fall (activation) of the source pulses (that is, the return pulse is blunt), the pulse width of the pre-charge pulse can be highly-accurately set. In this way, the problem of a decrease in pre-charge period due to uneven transistor characteristic, or inadequate timing of pre-charge can be solved. On this account, display quality of the display apparatus 1 is improved.
Alternatively, the pulse processing circuit 205 may have the structure shown in
Also in this structure of
Note that, in
As shown in the figure, the source driver 302 includes a shift register 304, a pulse processing circuit 305, a buffer 320. The shift register 304 includes a large number of shift register stages (circuits) SR. Among them, an (i−1)-th shift register circuit SRa, an i-th shift register circuit SRb, an (i+1)-th shift register circuit SRc, and an (i+2)-th shift register circuit SRd are discussed here. Each shift register circuit SR includes a flip-flop SR-FF, a single inverter INV and a switch SW. The flip-flop SR-FF is a set-reset type flip-flop having an input SB (set bar), a reset R, and outputs Q and QB.
In each shift register circuit SR, one of the conduction terminals of the switch SW is connected to either of SCK or SCKB depending on whether it resides in an-odd number stage or an even-number stage. The other conduction terminal (in the output end) is connected to the input SB of the flip-flop SR-FF in the same stage. The flip-flop SR-FF is connected to the Q of the shift register circuit SR (the second adjacent shift register circuit SR to the right of the figure) via its reset R, and also connected via its Q to the inverter INV of the shift register circuit SR to the right. Note that, the two control terminals of the switch SW are connected to the input and the output of the inverter INV.
The shift register circuit SRa includes a switch SWa, an inverter INVa and a flip-flop SR-FFa, the shift register circuit SRb includes a switch SWb, an inverter INVb and a flip-flop SR-FFb, the shift register circuit SRc includes a switch SWc, an inverter INVc and a flip-flop SR-FFc, and the shift register circuit SRd includes a switch SWd, an inverter INVd and a flip-flop SR-FFd.
Further, the pulse processing circuit 305 includes a delay circuit, two level shifters, and a NAND with two inputs corresponding to each shift register circuit SR. The buffer 320 includes a pre-charge buffer circuit BuP and a sampling buffer circuit BuS corresponding to each shift register circuit SR. The pre-charge buffer circuit BuP outputs a pre-charge pulse, and the sampling buffer circuit BuS outputs a sampling pulse. Note that, the NAND is a general circuit for outputting a result of logical multiplication, and serves to output “No”. In this embodiment, the polarity of the output is determined for the sake of convenience.
In the source driver 302 according to the present embodiment, a pulse processing circuit 305 of an i-th shift register circuit SR includes a level shifter LSx, a level shifter LSy, a delay circuit 306, and a NAND 307. The delay circuit 306 is constituted of a cascade four-stage inverter, and includes a single input terminal and a single output terminal. Further, corresponding to each i-th shift register circuit SRb, the buffer 320 includes an inverter circuit 318P and an inverter 319P serving as a pre-charge buffer circuit BuS, and an inverter circuit 318S and an inverter 319S serving as a sampling buffer BuS. The inverter circuits 318P and 318S are each constituted of a cascade two-stage inverter having a single input terminal and a single output terminal.
The input of the delay circuit 306 is connected to the conduction terminal (in the output end) of the switch SWa (provided in the (i−1)-th shift register circuit SRa), and the output of the delay circuit 306 is connected to the INB terminal of the level shifter LSx. The output Q of the i-th flip-flop SR-FFb is connected to the IN terminal of the level shifter LSy and the ENB terminal of the level shifter LSx. The OUT terminal of the level shifter LSx is connected to the input of the inverter circuit 318P and the input of the inverter 319P. Further, the output of the inverter 319P is connected to one of the inputs of the NAND307, and the other input of the NAND307 is connected to the OUT terminal of the level shifter LSy. The output of the NAND307 is connected to the input of the inverter circuit 318S and the input of the inverter 319S.
Also in the present embodiment, the pre-charge pulse (output pulse from the level shifter LSx) is generated by the two source pulses, namely, the pulse outputted from the flip-flop SR-FFa, and the pulse outputted from the flip-flop SR-FFb. The fall (activation) of the pulse outputted from the flip-flop SR-FFa forms a pulse-starting edge, and the rise (activation) of the pulse outputted from the flip-flop SR-FFb forms a pulse-termination edge. Therefore, by constituting the shift register 104 to be capable of providing a sharp rise/fall (activation) of the source pulses (that is, the return pulse is blunt), the pulse width of the pre-charge pulse can be highly-accurately set. In this way, the problem of a decrease in pre-charge period due to uneven transistor characteristic, or inadequate timing of pre-charge can be solved. On this account, display quality of the display apparatus 1 is improved.
Alternatively, the pulse processing circuit 305 may have the structure shown in
Also in this structure of
Note that, in
As shown in the figure, the source driver 402 includes a shift register 404, a pulse processing circuit 405, and a buffer 420. The shift register 404 includes a large number of shift register stages (circuits) SR. Among them, an (i−1)-th shift register circuit SRa, an i-th shift register circuit SRb, an (i+1)-th shift register circuit SRc, and an (i+2)-th shift register circuit SRd are discussed here. Each shift register circuit SR includes a flip-flop SR-FF and a level shifter LS. The level shifter LS serves to carry out level shift of clocks (CK and CKB), which are fetched when the EN terminal is active, and outputs the results through an OUTB. The flip-flop SR-FF is a set-reset type flip-flop having an input SB (set bar), a reset R, and outputs Q and QB.
The flip-flop SR-FF of each shift register circuit SR is connected to the OUTB of the level shifter LS in the same stage via its SB, and is also connected via R to the Q of the shift register circuit SR second adjacent to the right of the figure. The Q is connected to the EN terminal of the level shifter LS provided in the shift register circuit SR to the right.
The shift register circuit SRa includes a level shifter LSa and a flip-flop SR-FFa, the shift register circuit SRb includes a level shifter LSb and a flip-flop SR-FFb, the shift register circuit SRc includes a level shifter LSc and a flip-flop SR-FFc, and the shift register circuit SRd includes a level shifter LSd and a flip-flop SR-FFd.
Further, the pulse processing circuit 405 includes two delay circuits, two level shifters, and a NOR (two inputs) and a NAND (two inputs) corresponding to each shift register circuit SR. The buffer 420 includes a pre-charge buffer circuit BuP and a sampling buffer circuit BuS corresponding to each shift register circuit SR. The pre-charge buffer circuit BuP outputs a pre-charge pulse, and the sampling buffer circuit BuS outputs a sampling pulse. Note that, the NAND is a general circuit for outputting a result of logical multiplication, and serves to output “No”. In this embodiment, the polarity of the output is determined for the sake of convenience.
In the source driver 402 according to the present embodiment, a pulse processing circuit 405 of an i-th shift register circuit SR includes a level shifter LSx, a level shifter LSy, delay circuits 406 and 409, and two NORs 433 and 435, and a NAND434. The delay circuit 406 is constituted of a cascade four-stage inverter, and the delay circuit 409 is constituted of a cascade two-stage inverter. These two delay circuits each include a single input terminal and a single output terminal. Further, corresponding to each i-th shift register circuit SRb, the buffer 420 includes an inverter circuit 418P and an inverter 419P serving as a pre-charge buffer circuit BuS, and an inverter circuit 418S and an inverter 419S serving as a sampling buffer BuS. The inverter circuits 418P and 418S are each constituted of a cascade two-stage inverter having a single input terminal and a single output terminal.
The input of the delay circuit 406 is connected to the OUTB of the level shifter LSa (provided in the (i−1)-th shift register circuit SRa), and the output of the delay circuit 406 is connected to one of the inputs of the NOR433. The output Q of the i-th flip-flop SR-FFb (provided in the shift register circuit SRb) is connected to another input of the NOR433 and one of the inputs of the NAND434. The output of the NOR433 is connected to the input of the inverter circuit 418P and the input of the inverter 419P. Further, the output of the inverter 419P is connected to one of the inputs of the NAND434, and the output of the NAND434 is connected to one of the inputs of the NAND435. The other input of the NAND435 is connected to the output Q of the flip-flop SR-FFd (provided in the (i+2)-th shift register circuit SRd), and the output (of the NOR435) is connected to the input of the inverter circuit 418S and the input of the inverter 419S.
The following explains an operation of the source driver shown in
First, when the SCK becomes “L” at t1, the output terminal OUTB of the level shifter LSa becomes “L(active)” (falls). When the output terminal OUTB of the level shifter LSa becomes “L(active)”, the output of the delay circuit 406 also becomes “L(active)” (falls) with a delay. The delay is caused by the delay circuit 406. When the output of the delay circuit 406 becomes “L(active)”, one of the inputs of the NOR433 becomes “L”, and the output of the NOR433 becomes “H(active)” (rises) with a delay. At this time, the NOR433 starts outputting the pre-charge pulse. In this manner, the output pulse of the level shifter LSa serves as a source pulse for generating a pre-charge pulse (for forming a pulse-starting edge).
Next, when the output Q of the SR-FFb becomes “H(active)” at t2, one of the inputs of the NOR433 becomes “H”, and the NOR433 outputs “L”. At this time, the NOR433 finishes the output of pre-charge pulse. In this manner, the output pulse Q(i) of the flip-flop SR-FFb serves as a source pulse for generating a pre-charge pulse (for forming a pulse-termination edge).
When the output of the NOR433 becomes “L” again, the output of the inverter circuit 419 becomes “H” again. In response to this, the output of the NAND434 becomes “L(active)” with a delay. Consequently, the two inputs of the NOR435 (the other input is the output Q of the flip-flop SR-FFd) become “L”, and the output of the NOR435 becomes “H (active)”. At this time, the NOR435 starts outputting the sampling pulse. The provision of the NAND434 thus keeps an interval between the pre-charge pulse and the sampling pulse.
Next, when the output Q of the flip-flop SR-FFd becomes “H” at t3, one of the inputs of the NOR435 becomes “H”, and the output of the NOR435 becomes “L”. At this time, the NOR435 finishes the output of sampling pulse.
According to Fifth Embodiment, the pre-charge pulse (output pulse from the NOR433) is generated by the two source pulses, namely, the pulse outputted from the level shifter LSa, and the pulse outputted from the flip-flop SR-FFb. The fall (activation) of the pulse outputted from the level shifter LSa forms a pulse-starting edge, and the rise (activation) of the pulse outputted from the flip-flop SR-FFb forms a pulse-termination edge. Therefore, by providing a sharp rise or fall of pulse in response to activation of the source pulses (that is, the return pulse is blunt), the pulse width of the pre-charge pulse can be highly-accurately set. In this way, the problem of a decrease in pre-charge period due to uneven transistor characteristic, or inadequate timing of pre-charge can be solved. On this account, display quality of the display apparatus 1 is improved.
Further, according to the present embodiment, the sampling pulse (output pulse from the NOR435) is generated by the two source pulses, namely, the pulse outputted from the flip-flop SR-FFb, and the pulse outputted from the flip-flop SR-FFd. The fall (activation) of the pulse outputted from the flip-flop SR-FFb forms a pulse-starting edge, and the rise (activation) of the pulse outputted from the flip-flop SR-FFd forms a pulse-termination edge. Therefore, by providing a sharp rise or fall of pulse in response to activation of the source pulses (that is, the return pulse is blunt), the pulse width of the sampling pulse can be highly-accurately set. On this account, it becomes possible to prevent a problem of sampling error (pickup of next data; see the upper part of
By thus designing the delay circuits 406 and 9 so that the pulse-starting edge and the pulse-termination edge of the sampling pulse are formed at rapid timings (or deleted if not required), the width of the sampling pulse (sampling period) can be set to a desired length with high accuracy.
Note that, the NOR435 is a general circuit for outputting a result of logical multiplication, and serves to output “No”. In this embodiment, the polarity of the output is determined for the sake of convenience. Further, depending on the polarity combination of input signals supplied to the logic circuit, the NOR435 may be replaced with a circuit for outputting a result of logic addition.
As described, with the present embodiment, an excessive reduction in sampling pulse width due to uneven transistor characteristic can be prevented, and a pulse in which the pre-charge pulse and the sampling pulse are not superimposed can be easily generated. Further, an excessive reduction in pre-charge pulse width due to uneven transistor characteristic can be prevented, and a pulse in which the i-th pre-charge pulse and the (i+1)-th pre-charge pulse are not superimposed can be easily generated. Moreover, with addition of a delay elimination circuit (NOR435), the present embodiment eliminates an excessive delay of the pulse-termination edge of sampling pulse. On this account, false operation in sampling can be prevented.
The following explains a part of reference numerals.
The drive circuit (source driver) of a display apparatus according to the present invention is applicable to various purposes, such as a display panel for a mobile device, or a display apparatus including TVs and monitors.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2005-174386 | Jun 2005 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2006/311734 | 6/12/2006 | WO | 00 | 12/6/2007 |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2006/134861 | 12/21/2006 | WO | A |
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