Patent Application
20240274074
The present disclosure relates to, but is not limited to, the field of display technology, in particular to a drive control circuit, a gate drive circuit, a display substrate and a display apparatus.
An Organic Light Emitting Diode (OLED) and a Quantum dot Light Emitting Diode (QLED) are active light emitting display devices and have advantages of self-illumination, a wide viewing angle, a high contrast ratio, low power consumption, an extremely high reaction speed, lightness and thinness, bendability, and a low cost, etc.
The following is a summary of subject matters described herein in detail. The summary is not intended to limit the protection scope of claims.
Embodiments of the present disclosure provide a drive control circuit, a gate drive circuit, a display substrate and a display apparatus.
In one aspect, an embodiment of the present disclosure provides a drive control circuit, including: an input circuit, a first output circuit, and a second output circuit. the input circuit is electrically connected with a signal input terminal, a clock signal terminal, a first node and a second node, and is configured to control the potentials of the first node and the second node under the control of the signal input terminal and the clock signal terminal. The first output circuit is electrically connected with the first node, the second node, the first output terminal, the first power supply line, and the second power supply line, and is configured to output a first power supply signal supplied by the first power supply line to the first output terminal under the control of the first node, or to output a second power supply signal supplied by the second power supply line to the first output terminal under the control of the second node. The second output circuit is electrically connected with the first node, the second node, the second output terminal, the third power supply line and the fourth power supply line, and is configured to output a fourth power supply signal supplied by the fourth power supply line to the second output terminal under the control of the first node, or to output a third power supply signal supplied by the third power supply line to the second output terminal under the control of the second node.
In some exemplary embodiments, the second output circuit includes a third output transistor and a fourth output transistor. A control electrode of the third output transistor is electrically connected to the first node, a first electrode of the third output transistor is electrically connected to the fourth power supply line, and a second electrode of the third output transistor is electrically connected to the second output terminal. A control electrode of the fourth output transistor is electrically connected to the second node, a first electrode of the fourth output transistor is electrically connected to the third power supply line, and a second electrode of the fourth output transistor is electrically connected to the second output terminal.
In some exemplary embodiments, the second output circuit further includes: a fourth capacitor; a first electrode plate of the fourth capacitor is electrically connected to the first node, and a second electrode plate of the fourth capacitor is electrically connected to the fourth power supply line.
In some exemplary embodiments, the first output circuit includes: a first output transistor and a second output transistor. A control electrode of the first output transistor is electrically connected to the first node, a first electrode of the first output transistor is electrically connected to the first power supply line, and a second electrode of the first output transistor is electrically connected to the first output terminal. A control electrode of the second output transistor is electrically connected to the second node, a first electrode of the second output transistor is electrically connected to the second power supply line, and a second electrode of the second output transistor is electrically connected to the first output terminal.
In some exemplary embodiments, the input circuit includes: an input sub-circuit, a first control sub-circuit, a second control sub-circuit, and a third control sub-circuit. The input sub-circuit is electrically connected with the signal input terminal, the first clock terminal, the second power supply line, the second node, and the third node, and is configured to control the potentials of the second node and the third node under the control of the first clock terminal and the signal input terminal. The first control sub-circuit is electrically connected with the second node, the third node, the first power supply line, and the second clock terminal, and is configured to control the potential of the second node under the control of the third node and the second clock terminal, or to store the signal supplied by the first power supply line or the second clock terminal under the control of the second node and the third node. The second control sub-circuit is electrically connected with the third node, the first node and the second clock terminal, and is configured to control the potential of the first node under the control of the third node and the second clock terminal. The third control sub-circuit is electrically connected to the first node, the second node and the first power supply line, and is configured to control the potential of the first node under the control of the second node.
In some exemplary embodiments, the input sub-circuit includes: a third transistor, a fourth transistor and a fifth transistor. A control electrode of the third transistor is electrically connected to the second node, a first electrode of the third transistor is electrically connected to the first clock terminal, and a second electrode of the third transistor is electrically connected to the third node. A control electrode of the fourth transistor is electrically connected with the first clock terminal, a first electrode of the fourth transistor is electrically connected with the signal input terminal, and a second electrode of the fourth transistor is electrically connected with the second node. A control electrode of the fifth transistor is electrically connected to the first clock terminal, a first electrode of the fifth transistor is electrically connected to the second power supply line, and a second electrode of the fifth transistor is electrically connected to the third node.
In some exemplary embodiments, the first control sub-circuit includes: a first transistor, a second transistor and a third capacitor. The control electrode of the first transistor is electrically connected to the third node, the first electrode of the first transistor is electrically connected to the first power supply line, and the second electrode of the first transistor is electrically connected to the first electrode of the second transistor. The control electrode of the second transistor is electrically connected with the second clock terminal, and the second electrode of the second transistor is electrically connected with the second node. A first electrode plate of the third capacitor is electrically connected to the second node, and a second electrode plate of the third capacitor is electrically connected to the second clock terminal.
In some exemplary embodiments, the first control sub-circuit includes: a first transistor, a second transistor and a third capacitor. The control electrode of the first transistor is electrically connected to the third node, the first electrode of the first transistor is electrically connected to the first power supply line, and the second electrode of the first transistor is electrically connected to the second electrode of the second transistor. The control electrode of the second transistor is electrically connected with the second node, and the first electrode of the second transistor is electrically connected with the second clock terminal. The first electrode plate of the third capacitor is electrically connected to the second node, and the second electrode plate of the third capacitor is electrically connected to the second electrode of the second transistor.
In some exemplary embodiments, the second control sub-circuit includes: a sixth transistor, a seventh transistor and a second capacitor. A control electrode of the sixth transistor is electrically connected to the third node, a first electrode of the sixth transistor is electrically connected to the second clock terminal, and a second electrode of the sixth transistor is electrically connected to a first electrode of the seventh transistor. A control electrode of the seventh transistor is electrically connected with the second clock terminal, and a second electrode of the seventh transistor is electrically connected with the first node. A first electrode plate of the second capacitor is electrically connected to the third node, and a second electrode plate of the second capacitor is electrically connected to the first electrode of the seventh transistor.
In some exemplary embodiments, the third control sub-circuit includes: an eighth transistor and a first capacitor. A control electrode of the eighth transistor is electrically connected to the second node, a first electrode of the eighth transistor is electrically connected to the first power supply line, and a second electrode of the eighth transistor is electrically connected to the first node. A first electrode plate of the first capacitor is electrically connected to the first node, and a second electrode plate of the first capacitor is electrically connected to the first power supply line.
In another aspect, an embodiment of the present disclosure provides a gate drive circuit including a plurality of cascaded drive control circuits described above; wherein, a signal input terminal of a first stage drive control circuit is electrically connected with a start signal line, and a signal input terminal of an i+1 stage drive control circuit is electrically connected with a first output terminal of an i stage drive control circuit, wherein, i is an integer greater than 0.
In another aspect, embodiments of the present disclosure provide a display substrate including a display region and a non-display region located on the periphery the display region; the display region is provided with a plurality of sub-pixels, at least one sub-pixel includes a pixel circuit and a light emitting element, wherein the pixel circuit is electrically connected with the light emitting element; the non-display region is provided with a gate drive circuit including a plurality of cascaded drive control circuits. The pixel circuit at least includes a drive sub-circuit, a light emitting control sub-circuit and a second reset sub-circuit; the light emitting control sub-circuit is configured to supply a fifth power supply signal to the drive sub-circuit under the control of the light emitting control signal; the drive sub-circuit is configured to drive the light emitting element to emit light by using the fifth power supply signal; the second reset sub-circuit is configured to reset an anode of the light emitting element under the control of the second reset control signal. The drive control circuit is electrically connected to a signal input terminal, a first output terminal and a second output terminal, and is configured to provide the light emitting control signal to the pixel circuit through the first output terminal and provide a second reset control signal to the pixel circuit through the second output terminal.
In some exemplary embodiments, the pixel circuit further includes: a data writing sub-circuit configured to provide a data signal under control of a scan signal. Within the duration of one frame, the overlapping duration between the reset duration of the anode of the light emitting element under the control of the second reset control signal and the duration during which the light emitting element is not driven by the light emitting control signal is longer than twice the effective level duration of the scan signal.
In some exemplary embodiments, the drive control circuit includes: an input circuit, a first output circuit, and a second output circuit; the input circuit is configured to control the potentials of the first node and the second node under the control of the signal input terminal and the clock signal terminal. The first output circuit is configured to provide a light emitting control signal to the pixel circuit through a first output terminal under the control of the first node and the second node. The second output circuit is configured to provide a second reset control signal to the pixel circuit through a second output terminal under the control of the first node and the second node.
In some exemplary embodiments, the drive control circuit is electrically connected to a clock signal line, a first power supply line, and a second power supply line. The first power supply line and the clock signal line are arranged in a first direction along a direction in which the input circuit is away from the first output circuit, and the second power supply line is located on a side of the second output circuit away from the first output circuit in the first direction. Alternatively, the second power supply line and the clock signal line are arranged in the first direction along a direction in which the input circuit is away from the first output circuit, and the first power supply line is located on a side of the second output circuit away from the first output circuit in the first direction.
In some exemplary embodiments, the signal input terminal, the first output terminal and the second output terminal are of the same layer structure.
In some exemplary embodiments, the input circuit includes: an input sub-circuit, a first control sub-circuit, a second control sub-circuit, and a third control sub-circuit. The input sub-circuit is electrically connected with the signal input terminal, the first clock terminal, the second power supply line, the second node, and the third node, and is configured to control the potentials of the second node and the third node under the control of the first clock terminal and the signal input terminal. The first control sub-circuit is electrically connected with the second node, the third node, the first power supply line and the second clock terminal, and is configured to control the potential of the second node under the control of the third node and the second clock terminal. The second control sub-circuit is electrically connected with the third node, the first node and the second clock terminal, and is configured to control the potential of the first node under the control of the third node and the second clock terminal. The third control sub-circuit is electrically connected to the first node, the second node and the first power supply line, and is configured to control the potential of the first node under the control of the second node. The third control sub-circuit is located between the first output circuit and the second output circuit in a first direction, and the input sub-circuit, the first control sub-circuit and the second control sub-circuit are located on a side of the first output circuit away from the second output circuit in the first direction.
In some exemplary embodiments, the input sub-circuit at least includes a third transistor; the first control sub-circuit at least includes a third capacitor; the third control sub-circuit at least includes an eighth transistor; the first output circuit at least includes a second output transistor; the second output circuit at least includes a fourth output transistor. The control electrode of the third transistor, the control electrode of the second output transistor, the control electrode of the eighth transistor, the control electrode of the fourth output transistor and the first electrode plate of the third capacitor are in an integrated structure.
In some exemplary embodiments, the third control sub-circuit further includes a first capacitor; the first output circuit further includes a first output transistor; the second output circuit further includes a third output transistor and a fourth capacitor. The control electrode of the first output transistor, the control electrode of the third output transistor, the first electrode plate of the first capacitor and the first electrode plate of the fourth capacitor are in an integrated structure.
In some exemplary embodiments, the input sub-circuit further includes a fourth transistor and a fifth transistor; the control electrode of the fourth transistor and the control electrode of the fifth transistor are in an integrated structure, and are electrically connected with the first clock signal line, and further connected with the first electrode of the third transistor through a tenth connection electrode.
In some exemplary embodiments, the first control sub-circuit further includes a second transistor; the second control sub-circuit at least includes a sixth transistor and a seventh transistor. The control electrode of the second transistor is electrically connected with the second clock signal line, and is electrically connected with the second electrode plate of the third capacitor, the second electrode of the sixth transistor and the control electrode of the seventh transistor through an eleventh connection electrode. An orthographic projection of the eleventh connection electrode on the substrate is L-shaped.
In some exemplary embodiments, the input circuit, the first output circuit, and the second output circuit are sequentially arranged in a first direction.
In some exemplary embodiments, the first output terminal includes a first portion, a second portion, and a third portion connected in sequence; the first portion extends in a second direction and is located between the first output circuit and the second output circuit, the second portion extends in the first direction along a side away from the second output circuit, and the third portion extends in the first direction along a side away from the input circuit. The second output terminal includes a fourth portion and a fifth portion connected in sequence; the fourth portion extends along the second direction and is located on a side of the second output circuit away from the first output circuit, and the fifth portion extends along the first direction and is located on a side of the third portion close to the drive control circuit; wherein the second direction crosses the first direction.
In some exemplary embodiments, the input circuit includes: an input sub-circuit, a first control sub-circuit, a second control sub-circuit, and a third control sub-circuit. The input sub-circuit is electrically connected with the signal input terminal, the first clock terminal, the second power supply line, the second node, and the third node, and is configured to control the potentials of the second node and the third node under the control of the first clock terminal and the signal input terminal. The first control sub-circuit is electrically connected with the second node, the third node, the first power supply line, and the second clock terminal, and is configured to store the signal supplied by the first power supply line or the second clock terminal under the control of the second node and the third node. The second control sub-circuit is electrically connected with the third node, the first node and the second clock terminal, and is configured to control the potential of the first node under the control of the third node and the second clock terminal. The third control sub-circuit is electrically connected to the first node, the second node and the first power supply line, and is configured to control the potential of the first node under the control of the second node. The third control sub-circuit is located between the second control sub-circuit and the first output circuit in the first direction, and the input sub-circuit, the second control sub-circuit and the first output circuit surround three sides of the first control sub-circuit.
In some exemplary embodiments, the first control sub-circuit includes a first transistor, a second transistor, and a third capacitor; the third control sub-circuit includes an eighth transistor and a first capacitor; the first output circuit includes a first output transistor and a second output transistor; the second output circuit includes a third output transistor, a fourth output transistor and a fourth capacitor. The control electrode of the second transistor, the control electrode of the second output transistor, the control electrode of the fourth output transistor and the first electrode plate of the third capacitor are in an integrated structure. The control electrode of the first output transistor and the first electrode plate of the first capacitor are in an integrated structure, and the control electrode of the third output transistor and the first electrode plate of the fourth capacitor are in an integrated structure.
In some exemplary embodiments, the second electrode of the first transistor is electrically connected to the second electrode of the second transistor and the second electrode plate of the third capacitor through a forty-first connection electrode.
In some exemplary embodiments, the input sub-circuit includes: a third transistor, a fourth transistor and a fifth transistor. The control electrode of the third transistor and the control electrode of the eighth transistor are in an integrated structure and are electrically connected with the control electrode of the second transistor through a fortieth connection electrode, a thirty-second connection electrode and a forty-second connection electrode in turn; the fortieth connection electrode and the forty-second connection electrode are located on a side of the thirty-second connection electrode away from the substrate. The control electrode of the fourth transistor and the control electrode of the fifth transistor are in an integrated structure, and are electrically connected with the first clock signal line.
In some exemplary embodiments, the second control sub-circuit includes a sixth transistor, a seventh transistor, and a second capacitor; the control electrode of the sixth transistor and the first electrode plate of the second capacitor are in an integrated structure. The first electrode of the sixth transistor is electrically connected to a forty-fourth connection electrode, the forty-fourth connection electrode is electrically connected to the second clock signal line through a thirty-fifth connection electrode, and the forty-fourth connection electrode is electrically connected to the control electrode of the seventh transistor and the first electrode of the second transistor.
In some exemplary embodiments, an active layer of the first transistor, an active layer of the seventh transistor, and an active layer of the eighth transistor are in an integrated structure, and the orthographic projection on the substrate is G-shaped.
In some exemplary embodiments, the second electrode of the first output transistor, the second electrode of the second output transistor and the first output terminal are electrically connected through a forty-seventh connection electrode, and the second electrode of the third output transistor, the second electrode of the fourth output transistor and the second output terminal are electrically connected through a fifty-first connection electrode; both the orthographic projection of the forty-seventh connection electrode and the orthographic projection of the fifty-first connection electrode on the substrate are a “” shape.
In another aspect, an embodiment of the present disclosure provides a display apparatus, which includes the aforementioned display substrate.
Other aspects may be understood upon reading and understanding the drawings and the detailed description.
Accompanying drawings are used for providing further understanding of technical solutions of the present disclosure, constitute a part of the specification, and together with the embodiments of the present disclosure, are used for explaining the technical solutions of the present disclosure but not to constitute limitations on the technical solutions of the present disclosure. Shapes and sizes of one or more components in the drawings do not reflect true scales, and are only intended to schematically describe contents of the present disclosure.
The embodiments of the present disclosure will be described below in combination with the drawings in detail. Implementations may be implemented in a plurality of different forms. Those of ordinary skills in the art may easily understand such a fact that implementation modes and contents may be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be explained as being limited to contents described in following implementation modes only. The embodiments in the present disclosure and features in the embodiments may be combined randomly with each other if there is no conflict.
In the drawings, a size of one or more constituent elements, a thickness of a layer, or a region is sometimes exaggerated for clarity. Therefore, a mode of the present disclosure is not necessarily limited to the size, and a shape and a size of one or more components in the drawings do not reflect a true proportion. In addition, the drawings schematically illustrate ideal examples, and one implementation of the present disclosure is not limited to the shapes, numerical values, or the like shown in the drawings.
Ordinal numerals such as “first”, “second” and “third” in the present disclosure are set to avoid confusion of constituent elements, but not intended for restriction in quantity. In the present disclosure, “a plurality of ” represents two or more than two.
In the present disclosure, for convenience, wordings “central”, “up”, “down”, “front”, “back”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside” and the like indicating orientation or positional relationships are used to illustrate positional relationships between constituent elements with reference to the drawings. These wordings are not intended to indicate or imply that involved devices or elements must have specific orientations and be structured and operated in the specific orientations, but only to facilitate describing the present specification and simplify the description, and thus should not be understood as limitations on the present disclosure. The positional relationships between the constituent elements are changed as appropriate based on directions which are used for describing the constituent elements. Therefore, appropriate replacements may be made according to situations without being limited to the wordings described in the specification.
In the present disclosure, unless otherwise specified and defined, terms “mounting”, “mutual connection” and “connection” should be understood in a broad sense. For example, a connection may be a fixed connection, or a detachable connection, or an integrated connection. It may be a mechanical connection or an electrical connection. It may be a direct mutual connection, or an indirect connection through middleware, or internal communication between two components. Those of ordinary skills in the art may understand meanings of the above-mentioned terms in the present disclosure according to situations. An “electrical connection” includes a case where constituent elements are connected together through an element with some electric action. The “element having some electrical function” is not particularly limited as long as electrical signals between the connected constituent elements may be transmitted. Examples of the “element with the certain electrical effect” not only include electrodes and wirings, but include switching elements (such as transistors), resistors, inductors, capacitors, other elements with one or more functions, etc.
In the present disclosure, a transistor refers to an element at least including three terminals, i.e., a gate electrode (gate), a drain electrode, and a source electrode. The transistor has a channel area between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source), and a current can flow through the drain electrode, the channel area, and the source electrode. In the present disclosure, the channel area refers to a region through which a current mainly flows.
In the present disclosure, to distinguish two electrodes of a transistor except a gate electrode, one of the electrodes is referred to as a first electrode and the other electrode is referred to as a second electrode. The first electrode may be a source electrode or a drain electrode, and the second electrode may be a drain electrode or a source electrode. In addition, the gate electrode of the transistor is referred to as a control electrode. In cases that transistors with opposite polarities are used, a current direction changes during operation of a circuit, or the like, functions of the “source electrode” and the “drain electrode” are sometimes interchangeable. Therefore, the “source electrode” and the “drain electrode” are interchangeable in the present disclosure.
In the present disclosure, “parallel” refers to a state in which an angle formed by two straight lines is above −10 degrees and below 10 degrees, and thus may include a state in which the angle is above −5 degrees and below 5 degrees. In addition, “perpendicular” refers to a state in which an angle formed by two straight lines is above 80 degrees and below 100 degrees, and thus may include a state in which the angle is above 85 degrees and below 95 degrees.
In the present disclosure, “film” and “layer” are interchangeable. For example, a “conductive layer” may be replaced with a “conductive film” sometimes. Similarly, an “insulating film” may be replaced with an “insulating layer” sometimes.
In the present disclosure, “about”, “approximate” and “approximately” refer to a case that a boundary is defined not so strictly and a process and measurement error within a range is allowed.
In some exemplary implementations, the display substrate may include: a display region and a non-display region. For example, the non-display region may be located at a periphery of the display region. However, this embodiment is not limited thereto. The display region at least includes: a plurality of sub-pixels, a plurality of gate lines extending along the first direction (for example including: s scan line, s first reset control line, s second reset control line and an light emitting control line), a plurality of data lines and power supply lines extending along the second direction. At least one sub-pixel includes a pixel circuit and a light emitting element. The pixel circuit is electrically connected with the light emitting element, and is configured to drive the light emitting element to emit light. The first direction and the second direction are located in a same plane, and the first direction interacts with the second direction, for example, the first direction may be perpendicular to the second direction. The non-display region may be provided with a plurality of gate drive circuits. Each gate drive circuit may include a plurality of cascaded drive control circuits. The gate drive circuit may be configured to provide a gate drive signal (e.g. a scan signal, a reset control signal, a light emitting control signal and the like) to a pixel circuit of the display region.
In some exemplary embodiments, the pixel circuit of the display region may include at least a drive sub-circuit, a light emitting control sub-circuit, and a second reset sub-circuit. The light emitting control sub-circuit is configured to supply a fifth power supply signal transmitted by the third power supply line to the drive sub-circuit under the control of the light emitting control signal. The drive sub-circuit is configured to drive the light emitting element to emit light using the fifth power supply signal. The second reset sub-circuit is electrically connected to the anode of the light emitting element and is configured to reset the anode of the light emitting element under the control of the second reset control signal. In some examples, the light emitting control sub-circuit may include a first light emitting control sub-circuit and a second light emitting control sub-circuit.
In some exemplary embodiments, as shown in
In some exemplary embodiments, the seven transistors of the pixel circuit may be P-type transistors, or may be N-type transistors. Adopting a same type of transistors in a pixel circuit may simplify a process flow, reduce a process difficulty of a display substrate, and improve a yield of products. In some possible embodiments, the seven transistors in the pixel circuit may include P-type transistors and N-type transistors.
In some exemplary embodiments, the seven transistors in the pixel circuit may be low temperature poly-silicon thin film transistors, or may be oxide thin film transistors, or may be low temperature poly-silicon thin film transistors and oxide thin film transistors. An active layer of a Low Temperature Poly-Silicon thin film transistor is made of Low Temperature Poly-Silicon (LTPS), and an active layer of an oxide thin film transistor is made of an oxide semiconductor (Oxide). A Low-temperature Poly-Silicon thin film transistor has advantages such as a high mobility and fast charging, while an oxide thin film transistor has an advantage such as a low leakage current. The Low Temperature Poly-Silicon thin film transistor and the oxide thin film transistor are integrated on one display substrate to form a Low Temperature Polycrystalline Oxide (LTPO) display substrate, and advantages of both the Low Temperature Poly-Silicon thin film transistor and the oxide thin film transistor may be utilized, which may achieve low frequency drive, reduce power consumption, and improve display quality.
In some exemplary embodiments, as shown in
In some exemplary embodiments, the first initial signal line INIT1 is configured to provide a first initial signal to the pixel circuit, and the second initial signal line INIT2 is configured to provide a second initial signal to the pixel circuit. The magnitude of the first initial signal and the second initial signal may be the same or different. For example, the first initial signal and the second initial signal may be constant voltage signals whose magnitude may be between the fifth power supply signal and the sixth power supply signal, for example. In some examples, the voltage value of the second initial signal may be less than the voltage value of the first initial signal. For example, the voltage value of the second initial signal may be 2V lower than the voltage value of the first initial signal. However, this embodiment is not limited thereto.
In some exemplary implementations, as shown in
In this example, a first pixel node P1 is a connection point for the storage capacitor Cst, the first reset transistor M1, the drive transistor M3, and the threshold compensation transistor M2, a second pixel node P2 is a connection point for the first light emitting control transistor M5, the data writing transistor M4, and the drive transistor M3, a third pixel node P3 is a connection point for the drive transistor M3, the threshold compensation transistor M2, and the second light emitting control transistor M6, and a fourth pixel node P4 is a connection point for the second light emitting control transistor M6, the second reset transistor M7, and the light emitting element EL.
A working process of the pixel circuit shown in
In some exemplary implementation modes, as shown in
The first stage S11 is referred to as a first reset stage. The second reset control signal RESET2 provided by the second reset control line RST2 is a low-level signal, the second reset transistor M7 is turned on, and the second initial signal supplied by the second initial signal line INIT2 is supplied to the fourth pixel node P4 to reset the anode of the light emitting element EL. The first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, the scan signal SCAN provided by the scan line GL is a high-level signal, and the light emitting control signal EM provided by the light emitting control line EML is a high-level signal. The first reset transistor M1, the data writing transistor M4, the threshold compensation transistor M2, the first light emitting control transistor M5 and the second light emitting control transistor M6 are all turned off. In this stage, the light emitting element EL does not emit light.
The second stage S12 is referred to as a second reset stage. The first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, and the first reset transistor M1 is turned on. The first initial signal provided by the first initial signal line INIT1 is provided to the first pixel node P1 to initialize the first pixel node P1 and clear the original data voltage in the storage capacitor Cst. A scan signal SCAN provided by the scan line GL is a high-level signal, and a light emitting control signal EM provided by the light emitting control line EML is a high-level signal, so that the data writing transistor M4, the threshold compensation transistor M2, the first light emitting control transistor M5, and the second light emitting control transistor M6 are turned off. The second reset control signal RESET2 supplied by the second reset control line RST2 is a low-level signal, and the second reset transistor M7 is turned on to reset the anode of the light emitting element EL. In this stage, the light emitting element EL does not emit light.
The third stage S13 is referred to as a data writing stage or a threshold compensation stage. A scan signal SCAN provided by the scan line GL is a low-level signal, a first reset control signal RESET1 provided by the first reset control line RST1 and an emitting control signal EM provided by the emitting control line EML are both high-level signals, and the data line DL outputs a data signal DATA. In this phase, the first electrode plate of the storage capacitor Cst is at a low-level, such that the drive transistor M3 is turned on. The scan signal SCAN is a low-level signal, so that the threshold compensation transistor M2, and the data writing transistor M4 are turned on. The threshold compensation transistor M2 and the data writing transistor M4 are turned on, so that the data voltage output by the data line DL is provided to the first pixel node P1 through the second pixel node P2, the turned-on drive transistor M3, the third pixel node P3, and the turned-on threshold compensation transistor M2, and charge the difference between the data voltage output by the data line DL and the threshold voltage of the drive transistor M3 into the storage capacitor Cst. The voltage of the first electrode plate of the storage capacitor Cst (that is, the first pixel node P1) is Vdata−|Vth|, where Vdata is the data voltage output from the data line DL, and Vth is the threshold voltage of the drive transistor M3. The second reset control signal RESET2 supplied by the second reset control line RST2 is a low-level signal, and the second reset transistor M7 is turned on, so that the second initial signal supplied by the second initial signal line INIT2 is supplied to the anode of the light emitting element EL to ensure that the light emitting element EL does not emit light. The first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, so that the first reset transistor M1 is turned off. The light emitting control signal EM provided by the light emitting control signal line EML is a high-level signal, so that the first light emitting control transistor M5 and the second light emitting control transistor M6 are turned off.
The fourth stage S14 is referred to as a light emitting stage. The light emitting control signal EM provided by the light emitting control signal line EML is a low-level signal, so that the first light emitting control transistor M5 and the second light emitting control transistor M6 are turned on, and a fifth power supply signal of the high-level output by the fifth power supply line VDD provides a drive voltage to the anode of the light emitting element EL through the turned-on first light emitting control transistor M5, the drive transistor M3, and the second light emitting control transistor M6 to drive the light emitting element EL to emit light. The scan signal SCAN supplied by the scan line GL, the first reset control signal RESET1 supplied by the first reset control line RST1, and the second reset control signal RESET2 supplied by the second reset control line RST2 are all high-level signals, and the threshold compensation transistor M2, the data writing transistor M4, the first reset transistor M1, and the second reset transistor M7 are all turned off.
In a drive process of the pixel circuit, a drive current flowing through the drive transistor M3 is determined by a voltage difference between the gate and the first electrode of the drive transistor T3. Because the voltage of the first pixel node P1 is Vdata−|Vth|, the drive current of the drive transistor M3 is as follows.
I=K×(Vgs−Vth)2=K×[(Vdd−Vdata+|Vth|)−Vth]2=K×[Vdd−Vdata]2.
Among them, I is the drive current flowing through the drive transistor M3, that is, the drive current for driving the light emitting element EL; K is a constant; Vgs is the voltage difference between the gate and the first electrode of the drive transistor M3; Vth is the threshold voltage of the drive transistor M3; Vdata is the data voltage output by the data line DL, and Vdd is the fifth power supply signal output from the fifth power supply line VDD.
It may be seen from the above formula that a current flowing through the light emitting element EL has nothing to do with the threshold voltage of the drive transistor M3. Therefore, the pixel circuit of this embodiment may better compensate the threshold voltage of the drive transistor M3.
In some exemplary embodiments, within the duration of one frame, the overlapping duration between the reset duration of the anode of the light emitting element under the control of the second reset control signal and the duration during which the light emitting element is not driven by the light emitting control signal may be longer than twice the effective level duration of the scan signal supplied by the scan line. For example, the overlapping duration may be approximately three times the effective level duration of the scan signal. The effective level of the scan signal supplied by the scan line may be a low-level.
The present embodiment provides a drive control circuit, which can simultaneously provide a light emitting control signal and a second reset control signal to a pixel circuit in a display region, so that the pixel circuit can control the anode of a light emitting element to be reset by using the second reset control signal, and then control the light emitting element to emit light by using the light emitting control signal. In this example, the reset time of the fourth pixel node under the control of the second reset control signal is longer than the reset time of the first pixel node under the control of the first reset control signal.
In some implementations, the mobility of the hole transport material of the organic small molecule used in the organic light emitting layer of the light emitting element is generally two orders of magnitude higher than that of the electron transport material. Therefore, with the increase of the luminescent duration of the light emitting element, redundant holes will remain, resulting in leakage current and affecting the service life of the light emitting element. The second reset control signal supplied by the embodiment can increase the anode reset time of the light emitting element, so as to maintain the anode reset voltage of the light emitting element for a long time and avoid the formation of leakage current, thereby prolonging the service life of the light emitting element. Moreover, the number of gate drive circuits in the non-display region of the display substrate can be reduced to reduce the area of the circuit of the non-display region, which is beneficial to achieving the narrow bezel design of the display substrate.
In some examples, the first power supply line VGH1 and the third power supply line VGH2 may be the same power supply line and the first power supply signal and the third power supply signal may be the same. Alternatively, the first power supply line VGH1 and the third power supply line VGH2 may be two different power supply lines, and the first power supply signal supplied by the first power supply line VGH1 and the third power supply signal supplied by the third power supply line VGH2 may be the same. Alternatively, the first power supply line VGH1 and the third power supply line VGH2 may be two different power supply lines, and the first power supply signal and the third power supply signal may be different. However, this embodiment is not limited thereto.
In some examples, the second power supply line VGL1 and the fourth power supply line VGL2 may be the same power supply line, and the second power supply signal and the fourth power supply signal may be the same. Alternatively, the second power supply line VGL1 and the fourth power supply line VGL2 may be two different power supply lines, and the second power supply signal supplied by the second power supply line VGL1 and the fourth power supply signal supplied by the fourth power supply line VGL2 may be the same. Alternatively, the second power supply line VGL1 and the fourth power supply line VGL2 may be two different power supply lines, and the second power supply signal and the fourth power supply signal may be different. However, this embodiment is not limited thereto.
In some examples, the phases of the output signal of the first output terminal OUT1 and the output signal of the second output terminal OUT2 may be opposite. However, this embodiment is not limited thereto. For example, the absolute values of the voltages of the effective level of the output signal of the first output terminal OUT1 and the output signal of the second output terminal OUT2 may be different.
The drive control circuit provided in this embodiment can provide two kinds of signals (i.e., a light emitting control signal and a second reset control signal) to the pixel circuit. Moreover, the second reset control signal generated by the drive control circuit can maintain the anode reset voltage of the light emitting element for a long time, thus avoiding the formation of leakage current, thereby prolonging the service life of the light emitting element.
In some examples, as shown in
In this example, the first node N1 is a connection point of the seventh transistor T7, the eighth transistor T8, the first output transistor T9, the third output transistor T11, the first capacitor C1, and the fourth capacitor C4. The second node N2 is a connection point of the second transistor T2, the third transistor T3, the fourth transistor T4, the eighth transistor T8, the tenth transistor T10, the twelfth transistor T12 and the third capacitor C3. The third node N3 is a connection point of the first transistor T1, the third transistor T3, the fifth transistor T5, the sixth transistor T6 and the second capacitor C2.
In some examples, transistors T1 to T12 are of the same type, for example, they are all P-type transistors. However, this embodiment is not limited thereto. For example, a plurality of transistors may all be N-type transistors. In some examples, the P-type transistor may be an LTPS thin film transistor and the N-type transistor may be an oxide thin film transistor such as an IGZO thin film transistor. However, this embodiment is not limited thereto.
In other exemplary embodiments, in
As shown in
The first stage S21 is referred to as a first shift stage. The signal input terminal INT provides a high-level signal, the first clock terminal CK provides a low-level signal, and the second clock terminal CB provides a high-level signal.
The first clock terminal CK provides a low-level signal, and the fourth transistor T4 and the fifth transistor T5 are turned on. The fourth transistor T4 is turned on, the second node N2 is at a high potential, and the third transistor T3, the eighth transistor T8, the second output transistor T10 and the fourth output transistor T12 are turned off. The fifth transistor T5 is turned on, the third node N3 is at a low potential, and the first transistor T1 and the sixth transistor T6 are turned on.
The second clock terminal CB provides a high-level signal, and the second transistor T2 and the seventh transistor T7 are turned off. The first node N1 maintains the high potential of the previous stage, and the first output transistor T9 and the third output transistor T11 are turned off. Because both the first output transistor T9 and the second output transistor T10 are turned off, the first output terminal OUT1 maintains the low-level signal before output. Because both the third output transistor T11 and the fourth output transistor T12 are turned off, the second output terminal OUT2 maintains the high-level signal before output.
In the second stage S22, it is referred to as an output stage. The signal input terminal INT provides a high-level signal, the first clock terminal CK provides a high-level signal, and the second clock terminal CB provides a low-level signal.
The second clock terminal CB provides a low-level signal, and the second transistor T2 and the seventh transistor T7 are turned on. The first clock terminal CK provides a high-level signal, the fourth transistor T4 and the fifth transistor T5 are turned off, and the third node N3 maintains the low potential of the previous stage under the storage function of the second capacitor C2. The first transistor T1 and the sixth transistor T6 are turned on. The high-level signal supplied by the first power supply line VGH1 is transmitted to the second node N2 through the first transistor T1 and the second transistor T2 which are turned on, so that the second node N2 is held at a high potential, so that the third transistor T3, the eighth transistor T8, the second output transistor T10 and the fourth output transistor T12 are all turned off.
A low-level signal supplied by the second clock terminal CB is transmitted to the first node N1 through a sixth transistor T6 and a seventh transistor T7 which are turned on, so that the first node N1 is at a low potential, and the first output transistor T9 and the third output transistor T11 are turned on. The first output terminal OUT1 outputs a high-level signal supplied by the first power supply line VGH1, and the second output terminal OUT2 outputs a low-level signal supplied by the fourth power supply line VGL2.
The third stage S23 is referred to as a continuous output stage. The signal input terminal INT provides a high-level signal, the first clock terminal CK provides a low-level signal, and the second clock terminal CB provides a high-level signal.
The first clock terminal CK provides a low-level signal, and the fourth transistor T4 and the fifth transistor T5 are turned on. The fourth transistor T4 is turned on, so that the second node N2 is at a high potential, and the third transistor T3, the eighth transistor T8, the second output transistor T10 and the fourth output transistor T12 are turned off. The fifth transistor T5 is turned on, so that the third node T3 is at a low potential, and the first transistor T1 and the sixth transistor T6 are turned on. The second clock terminal CB provides a high-level signal, and the second transistor T2 and the seventh transistor T7 are turned off. The first node N1 maintains the low potential of the previous stage, and the first output transistor T9 and the third output transistor T11 are turned on. The first output terminal OUT1 outputs a high-level signal supplied by the first power supply line VGH1, and the second output terminal OUT2 outputs a low-level signal supplied by the fourth power supply line VGL2.
The fourth stage S24 is referred to as a second shift stage. The signal input terminal INT provides a low-level signal, the first clock terminal CK provides a high-level signal, and the second clock terminal CB provides a low-level signal.
The second clock terminal CB provides a low-level signal, and the second transistor T2 and the seventh transistor T7 are turned on. The first clock terminal CK provides a high-level signal, and the fourth transistor T4 and the fifth transistor T5 are turned off. Under the storage function of the third capacitor C3, the second node N2 maintains the high potential of the previous stage, and the third transistor T3, the eighth transistor T8, the second output transistor T10 and the fourth output transistor T12 are all turned off. Under the storage function of the second capacitor C2, the third node N3 maintains a low potential, and the first transistor T1 and the sixth transistor T6 are turned on. A low-level signal supplied by the second clock terminal CB is transmitted to the first node N1 through a sixth transistor T6 and a seventh transistor T7 which are turned on, so that the first node N1 is at a low potential, and the first output transistor T9 and the third output transistor T11 are turned on. The first output terminal OUT1 outputs a high-level signal supplied by the first power supply line VGH1, and the second output terminal OUT2 outputs a low-level signal supplied by the fourth power supply line VGL2.
The fifth stage S25 is referred to as a pull-down stage. The signal input terminal INT provides a low-level signal, the first clock terminal CK provides a low-level signal, and the second clock terminal CB provides a high-level signal.
The first clock terminal CK provides a low-level signal, and the fourth transistor T4 and the fifth transistor T5 are turned on. The second node N2 is at a low potential, and the third transistor T3, the eighth transistor T8, the second output transistor T10 and the fourth output transistor T12 are all turned on. The third node N3 is at a low potential, and the first transistor T1 and the sixth transistor T6 are turned on. The second clock terminal CB provides a high-level signal, and the second transistor T2 and the seventh transistor T7 are turned off. The first node N1 is at a high potential, and the first output transistor T9 and the third output transistor T11 are turned off. The first output terminal OUT1 outputs a low-level signal supplied by the second power supply line VGL1, and the second output terminal OUT2 outputs a high-level signal supplied by the third power supply line VGH1.
The sixth stage S26 is referred to as a stable stage. The signal input terminal INT provides a low-level signal, the first clock terminal CK provides a high-level signal, and the second clock terminal CB provides a low-level signal.
The first clock terminal CK provides a high-level signal, and the fourth transistor T4 and the fifth transistor T5 are turned off. The second node N2 remain a low potential, and the third transistor T3, the eighth transistor T8, the second output transistor T10 and the fourth output transistor T12 are all turned on. The third node N3 is at a high potential, and the first transistor T1 and the sixth transistor T6 are turned off. The second clock terminal CB provides a low-level signal, and the second transistor T2 and the seventh transistor T7 are turned on. The first node N1 is at a high potential, and the first output transistor T9 and the third output transistor T11 are turned off. The first output terminal OUT1 outputs a low-level signal supplied by the second power supply line VGL1, and the second output terminal OUT2 outputs a high-level signal supplied by the third power supply line VGH2.
After the sixth stage S26, the fifth stage S25 and the sixth stage S26 can be repeated until the signal input terminal INT inputs a high-level signal, and then restart from the first stage S21.
According to the working process of the drive control circuit, from the second stage S22 to the fourth stage S24, the first output terminal OUT1 may output a high-level signal supplied by the first power supply line VGH1, and the second output terminal OUT2 outputs a low-level signal supplied by the fourth power supply line VGL2. In other stages, the first output terminal OUT1 outputs a low-level signal supplied by the second power supply line VGL1, and the second output terminal OUT2 outputs a high-level signal supplied by the third power supply line VGH2. For example, the phases of the first output signal supplied by the first output terminal OUT1 and the second output signal supplied by the second output terminal OUT2 may be opposite. Taking the example where the effective level of the first output signal is high, and the effective level of the second output signal is low, within a frame duration, the effective level duration of the first output signal and the effective level duration of the second output signal may be approximately the same, and the absolute voltage value of the effective level of the first output signal and the absolute voltage value of the effective level of the second output signal may be approximately the same. Within a frame duration, the overlapping duration of the effective level (for example, high-level) of the first output signal and the effective level (for example, low-level) of the second output signal may be longer than one pulse period of the clock signal. The duty ratio of the first clock signal supplied by the first clock terminal and the second clock signal supplied by the second clock terminal may be the same, and the first clock signal and the second clock signal may be high voltage not at the same time. A duty ratio refers to a proportion of a high-level time length to a whole pulse period within a pulse period (including a high-level time length and a low-level time length). However, this embodiment is not limited thereto. In some examples, due to the presence of the rising edge and the falling edge of the signal, the first output signal may be gradually raised when the second output signal is not completely lowered. However, due to the very small time of the duration, it exceeds the recognition ability of the human eye and will not affect the luminescence of the light emitting element.
In some exemplary embodiments, a first output signal supplied by the first output terminal OUT1 may be provided to the pixel circuit as a light emitting control signal, and a second output signal supplied by the second output terminal OUT2 may be provided to the pixel circuit as a second reset control signal. In some examples, the first output signal supplied by the first output terminal of the drive control circuit of the current stage can be transmitted to the signal input terminal of the drive control circuit of the next stage to be as an input signal of the drive control circuit of the next stage. However, this embodiment is not limited thereto.
In some examples, as shown in
The connection relationship between the rest of the transistors and the capacitors of the drive control circuit of the present embodiment can be described as in the previous embodiment and is therefore not described here.
In this example, the first node N1 is a connection point of the seventh transistor T7, the eighth transistor T8, the first output transistor T9, the third output transistor T11, the first capacitor C1, and the fourth capacitor C4. The second node N2 is a connection point of the second transistor T2′, the third transistor T3, the fourth transistor T4, the eighth transistor T8, the tenth transistor T10, the twelfth transistor T12 and the third capacitor C3′. The third node N3 is a connection point of the first transistor T1′, the third transistor T3, the fifth transistor T5, the sixth transistor T6 and the second capacitor C2.
In other exemplary embodiments, in
The operation process of the drive control circuit shown in
As shown in
In the first stage S21, the first clock terminal CK inputs a low-level signal, the second clock terminal CB inputs a high-level signal, and the signal input terminal INT inputs a high-level signal.
The fourth transistor T4 and the fifth transistor T5 are turned on, the second node N2 is at a high potential, and the third transistor T3, the second transistor T2′, the eighth transistor T8, the second output transistor T10 and the fourth output transistor T12 are turned off. The third node N3 is at a low potential, and the first transistor T1′ and the sixth transistor T6 are turned on. The second clock terminal CB inputs a high-level, and the seventh transistor T7 is turned off. The first node N1 maintains the high potential of the previous stage, and the first output transistor T9 and the third output transistor T11 are turned off. The first output terminal OUT1 maintains the low-level signal before output, and the second output terminal OUT2 maintains the high-level signal before output.
In the second stage S22, the first clock terminal CK inputs a high-level signal, the second clock terminal CB inputs a low-level signal, and the signal INPUT terminal INPUT inputs a high-level signal.
The fourth transistor T4 and the fifth transistor T5 are turned off, the second node N2 remains at a high potential, and the third transistor T3, the second transistor T2′, the eighth transistor T8, the second output transistor T10 and the fourth output transistor T12 are turned off. The third node N3 remains at a low potential, and the first transistor T1′ and the sixth transistor T6 are turned on. The second clock terminal CB inputs a low-level signal, and the seventh transistor T7 is turned on. The first node N1 is at a low potential, and the first output transistor T9 and the third output transistor T11 are turned on. The first output terminal OUT1 outputs a high-level signal supplied by the first power supply line VGH1, and the second output terminal OUT2 outputs a low-level signal supplied by the fourth power supply line VGL2.
In the third stage S23, the first clock terminal CK inputs a low-level signal, the second clock terminal CB inputs a high-level signal, and the signal input terminal INPUT inputs a high-level signal.
The fourth transistor T4 and the fifth transistor T5 are turned on, the second node N2 is at a high potential, and the third transistor T3, the second transistor T2′, the eighth transistor T8, the second output transistor T10 and the fourth output transistor T12 are turned off. The third node N3 is at a low potential, and the first transistor T1′ and the sixth transistor T6 are turned on. The second clock terminal CB inputs a high-level signal, and the seventh transistor T7 is turned off. The first node N1 remains at a low potential, and the first output transistor T9 and the third output transistor T11 are turned on. The first output terminal OUT1 outputs a high-level signal supplied by the first power supply line VGH1, and the second output terminal OUT2 outputs a low-level signal supplied by the fourth power supply line VGL2.
In the fourth stage S24, the first clock terminal CK inputs a high-level signal, the second clock terminal CB inputs a low-level signal, and the signal INPUT terminal INPUT inputs a low-level signal.
The fourth transistor T4 and the fifth transistor T5 are turned off, the second node N2 is at a high potential, and the third transistor T3, the second transistor T2′, the eighth transistor T8, the second output transistor T10 and the fourth transistor T12 are turned off. The third node N3 remains at a low potential, and the first transistor T1′ and the sixth transistor T6 are turned on. The second clock terminal CB supplies a low-level signal, and the seventh transistor T7 is turned on. The first node N1 is at a low potential, and the first output transistor T9 and the third output transistor T11 are turned on. The first output terminal OUT1 outputs a high-level signal supplied by the first power supply line VGH1, and the second output terminal OUT2 outputs a low-level signal supplied by the fourth power supply line VGL2.
In the fifth stage S25, the first clock terminal CK inputs a low-level signal, the second clock terminal CB inputs a high-level signal, and the signal input terminal INPUT inputs a low-level signal.
The fourth transistor T4 and the fifth transistor T5 are turned on, the second node N2 is at a low potential, and the third transistor T3, the second transistor T2′, the eighth transistor T8, the second output transistor T10 and the fourth output transistor T12 are turned on. The third node N3 is at a low potential, and the first transistor T1′ and the sixth transistor T6 are turned on. The second clock terminal CB inputs a high-level signal, and the seventh transistor T7 is turned off. The first node N1 is at a high potential, and the first output transistor T9 and the third output transistor T11 are turned off. The first output terminal OUT1 outputs a low-level signal supplied by the second power supply line VGL1, and the second output terminal OUT2 outputs a high-level signal supplied by the third power supply line VGH2.
In the sixth stage S26, the first clock terminal CK inputs a high-level signal, the second clock terminal CB inputs a low-level signal, and the signal INPUT terminal INPUT inputs a low-level signal.
The fourth transistor T4 and the fifth transistor T5 are turned off, the second node N2 remains at a low potential, and the third transistor T3, the second transistor T2′, the eighth transistor T8, the second output transistor T10 and the fourth output transistor T12 are turned on. The third node N3 is at a high potential, and the first transistor T1′ and the sixth transistor T6 are turned off. The second clock terminal CB inputs a low-level signal, and the seventh transistor T7 is turned on. The first node N1 is at a high potential, and the first output transistor T9 and the third output transistor T11 are turned off. The first output terminal OUT1 outputs a low-level signal supplied by the second power supply line VGL1, and the second output terminal OUT2 outputs a high-level signal supplied by the third power supply line VGH2.
For the rest of the description about the working sequence of the drive control circuit of this embodiment, reference may be made to the description of the foregoing embodiment, so details are not repeated here.
In a drive control circuit provided by the present exemplary embodiment, the first output transistor T9 and the second output transistor T10 may be used to control the output of the light emitting control signal, and the third output transistor T11 and the fourth output transistor T12 may be used to control the output of the second reset control signal, thereby avoiding the risk of causing excessive output burden of the light emitting control signal or the second reset control signal.
The drive control circuit provided by the present exemplary embodiment supplies a second reset control signal to the pixel circuit. The pixel circuit may use the second reset control signal to write a second initial signal lower than the first initial signal to the anode of the light emitting element, so as to improve the anode reset effect. The second reset control signal of the embodiment can prolong the reset time of the anode of the light emitting element, avoid the formation of leakage current, and prolong the service life of the light emitting element.
In the present exemplary embodiment, as shown in
In the present exemplary embodiment, as shown in
In some exemplary embodiments, as shown in
In some exemplary embodiments, as shown in
In some exemplary embodiments, as shown in
In some exemplary embodiments, as shown in
In some examples, a material of the semiconductor layer 40, for example, may include poly-silicon. An active layer may include at least one channel region and a plurality of doped regions. The channel region may not be doped with an impurity, and has characteristics of a semiconductor. The plurality of doped regions may be on two sides of the channel region and doped with impurities, and thus have conductivity. The impurities may be changed according to the type of the transistor. A doped region of the active layer may be interpreted as a source or a drain of a transistor. For example, a first electrode of the transistor may correspond to the first doped region at a periphery of the channel region of the active layer and doped with impurities, and a second electrode of the transistor may correspond to the second doped region at the periphery of the channel region of the active layer and doped with impurities. In addition, portions of the active layers between the transistors may be interpreted as wirings doped with impurities, and may be used for electrically connecting the transistors.
In some examples, as shown in
In some examples, as shown in
In some examples, as shown in
In some examples, as shown in
In some examples, as shown in
In some examples, as shown in
In some examples, as shown in
In some examples, as shown in
In some examples, as shown in
In some examples, as shown in
In some examples, as shown in
In some examples, the twelfth connection electrode L12 may be electrically connected to the first doped region 150Ab of the active layer 150A of the fifth transistor T5 through the fifth via hole K5, may be electrically connected to the first doped region 200Ab1 of the first partition 200A1 of the active layer of the second output transistor T10 through a plurality (e.g. three) of the twelfth via hole K12 arranged side by side, may be electrically connected to the fifth doped region 200Ab3 of the second partition 200A2 of the active layer of the second output transistor T10 through a plurality (e.g. three) of the thirteenth via hole K13 arranged side by side, may be electrically connected to the third doped region 200Ab2 of the first partition 200A1 of the active layer of the second output transistor T10 through a plurality (e.g. three) of the sixteenth via holes K16 arranged side by side, and may be electrically connected to the seventh doped region 200Ab4 of the second partition 200A2 of the active layer of the second output transistor T10 through a plurality (e.g. three) of the seventeenth via hole K17 arranged side by side. The twelfth connection electrode L12 and the second power supply line VGL1 may be of an integrated structure.
In some examples, the thirteenth connection electrode L13 may be electrically connected to the second doped region 200Ac1 of the first partition 200A1 of the active layer of the second output transistor T10 through a plurality (e.g. three) of the fourteenth via hole K14 arranged side by side, may be electrically connected to the sixth doped region 200Ac3 of the second partition 200A2 of the active layer of the second output transistor T10 through a plurality (e.g. three) of the fifteenth via hole K15 arranged side by side, may be electrically connected to the fourth doped region 200Ac2 of the first partition 200A1 of the active layer of the second output transistor T10 through a plurality (e.g. three) of the eighteenth via hole K18 arranged side by side, may be electrically connected to the eighth doped region 200Ac4 of the second partition 200A2 of the active layer of the second output transistor T10 through a plurality (e.g. three) of the nineteenth via hole K19 arranged side by side, may be electrically connected to the second doped region 190Ac1 of the first partition 190A1 of the active layer of the first output transistor T9 through a plurality (e.g. three) of the twenty-second via hole K22 arranged side by side, may be electrically connected to the eighth doped region 190Ac4 of the second partition 190A2 of the active layer of the first output transistor T9 through a plurality (e.g. three) of the twenty-third via hole K23 arranged side by side, and may be electrically connected to the first output terminal OUT1 through two fifty-sixth via holes K56 arranged side by side.
In some examples, the fourteenth connection electrode L14 may be electrically connected to the first doped region 190Ab1 of a first partition 190A1 of the active layer of the first output transistor T9 through a plurality (e.g. three) of the twentieth via hole K20 arranged side by side, may be electrically connected to the fifth doped region 190Ab3 of the second partition 190A2 of the active layer of the first output transistor T9 through a plurality (e.g. three) of the twenty-first via hole K21 arranged side by side, and may be electrically connected to the second electrode plate C1-2A of the first capacitor C1 through the sixty-second via hole K62.
In some examples, the fifteenth connection electrode L15 may be electrically connected to the third doped region 190Ab2 of a first partition 190A1 of the active layer of the first output transistor T9 through a plurality (e.g. three) of the twenty-fourth via hole K24 arranged side by side, may be electrically connected to the seventh doped region 190Ab4 of the second partition 190A2 of the active layer of the first output transistor T9 through a plurality (e.g. three) of the twenty-fifth via hole K25 arranged side by side, and may be electrically connected to the second electrode plate C1-2A of the first capacitor C1 through the sixty-third via hole K63.
In some examples, the sixteenth connection electrode L16 may be electrically connected to the first doped region 180Ab of the active layer 180A of the eighth transistor T8 through the twenty-sixth via hole K26, and may be electrically connected to the second connection electrode L2 through the fifty-first via hole K51. The second connection electrode L2 may be electrically connected to the twenty-second connection electrode L22 through the fifty-third via hole K53. The seventeenth connection electrode L17 may be electrically connected to the second doped region 180Ac of the active layer 180A of the eighth transistor T8 through the twenty-seventh via hole K27, and may be electrically connected to the first electrode plate C1-1A of the first capacitor C1 through the fifty-second via hole K52.
In some examples, the eighteenth connection electrode L18 may be electrically connected to the first doped region 220Ab1 of a first partition 220A1 of the active layer of the fourth output transistor T12 through a plurality (e.g. three) of the twenty-eighth via hole K28 arranged side by side, may be electrically connected to the fifth doped region 220Ab3 of the second partition 220A2 of the active layer of the fourth output transistor T12 through a plurality (e.g. three) of the twenty-ninth via hole K29 arranged side by side, may be electrically connected to the third doped region 220Ab2 of the first partition 220A1 of the active layer of the fourth output transistor T12 through a plurality (e.g. three) of the thirty-second via hole K32 arranged side by side, may be electrically connected to the seventh doped region 220Ab4 of the second partition 220A2 of the active layer of the fourth output transistor T12 through a plurality (e.g. three) of the thirty-third via hole K33 arranged side by side, and may be electrically connected to the first connection electrode L1 through two fifty-fourth via holes K54 arranged side by side. The first connection electrode LI may be electrically connected to the twenty-third connection electrode L23 through two fifty-fifth via holes K55 arranged vertically.
In some examples, the nineteenth connection electrode L19 may be electrically connected to the first doped region 210Ab1 of a first partition 210A1 of the active layer of the third output transistor T11 through a plurality (e.g. three) of the thirty-sixth via hole K36 arranged side by side, may be electrically connected to the fifth doped region 210Ab3 of the second partition 210A2 of the active layer of the third output transistor T11 through a plurality (e.g. three) of the thirty-seventh via hole K37 arranged side by side, and may be electrically connected to the second electrode plate C4-2A of the fourth capacitor C4 through the sixty-fourth via hole K64.
In some examples, the twentieth connection electrode L20 may be electrically connected to the second doped region 220Ac1 of a first partition 220A1 of the active layer of the fourth output transistor T12 through a plurality (e.g. three) of the thirtieth via hole K30 arranged side by side, may be electrically connected to the sixth doped region 220Ac3 of the second partition 220A2 of the active layer of the fourth output transistor T12 through a plurality (e.g. three) of the thirty-first via hole K31 arranged side by side, may be electrically connected to the fourth doped region 220Ac2 of the first partition 220A1 of the active layer of the fourth output transistor T12 through a plurality (e.g. three) of the thirty-fourth via hole K34 arranged side by side, may be electrically connected to the eighth doped region 220Ac4 of the second partition 220A2 of the active layer of the fourth output transistor T12 through a plurality (e.g. three) of the thirty-fifth via hole K35 arranged side by side, may be electrically connected to the fourth doped region 210Ac2 of the first partition 210A1 of the active layer of the third output transistor T11 through a plurality (e.g. three) of the thirty-eighth via hole K38 arranged side by side, may be electrically connected to the eighth doped region 210Ac4 of the second partition 210A2 of the active layer of the third output transistor T11 through a plurality (e.g. three) of the thirty-ninth via hole K39 arranged side by side, and may be electrically connected to the second output terminal OUT2 through two fifty-eighth via holes K58 arranged side by side.
In some examples, the twenty-first connection electrode L21 may be electrically connected to the third doped region 210Ab2 of the first partition 210A1 of the active layer of the third output transistor T11 through a plurality (e.g. three) of the fortieth via hole K40 arranged side by side, may be electrically connected to the seventh doped region 210Ab4 of the second partition 210A2 of the active layer of the third output transistor T11 through a plurality (e.g. three) of the forty-first via hole K41 arranged side by side, and may be electrically connected to the second electrode plate C4-2A of the fourth capacitor C4 through the sixty-fifth via hole K65.
In some examples, the third connection electrode L3 may be electrically connected to the twenty-fourth connection electrode L24 through two sixty-seventh via holes K67 arranged vertically. The twenty-second connection electrode L22, the twenty-third connection electrode L23, and the twenty-fourth connection electrode L24 may be electrically connected to a third power supply line near the display region side, for example, may be integrated with the third power supply line. The third power supply line may be configured to provide a high-level power supply signal to an adjacent gate drive circuit. However, this embodiment is not limited thereto.
In some examples, the twenty-fifth connection electrode L25 may be electrically connected to the first output terminal OUT1 through two fifty-seventh via holes K57 arranged side by side. The twenty-sixth connection electrode L26 may be electrically connected to the second output terminal OUT2 through two fifty-ninth via holes K59 arranged side by side. The twenty-fifth connection electrode L25 and the twenty-sixth connection electrode L26 may extend in the first direction X. For example, the twenty-fifth connection electrode L25 may be electrically connected to the light emitting control line to supply the light emitting control signal to the pixel circuit of the display region, and the twenty-sixth connection electrode L26 may be electrically connected to the second reset control line to supply the second reset control signal to the pixel circuit of the display region. However, this embodiment is not limited thereto.
In some examples, the second power supply line VGL1 may be electrically connected to the fourth connection electrode L4 through two sixty-sixth via holes K66 arranged vertically.
In the embodiments of the present disclosure, “disposed side by side” may mean being disposed in sequence along the first direction X, and “disposed vertically” may mean being disposed in sequence along the second direction Y.
In the present exemplary embodiment, electrical connection with the first clock signal line CKL is achieved through the control electrodes of the fourth transistor and the fifth transistor. The electrical connection to the second clock signal line CBL is achieved through a control electrode of the second transistor and an eleventh connection electrode L11. The electrical connection between the second power supply line VGL1 and the second output circuit is achieved through the fourth connection electrode L4. The transmission of a second power supply signal to the first output circuit is achieved through a third connection electrode L3 and a twenty-fourth connection electrode L24. The electrical connection between the first output circuit, the input circuit, and the first power supply line is achieved through the twelfth connection electrode L12. The transmission of the first power signal to the second output circuit is achieved through the twenty-third connection electrode L23 and the first connection electrode L1.
In the display substrate provided by the exemplary embodiment, a light emitting control signal and a second reset control signal are provided to a pixel circuit by a drive control circuit, thereby saving arrangement space and achieving a display substrate with a narrow bezel design.
In some exemplary embodiments, as shown in
In some exemplary embodiments, as shown in
In some exemplary embodiments, as shown in
In some exemplary embodiments, as shown in
In some examples, as shown in
In some examples, as shown in
In some examples, the active layer 190B of the first output transistor T9 includes channel regions 190Ba1, 190Ba2, 190Ba3, and 190Ba4 arranged in sequence along the first direction X, a first doped region 190Bb1 and a second doped region 190Bc1 on both sides of the channel region 190Ba1 along the first direction X, a third doped region 190Bb2 and a fourth doped region 190Bc2 on both sides of the channel region 190Ba4 along the first direction X, and a fifth doped region 190Bc3 between the channel regions 190Ba2 and 190Ba3. The third doped region 190Bb2 is located between channel regions 190Ba3 and 190Ba4, and the first doped region 190Bb1 is located between channel regions 190Ba1 and 190Ba2.
In some examples, the active layer 200B of the second output transistor T10 includes channel regions 200Ba1, 200Ba2, 200Ba3, and 200Ba4 arranged in sequence along the first direction X, a first doped region 200Bb1 and a second doped region 200Bc1 on both sides of the channel region 200Ba1 along the first direction X, a third doped region 200Bb2 and a fourth doped region 200Bc2 on both sides of the channel region 200Ba4 along the first direction X, and a fifth doped region 200Bc3 between the channel regions 200Ba2 and 200Ba3. The third doped region 200Bb2 is located between channel regions 200Ba3 and 200Ba4, and the first doped region 200Bb1 is located between channel regions 200Ba1 and 200Ba2.
In some examples, the active layer 210B of the third output transistor T11 includes channel regions 210Ba1, 210Ba2, 210Ba3, and 210Ba4 arranged in sequence along the first direction X, a first doped region 210Bb1 and a second doped region 210Bc1 on both sides of the channel region 210Ba1 along the first direction X, a third doped region 210Bb2 and a fourth doped region 210Bc2 on both sides of the channel region 210Ba4 along the first direction X, and a fifth doped region 210Bc3 between the channel regions 210Ba2 and 210Ba3. The third doped region 210Bb2 is located between channel regions 210Ba3 and 210Ba4, and the first doped region 210Bb1 is located between channel regions 210Ba1 and 210Ba2.
In some examples, the active layer 220B of the fourth output transistor T12 includes channel regions 220Ba1, 220Ba2, 220Ba3, and 220Ba4 arranged in sequence along the first direction X, a first doped region 220Bb1 and a second doped region 220Bc1 on both sides of the channel region 220Ba1 along the first direction X, a third doped region 220Bb2 and a fourth doped region 220Bc2 on both sides of the channel region 220Ba4 along the first direction X, and a fifth doped region 220Bc3 between the channel regions 220Ba2 and 220Ba3. The third doped region 220Bb2 is located between channel regions 220Ba3 and 220Ba4, and the first doped region 220Bb1 is located between channel regions 220Ba1 and 220Ba2.
In some examples, as shown in
In some examples, the first output OUT1 includes a first portion 301 extending in a second direction Y, a second portion 302 and a third portion 303 extending in a first direction X. The first portion 301 of the first output OUT1 is located between the first output circuit and the second output circuit. The second portion 302 and the third portion 303 are located on the same side of the first output circuit and the second output circuit in the second direction Y. The second output terminal OUT2 includes a fourth portion 304 extending in the second direction Y and a fifth portion 305 extending in the first direction X. An orthographic projection of the second output terminal OUT2 on the substrate may be L-shaped. The fifth portion 305 is located on a side of the third portion 303 close to the second output circuit.
The first output terminal OUT1 of the current stage drive control circuit can be electrically connected with the signal input terminal of the next stage drive control circuit. However, this embodiment is not limited thereto.
In some examples, as shown in
In some examples, as shown in
In some examples, as shown in
In some examples, as shown in
In some examples, as shown in
In some examples, as shown in
In the display substrate provided by the exemplary embodiment, a light emitting control signal and a second reset control signal are provided to a pixel circuit by a drive control circuit, thereby saving arrangement space and achieving a display substrate with a narrow bezel design.
The structure of the display substrate will be described below through an example of a manufacturing process of the display substrate. A “patterning process” mentioned in the present disclosure includes processes, such as deposition of a film layer, photoresist coating, mask exposure, development, etching, and photoresist stripping. Deposition may be any one or more of sputtering, evaporation, and chemical vapor deposition. Coating may be any one or more of spray coating and spin coating. Etching may be any one or more of dry etching and wet etching. A “thin film” refers to a layer of a thin film prepared from a material on a substrate using a process of deposition or coating. If a patterning process is not needed for the “thin film” during a whole preparation process, the “thin film” may be referred to as a “layer”. When a patterning process is needed for the “thin film” during the whole preparation process, the thin film is referred to as a “thin film” before the patterning process and referred to as a “layer” after the patterning process. The “layer” after the patterning process at least includes one “pattern”.
“A and B are arranged in the same layer” mentioned in the present disclosure refers to that A and B are simultaneously formed by the same patterning process. The “thickness” of the thin film layer is a size of the film layer in a direction perpendicular to the display substrate. In the exemplary embodiment of the present disclosure, “a projection of A includes a projection of B” refers to that a boundary of a projection of B falls within a range of a boundary of a projection of A or the boundary of a projection of A is overlapped with the boundary of a projection of B.
The preparation process of the display substrate according to the exemplary embodiment may include following acts.
(1) A substrate is provided.
In some exemplary embodiments, a substrate 30 may be a rigid substrate or a flexible substrate. The rigid substrate may include one or more of glass and metal foil sheet. The flexible substrate may include one or more of polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylester, polyimide, polyvinyl chloride, polyethylene, and textile fiber.
(2) A pattern of a semiconductor layer is formed.
In some exemplary implementation modes, a semiconductor thin film is deposited on the substrate 30, and the semiconductor thin film is patterned through a patterning process to form a a semiconductor layer 40, as shown in
(3) A pattern of a first conductive layer is formed.
In some exemplary embodiments, a first insulating thin film and a first conductive thin film are sequentially deposited on the substrate 30 where the aforementioned pattern is formed, and the first conductive thin film is patterned through a patterning process to form a first insulating layer 31 covering the semiconductor layer 40 and form a first conductive layer 41 arranged on the first insulating layer 31, as shown in
(4) A pattern of a second conductive layer is formed.
In some exemplary implementations, a second insulation thin film and a second conductive thin film are sequentially deposited on the substrate 30 where the aforementioned patterns are formed, and the second conductive thin film is patterned through a patterning process to form a second insulating layer 32 covering the first conductive layer 41 and a second conductive layer 42 disposed on the second insulating layer 32, as shown in
(5) A pattern of a third insulating layer is formed.
In some exemplary embodiments, a third insulating thin film is deposited on the substrate 30 where the aforementioned patterns are formed, and the third insulating thin film is patterned through a patterning process to form a third insulating layer 33 covering the second conductive layer 42, as shown in
(6) A pattern of a third conductive layer is formed.
In some exemplary implementations, a third conductive thin film is deposited on the substrate 30 where the aforementioned patterns are formed, and the third conductive thin film is patterned through a patterning process to form a third conductive layer 43 on the third insulating layer 33, as shown in
In some exemplary embodiments, a pixel circuit may be formed in the display region while a drive control circuit is formed in the non-display region. For example, a semiconductor layer of the display region may include active layers of a plurality of transistors of a pixel circuit, a first conductive layer of the display region may include control electrodes of a plurality of transistors of the pixel circuit and a first electrode of a storage capacitor, a second conductive layer of the display region may at least include a second electrode of the storage capacitor of the pixel circuit, and a third conductive layer of the display region may at least include a first electrode and a second electrode of the transistor of the pixel circuit. However, this embodiment is not limited thereto.
In some exemplary implementations, after the third conductive layer is formed, patterns of a fourth insulating layer, an anode layer, a pixel definition layer, an organic light emitting layer, a cathode layer, and an encapsulation layer may be sequentially formed in the display region. In some examples, on a substrate where the aforementioned patterns are formed, a fourth insulation thin film is coated, and a pattern of a fourth insulating layer is formed through masking, exposing, and developing for the fourth insulation thin film. Then, an anode thin film is deposited on the substrate where the display region of the aforementioned patterns is formed, and the anode thin film is patterned through a patterning process to form a pattern of an anode on the fourth insulating layer. Next, on the substrate where the aforementioned patterns are formed, a pixel definition thin film is coated, and a pattern of a Pixel Definition layer (PDL) is formed through masking, exposure, and development processes. The pixel definition layer is formed in each sub-pixel in the display region. A pixel opening exposing the anode is formed in the pixel definition layer in each sub-pixel. Subsequently, the organic emitting layer connected to the anode is formed in the pixel opening formed before. Subsequently, a cathode thin film is deposited, and the cathode thin film is patterned through a patterning process to form a pattern of a cathode. Then, an encapsulation layer is formed on the cathode. The encapsulation layer may include a stacked structure of an inorganic material/an organic material/an inorganic material.
In some exemplary embodiments, the first conductive layer 41, the second conductive layer 42, and the third conductive layer 43 may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure, such as Mo/Cu/Mo. The first conductive layer 41 may also be referred to as a first gate metal layer, the second conductive layer 42 may also be referred to as a second gate metal layer, and the third conductive layer 43 may be referred to as a first source-drain metal layer. The first insulating layer 31 to the third insulating layer 33 may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be in a single layer, a plurality of layers, or a composite layer. The fourth insulating layer and the pixel definition layer may be made of the organic material, such as polyimide, acrylic, or polyethylene terephthalate, etc. The anode may be made of a transparent conductive material, e.g., Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). The cathode may be made of any one or more of Magnesium (Mg), Argentum (Ag), Aluminum (Al), Copper (Cu), and Lithium (Li), or an alloy made of any one or more of the aforementioned metals. However, this embodiment is not limited thereto. For example, the anode may be made of a reflective material such as a metal, and the cathode may be made of a transparent conductive material.
The structure shown in the exemplary embodiment and the preparation process thereof are merely illustrative. In some exemplary implementations, corresponding structures may be altered and patterning processes may be increased or decreased according to actual needs.
The manufacturing process of the exemplary embodiment may be implemented using an existing mature manufacturing device, and may be compatible well with the relevant manufacturing process, simple in process implementation, easy to implement, high in a production efficiency, low in a production cost, and high in a yield.
In the exemplary embodiment, a reasonable arrangement of the dual-output drive control circuit can be achieved by a simple arrangement, the arrangement space can be saved, and the display substrate with a narrow bezel can be achieved.
An embodiment of the present disclosure further provides a display apparatus, which includes the display substrate as described above. In some examples, the display substrate may be an OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display apparatus may be any product or component with a display function, such as an OLED display apparatus, a watch, a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, and a navigator. However, this embodiment is not limited thereto.
The drawings of the present disclosure only involve structures involved in the present disclosure, and other structures may refer to conventional designs. The embodiments of the present disclosure and features in the embodiments may be combined to each other to obtain new embodiments if there is no conflict. Those of ordinary skills in the art should understand that modifications or equivalent replacements of the technical solutions of the present disclosure may be made without departing from the spirit and scope of the technical solutions of the present disclosure, and shall all fall within the scope of the claims of the present disclosure.
The present application is a U.S. National Phase Entry of International Application No. PCT/CN2022/078427 having an international filing date of Feb. 28, 2022. The above-identified application is hereby incorporated by reference.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2022/078427 | 2/28/2022 | WO |
