Patent Application
20120133577
The present invention relates to a drive device for a liquid crystal display panel, which drives a liquid crystal display panel by column inversion driving.
When a liquid crystal display panel using TFT (Thin Film Transistor) is to be driven, a gate-on voltage VGH to switch on a TFT gate provided for every pixel at an intersection of a gate wiring and a source wiring, a gate-off voltage VGL to switch off the TFT gate, a data voltage (source voltage) VD to be applied to a TFT source and a common voltage VCOM to be applied to a common electrode, are required.
If a liquid crystal display panel is driven by a DC voltage, its useful life tends to be short. For such a reason, it is common to use an AC voltage in a drive method for driving a liquid crystal display panel. AC driving includes, for example, line inversion driving, column inversion driving and dot inversion driving (e.g. Patent Document 1).
Column inversion driving is a drive method wherein in a liquid crystal display panel having pixels arranged in a matrix form, when pixel groups in a horizontal direction (lines: rows) are to be driven, for example, sequentially from the upper side towards the lower side, in one frame, the data voltage is made to be, for example, from a left hand side source wiring (column) towards a right hand side column, positive polarity, negative polarity, positive polarity, negative polarity, . . . , and in the next frame, the polarity of the data voltage in each column is made to be opposite to the polarity in the last frame.
Hereinafter, a state where the potential of a source electrode is higher than the common voltage is regarded as a positive polarity state, and a state where the potential of a source electrode is lower than the common voltage is regarded as a negative polarity state.
Patent Document 1 discloses a method wherein in order to reduce power consumption of the drive device, the voltage applied to source wirings during the vertical blanking period is inverted, or when the vertical blanking period is started, the source wirings are once charged to the common potential. By such a construction, a rush current (inrush current) flowing in the source driver at the time of changing the polarity, can be reduced.
Further, Patent Document 1 discloses a method wherein in the vertical blanking period, charge sharing is carried out to short-circuit adjacent source wirings, then positively and negatively polarized data voltages with prescribed voltages are supplied to source wirings, and further charge sharing is carried out to bring the potential of the source wirings close to the common voltage. Here, a data voltage with a prescribed voltage to be supplied to a source wiring, is supplied to a source driver which outputs the data voltage to the source wiring, in the first horizontal effective period in the vertical blanking period.
However, if the drive device for a liquid crystal display panel disclosed in Patent Document 1 is to be used, it is necessary to preliminarily determine by calculation, etc. the voltage value for the data voltage to be output in the first horizontal effective period in the vertical blanking period. Further, the number of types of the voltage values for the data voltages which can be used, is usually limited to a number corresponding to the number of gradations and cannot be set to be an optional desired value. Further, in order to make it possible for the data voltages to be output in the first horizontal effective period in the vertical blanking period, the construction of a timing control circuit to supply a clock signal or a latch signal to a source driver or a gate driver, has to be substantially changed from a common construction of a timing control circuit. Further, power consumption is not reduced in a period wherein driving is carried out for actual display (hereinafter referred to as a display period).
Accordingly, it is an object of the present invention to further reduce power consumption by a simple construction in a drive device for driving a liquid crystal display panel by column inversion driving.
The drive device for a liquid crystal display panel according to the present invention is a drive device for a liquid crystal display panel having a plurality of gate wirings and a plurality of source wirings arranged to intersect with each other, which drive device is provided with a source driver to drive the source wirings by column inversion driving, wherein the source driver makes, as compared with the driving ability in at least an initial period (a period for at least one line) to drive a first one line in each frame, the driving ability to be low in at least a part of a period subsequent to the initial period in each frame.
The source driver is constructed, for example, to make the driving ability to be low over the entire period in the period subsequent to the initial period.
The source driver is constructed, for example, to make, in the period subsequent to the initial period, as compared with the driving ability in a preceding prescribed interval (first half interval) in each periodically occurring period (e.g. a period for each line), the driving ability to be low in an interval (second half interval) subsequent to the prescribed interval. By such a construction, it is possible to reduce consumption current while preventing deterioration of the display quality, taking into consideration the properties of the liquid crystal display panel. Further, the driving ability in the preceding prescribed interval may be made to be lower than the driving ability in the initial period. Further, the source driver may include an interval adjusting means to adjust the length of the preceding prescribed interval.
The source driver is constructed, for example, to include an output pathway setting unit which sets either one of a state where a voltage signal corresponding to a data signal is applied to a source wiring via an amplifier and a state where the voltage signal is applied to the source wiring without via the amplifier; when the driving ability is to be made low, the output pathway setting unit sets the state where the voltage signal corresponding to the data signal is applied to the source wiring without via the amplifier; and when the driving ability is to be made high, the output pathway setting unit sets the state where the voltage signal corresponding to the data signal is applied to the source wiring via the amplifier, and the amplifier increases an output current as compared with an output current in the state where the voltage signal corresponding to the data signal is applied, as it is, to the source wiring.
The source driver may be constructed to include an amplifier which is capable of changing an output current; a voltage signal corresponding to a data signal may be applied to a source wiring via the amplifier; when the driving ability is to be made high, the amplifier may be constructed to apply to the source wiring the voltage signal corresponding to the data signal in a state where the output current is increased as compared with an output current when the driving ability is to be made low.
The source driver may include a source wiring initial setting unit which, in a vertical blanking period, short-circuits adjacent source wirings, or connects each source wiring to a prescribed potential. By such a construction, it is possible to reduce power consumption, with a simpler construction, by suppressing a rush current which flows in the source driver when the polarity is changed over.
According to the present invention, in a drive device for driving a liquid crystal display panel by column inversion driving, it is possible to further reduce power consumption by a simple construction.
Now, embodiments of the present invention will be described with reference to the drawings.
A facing substrate (not shown) is provided to face the substrate having the gate wirings 13, the source wirings 14 and the pixels 12 formed thereon, and liquid crystal is sandwiched between the substrate having the pixels 12 formed, and the facing substrate. On the facing substrate, a counter electrode (common electrode) is formed, and the counter electrode is set at a common potential VCOM. Here, electrically, liquid crystal may be regarded as an element having a capacity, and in
A gate driver 30 drives gate wirings 13, for example, line-sequentially. To a pixel electrode of a pixel connected to a selected gate wiring 13 i.e. a gate wiring 13 to which a gate-on voltage VLH is applied, a data voltage (voltage corresponding to a data signal) VD is applied via a source wiring 14.
In the construction example shown in
Taking as a starting point a horizontal start pulse STH corresponding to a signal for initiation of a selected period output by a control unit (timing control circuit) 40, the shift resistor 21 forms a data taking-in signal from a clock signal CLK for data shift and outputs it. In this embodiment, the number of source wirings 14 is assumed to be m (m: a positive integer in multiples of 3). With respect to the data signals, data corresponding to one clock signal CLK in the case of RGB parallel, are three RGB. Accordingly, the number of output signals of the shift resistor 21 is m/3. For example, in response to the Ith clock (I:1 to m/3) of the clock signal CLK, the shift resistor 21 brings a first set of outputs to an on-state (data taking-in state). Here, in this embodiment, the liquid crystal display panel 10 is driven by a line sequential driving method, and the selected period corresponds to a period for driving one line.
To the first latch circuit 22, data signals DATA from the timing control circuit 40 are sequentially output. Further, to the first latch circuit 22, m/3 signal is input from the shift resistor 21. When among m signals, the Ith set (I:1 to m/3) of signals become an on-state, the first latch circuit 22 latches and outputs the first set of data (data signals DATA).
The second latch circuit 23 collectively takes in signals latched by the first latch circuit 22, for example, at the time of falling of a strobe signal STB (hereinafter referred to as a latch signal STB) output from the timing control circuit 40.
To the D-A converter 24, e.g. a voltage Vn (n: 0 to 15) is supplied from a power source circuit (not shown) included in the timing control circuit 40. As shown in
From the D-A converter 24, m signals are output which show values appropriate for the level (a high level or a low level) of a polarity inversion signal POL output from the timing control circuit 40. For example, in a case where the level of the polarity inversion signal POL is a high level, among m signals, odd-numbered signals are made to be signals with a value appropriate for positive polarity and the level of a signal input from the second latch circuit 23, and among the m signals, even-numbered signals are made to be signals with a value appropriate for negative polarity and the level of a signal input from the second latch circuit 23. Whereas, in a case where the level of the polarity conversion signal POL is a low level, among the m signals, odd-numbered signals are made to be signals with a value appropriate for negative polarity and the level of a signal input from the second latch circuit 23, and among the m signals, even-numbered signals are made to be signals with a value appropriate for positive polarity and the level of a signal input from the second latch circuit 23.
Further, in this embodiment, to simplify the description, the source driver 20 realizes 64 tones by means of a register ladder in the driver by inputting eight standard voltages in positive polarity by using voltages V8 to V15 and displays 64 tones by eight standard voltages in negative polarity by using voltages V0 to V7. The present invention may be applied to a case where a larger number of tones are to be realized. Further, the D-A converter 24 is provided with a register ladder at the input portion to realize multi-tone.
Further, in the construction shown in
The D-A converter 24 outputs signals of voltage (voltage signals) corresponding to the values shown respectively by the m signals output from the second latch circuit 23, to the buffer circuit 25.
The buffer circuit 25 applies the respective m voltage signals output from the D-A converter 24 to m source wirings 14.
Further, the source driver 20, the gate driver 30 and the timing control circuit 40 shown in
Further, as shown in
Further, in this embodiment, the timing control circuit 40 outputs a control signal Cont 2 as shown in
In
In the example shown in
Further, the first switch 263 and the second switch 264 realize an output pathway setting unit which sets either one of a state where a voltage signal corresponding to a data signal is applied to a source wiring 14 via the amplifier 261 and a state where the voltage signal is applied to the source wiring without via the amplifier 261.
The control signal Cont 2 is, for example, a 2 bit signal.
As shown in
Here, the driving ability of 130% or 80% represents a relative maximum output current based on the driving ability when the level of the control signal Cont 2 is (L, H).
Further, the driving ability by the voltage signal from the D-A converter 24 is lower than the driving ability when the level of the control signal Cont 2 is (H, L) (corresponding to output C shown in
As shown in
Here, the first output switch 266, the second output switch 268 and the third switch 267 are an example of a source wiring initial setting unit to short-circuit the adjacent source wirings 14.
Further, the internal construction of the output buffer 252 is the same as the internal construction of the output buffer 251 shown in
Now, the operation of the source driver 20 will be described with reference to the timing diagram in
As shown in
That is, each odd-numbered source wirings S(2n-1) will be connected to the adjacent even-numbered source wiring S(2n). Further, each source wiring 14 is cut off from the output buffer 251 or 252.
As a result, charge sharing is carried out by the potential of source wirings 14 which have been driven at a voltage higher than the common voltage VCOM and the potential of source wirings 14 which have been driven at a voltage lower than the common voltage VCOM are neutralized. That is, the potential of each source wiring 14 becomes close to the common voltage VCOM.
The charge sharing is carried out in the vertical blanking period. Thus, when a display period in one frame is to be initiated, the potential of each source wiring 14 is close to the common voltage VCOM, whereby a rush current at the initiation of the display period can be reduced, for example, as compared with a case where the driving state is directly changed from a state of driving with negative polarity to a state of driving with positive polarity.
Further, in this embodiment, as shown in
Referring to
Thus, the source wiring 14 is driven in the state of the driving ability of 80% during the prescribed period where the level of the control signal Cont 2 is at a prescribed level.
Upon completion of the prescribed period, the timing control circuit 40 controls the level of the control signal Cont 2 to be at a level other than the prescribed level, in this embodiment, the level other than the prescribed level is (H, H).
Referring to
The driving ability by the voltage signal from the D-A converter 24 is lower than the driving ability when the level of the control signal Cont 2 is (H, L), and accordingly, after completion of the prescribed period, the source wiring 14 is driven by a lower driving ability. As a result, consumption current of the source driver 20 becomes low.
As shown in
Further, as described above, in this embodiment, the potential of each source wiring 14 is adjusted to be close to the common voltage VCOM before initiation of the display period, by the charge sharing in the vertical blanking period, whereby the rush current at the initiation of the display period is reduced. Thus, it is possible to reduce the degree of rising of the driving ability in the prescribed period after initiation of the display period. That is, in the prescribed period after initiation of the display period, the driving ability of the output buffer 251 is increased, but is not required to be increased so much.
However, even in a case where no charge sharing is carried out in the vertical blanking period, it is effective to control the driving ability of the source driver 20 to be high in a prescribed period after initiation of the display period.
Further, in this embodiment, in a prescribed period (e.g. a period of at least one horizontal period) after initiation of the display period, the source wiring 14 is driven at 80% of the driving ability exemplified in
As one example, in a prescribed period after initiation of the display period, driving is carried out in a state of a driving ability of 130% or 100% (see
Further, in this embodiment, charge sharing is carried out in the vertical blanking period, but instead of the charge sharing, precharging may be carried out wherein a prescribed precharge voltage (e.g. the common voltage VCOM) is applied to the source wiring 14. In a case where such precharging is to be carried out, in the construction shown in
In such a case, the first output switch 266, the second output switch 268 and the fourth switch, correspond to a source wiring initial setting unit to connect each source wiring 14 to a prescribed potential.
As described in the foregoing, in this embodiment, the source driver 20 makes, as compared with the driving ability in at least a period to drive the first one line in each frame i.e. in a period of at least a period to drive one line, the driving ability to be low in a period after such a period. In other words, the driving ability in at least a period to drive the first one line in each frame, is made to be higher than the driving ability in a period after such a period, whereby with a simple construction, it is possible to reduce power consumption while preventing deterioration of the display quality.
In the above described embodiment, the drive device is designed to carry out a control in such a manner that in a prescribed period (specifically an initial period being a period of at least a period to drive one line) after initiation of the display period, a source wiring 14 is driven by e.g. a driving ability of 80% as shown in
In the second embodiment, in the period subsequent to the prescribed period, while in a first half interval in each periodically occurring period, a source wiring 14 is driven by a high driving ability, in a second half interval, the source wiring 14 is driven by a low driving ability as compared with the first half interval.
Here, in order to make the description simple, in the following description, each periodically occurring period is regarded as a period to drive each line (a period for each line).
The operation of the source driver 20 in the second embodiment will be described with reference to the timing diagrams in
Further, in
The constructions of the source driver 20 and the gate driver 30 are the same as their constructions in the first embodiment shown in
Hereinafter, description will be made by paying attention to two output buffers 251 and 252 (see
As shown in
Further, also in this embodiment, as shown in
Thus, in the same manner as in the case of the first embodiment, the source wiring 14 is driven in a state of the driving ability of 80% during a prescribed period wherein the level of the control signal Cont 2 is a prescribed level.
In the first embodiment, the timing control circuit 40 controls the level of the control signal Cont 2 to be a level other than the prescribed level upon completion of the prescribed period. Specifically, the level of the control signal Cont 2 is adjusted to be (H, H). Thus, the source wiring 14 is driven by a voltage signal from the D-A converter 24 (see
That is, in the first embodiment, the timing control circuit 40 is controlled so that the source wiring 14 is driven by a low driving ability over the entire period in the period for the second line et seq.
However, in this embodiment, in each period for the second line or subsequent line, in the first half interval, the source wiring 14 is driven by a high driving ability, but in a second half interval, the source wiring 14 is driven by a low driving ability as compared with the first half interval, and accordingly, the manner for the output of the control signal Cont 2 is made different from the case of the first embodiment.
That is, as shown in
In this embodiment, as compared with the first embodiment, power consumption is reduced in consideration of the properties of the liquid crystal display panel 10. That is, in a case where if the first embodiment is applied, the electric current tends to be inadequate, thus leading to a phenomenon such as deterioration of the display quality, due to such a cause that the size or the number of pixels of the liquid crystal display panel 10 is large, by applying this embodiment, an increase of the power consumption can be controlled by not driving by a high driving ability over the entire period of one frame, while preventing deterioration of the display quality by prolonging the period of driving at a high driving ability, as compared with the first embodiment.
Further, in the periods of the second and subsequent lines, after the timing control circuit 40 has adjusted the output level of the control signal Cont 2, by changing the period to release the prescribed level output (corresponding to the timing of completion of the first half interval), it is possible to change the length of the period where the driving ability is made high (i.e. the first half interval). Thus, depending upon e.g. the size or the number of pixels of the liquid crystal display panel 10, it is possible to adjust the length of the first half interval. That is, it becomes possible to realize a fine control to reduce consumption current while preventing deterioration of the display quality. For example, the first half interval is prolonged, in a case where if the period where the driving ability is made high, is shortened too much in order to reduce consumption current, the display quality becomes lower than the desired quality.
As a construction to realize the control to adjust the length of the first half interval, there is, for example, a construction wherein a control input terminal is provided in the timing control circuit 40. In such a case, the timing control circuit 40, after adjusting the output level of the control signal Cont 2 to a prescribed level, counts the number of pulses of the block signal and releases the prescribed level output when the counted value becomes a preliminarily determined value corresponding to the type of signal (specifically the type of the signal level) input in the control input terminal. When such a construction is taken, by the timing control circuit 40, the interval adjusting means to adjust the length of the first half interval, is realized.
Further, in this embodiment, the control signal Cont 2 is utilized to realize the control to drive a source wiring 14 by a high driving ability in the first half interval and to drive the source wiring 14 by a low driving ability in the second half interval. However, a practical method is not limited to such a method of using the control signal Cont 2. For example, as shown in
When the control signal Cont 3 is used, the timing control circuit 40 adjusts the level of the control signal Cont 3 to a prescribed level in a prescribed period (the first half interval). In this embodiment, the prescribed level is (H, L) (see
Further, in the periods of the second and subsequent lines, without using the control signal Cont 2 or the control signal Cont 3, the buffer circuit 25 may input e.g. a clock signal CLK for data shift and counts the number of times of rising or falling of the clock signal CLK, whereby the timing for completion of the first half interval may be independently set. When such a construction is adopted, it is possible that by the buffer circuit 25, an interval-adjusting means to adjust the length of the first half interval, is realized.
Further, in this embodiment, in the first half interval, the source wiring 14 is driven by a driving ability of 80% as exemplified in
As an example, the combination may be such that in the first half interval, driving is carried out in a state of a driving ability of 130% or 100% (see
Further, in this embodiment, the driving ability in a prescribed period (initial period) after initiation of the display period and the driving ability in the first half interval in a period subsequent to the prescribed period, are made to be the same, but the driving ability in the first half interval may be made lower than the driving ability in the initial period. Further, in a case where the first half interval or the second half interval is designed to be set by a control signal Cont 3 separate from the control signal Cont 2, it is easier to carry out such a control that the driving ability in the first half interval is made different from the driving ability in the initial period.
Further, in the foregoing description, the liquid crystal display panel 10 may be either a monochromatic panel or a color panel.
The present invention is applicable to a liquid crystal display device to be mounted on portable devices, in-vehicle devices, image display devices, etc.
The entire disclosures of Japanese Patent Application No. 2010-264893 filed on Nov. 29, 2010 and Japanese Patent Application No. 2010-117118 filed on May 21, 2010 including specifications, claims, drawings and summaries are incorporated herein by reference in their entireties.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2010-264893 | Nov 2010 | JP | national |
