The present invention relates to a drive device of a liquid ejection head and to a liquid ejection apparatus, and more particularly to a drive device of a liquid ejection head and to a liquid ejection apparatus that drives a liquid ejection head that ejects recording liquid droplets from nozzles disposed with drive elements according to the application of drive signal voltages to those drive elements.
The piezoelectric format is known as one type of inkjet recording format that records characters and images such as photographs on a recording medium by causing ink droplets ejected from the nozzles of a recording head to adhere to the recording medium. In the piezoelectric format, the deformation of piezoelectric elements that results from the application of drive signal voltages to those piezoelectric elements is transmitted via diaphragms to pressure chambers filled with ink, whereby pressure fluctuations inside the pressure chambers cause the ink droplets to be ejected from the nozzles.
The drive device that drives a piezoelectric recording head is configured by an integrated circuit and the like, which includes a high voltage unit that is driven at a high voltage (e.g., 40 V) in order to drive the piezoelectric elements and a logic unit that includes logic circuits or the like such as shift registers. However, sometimes the logic unit malfunctions due to the effect of noise generated by the logic power supply (e.g., 3.3 V) for driving the logic unit, or else the high voltage unit malfunctions due the effect of noise generated by the high voltage power supply unit for driving the high voltage unit (latch up).
When the high voltage unit latches up, the reference potential in the integrated circuit rises because a huge overcurrent flows to the high voltage unit. As a result, this also causes the logic unit to malfunction.
In order to detect such malfunction of the recording head, a technique is available that detects malfunctions by looping back the output of the final stage of the shift registers of the drive device of the recording head and checking this against a signal inputted to the shift registers to determine whether or not both match.
Further, a technique is available that detects malfunctions by adding a parity to the printing data to be recorded by the recording head and parity-checking the output of the shift registers.
Further, a technique is available that detects malfunctions by detecting when all of the data on a data bus are “1” or “0”, since this is often what happens when a an out-of-control situation arises resulting from a malfunction.
In recent years, there has been an increasing trend to lengthen the recording head of inkjet printers, and in accompaniment therewith there has also been the trend to increase the number of integrated circuits in the drive device disposed in the recording head.
Yet when the technology described above in the paragraph [0005] is applied to the drive device of a recording head lengthened in this manner, there is the problem that the number of wires for looping back the output of the final stage of shift registers increases as the number of integrated circuits of the drive devices disposed in the recording heads becomes greater, which leads to an increase in cost.
Further, in the technology described above in the paragraph [0006], because a parity is added to the printing data and the output of the shift registers is parity-checked, there have been the problems that compatibility with the control device that outputs printing data to which a parity has not been added becomes poor, and the probability of detecting malfunction in the case of a lengthened recording head becomes low.
Further, in the technology described above in the paragraph [0007], there is the problem that compatibility with malfunction detection becomes poor because all of the data on the data bus do not invariably become “1” or “0” during an out-or-control situation resulting from a malfunction.
Further, when a circuit for detecting malfunction is disposed outside the recording head, that is, in the printer body, the number of signal lines connecting the recording heads and the printer body increase and the processing burden of the control device of the printer body becomes large, which leads to an increase in the cost of the device. Consequently, it is preferable for the detection of malfunction of the drive device of the recording head to be conducted by the drive device of the recording head itself.
The present invention has been made in view of the above circumstances and provides a liquid ejection head drive device and a liquid ejection apparatus that can reliably detect, with an inexpensive configuration and by the drive device itself, malfunction of a drive device disposed in a recording head.
An aspect of the invention provides a liquid ejection head drive device that drives a liquid ejection head that ejects recording liquid droplets from plural nozzles disposed in correspondence to plural drive elements as a result of drive signal voltages being applied to the plural drive elements by plural drive signal voltage generating units that are disposed in correspondence to the plural drive elements and generate drive signal voltages on the basis of printing data, the liquid ejection head drive device comprising: a transfer unit that transfers printing data of a predetermined transfer data number and outputs the corresponding printing data to the plural drive signal voltage generating units; and an output unit that acquires printing data from plural predetermined positions that are on a transfer path of the transfer unit and are apart a predetermined data number and outputs the result of a comparison where the acquired plural printing data are compared.
Other aspects, features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings.
Preferred embodiments of the present invention will be described in detail based on the following figures, in which:
An example of an embodiment of the present invention will be described in detail below with reference to the drawings.
As shown in
The head drive unit 60 includes: drive signal voltage generating units 34 that are numerously disposed in correspondence to the individual piezoelectric elements 20 of the liquid ejection head 10; basic waveform data generation/input circuit for use with large droplets (large droplet-use basic waveform data generation/input circuit) 62A, a medium droplet-use basic waveform data generation/input circuit 62B, a small droplet-use basic waveform data generation/input circuit 62C, and waveform data generation/input circuit for use in non-jetting (a no-jet-use basic waveform data generation/input circuit) 62D, which generate plural types of basic waveform data in accordance with liquid droplet amounts; shift register groups 28A, 28B, 28C and 28D that transfer and supply, to the individual drive signal voltage generation units 34, the plural types of basic waveform data generated by the corresponding basic waveform data generation/input circuits; a selection data input circuit 66 that determines, on the basis of inputted image data, from which of the individual nozzles 18 ink droplets are to be ejected and the liquid droplet amounts (large droplets, medium droplets, small droplets) of the ink droplets to be ejected, and generates and outputs selection data instructing which of the basic waveform data of the large droplet-use, medium droplet-use, small droplet-use, and no-jet-use basic waveform data are to be selected; and a data transfer input unit 68 that transfers the inputted selection data and retains the corresponding selection data in the individual drive signal voltage generating units 34.
In the present embodiment, the basic waveform data are data representing basic waveforms whose voltage level changes in two stages (waveforms serving as the base of the drive signal voltages; see
Further, two types of basic waveform data representing mutually different basic waveforms are stored in the internal memory of each of the basic waveform data generation/input circuits 62 (for the sake of convenience, one of these two types of basic waveform data will be called basic waveform data A, and the other of these two types of basic waveform data will be called basic waveform data B below). As will be described later, the two types of basic waveform data are inputted to the individual drive signal voltage generating units 34, where they are boosted to mutually different voltage levels, and the basic waveform voltage of the two types of basic waveform voltages that is to be selectively outputted as the drive signal voltage is appropriately switched, whereby a drive signal voltage whose voltage level changes in three stages or more is generated. The two types of basic waveform data represent mutually different basic waveforms that are determined such that a drive signal voltage with a predetermined waveform is obtained (see
The basic waveform data A and B are mutually different in each of the basic waveform data generation/input circuits 62. In the internal memory of the large droplet-use basic waveform data generation/input circuit 62A are stored large droplet-use basic waveform data A and B (see
Further, selectors 64A and 64B are disposed in each of the individual drive signal voltage generating units 34 corresponding to the individual piezoelectric elements 20. Input ends of booster circuits 36A are connected to output ends of the selectors 64A, and input ends of booster circuits 36B are connected to output ends of the selectors 64B.
The basic waveform data A and B outputted from the basic waveform data generation/input circuits 62 are inputted to the shift register groups 28A to 28D. Each of the shift register groups 28A to 28D is disposed with a shift register row A, which comprises numerous shift registers 30 that are serially connected and disposed in correspondence to the individual drive signal voltage generating units 34, and a shift register row B, which comprises numerous shift registers 32 that are serially connected and disposed in correspondence to the individual drive signal voltage generating units 34. The basic waveform data A inputted 1 bit at a time to the shift register groups 28A to 28D are inputted to the shift register rows A and sequentially transferred through the shift register rows A at a period synchronized with a predetermined clock signal. Similarly, the basic waveform data B inputted 1 bit at a time to the shift register groups 28 are inputted to the shift register rows B and sequentially transferred through the shift register rows B at a period synchronized with a predetermined clock signal.
Further, output ends of the individual shift registers 30 of the shift register rows A are connected to input ends of the selectors 64A of the corresponding drive signal voltage generating units 34, and output ends of the individual shift registers 32 of the shift register rows B are connected to input ends of the selectors 64B of the corresponding drive signal voltage generating units 34. Consequently, the basic waveform data A and B are inputted to the individual drive signal voltage generating units 34 at a timing shifted one period at a time of the predetermined clock signal.
The booster circuits 36A generate basic waveform voltages A by boosting the inputted basic waveform data A to a predetermined voltage level (voltage level 1). The booster circuits 36B generate basic waveform voltages B by boosting the inputted basic waveform data B to a predetermined voltage level (voltage level 2). Output ends of the booster circuits 36A and 36B are connected to input ends of driver circuits 38, and the basic waveform voltages A and B generated by the booster circuits 36A and 36B are inputted to the driver circuits 38.
The driver circuits 38 generate, on the basis of the inputted basic waveform voltages A and B, drive signal voltages whose voltage level changes in three stages and apply the drive signal voltages to the piezoelectric elements 20 (see
The head drive unit 60 is also disposed with the selection data input circuit 66. Image data representing an image to be formed on a recording medium as a result of ink droplets being ejected from the nozzles 18 of the liquid droplet ejection head 10 are inputted to the selection data input circuit 66. The selection data input circuit 66 determines, on the basis of the inputted image data, from which of the individual nozzles 18 ink droplets are to be ejected and the liquid droplet amounts (large droplets, medium droplets, small droplets) of the ink droplets to be ejected. On the basis of the result of that determination, the selection data input circuit 66 generates, for each of the individual drive signal voltage generating units 34, selection data instructing which of the basic waveform data of the large droplet-use, medium droplet-use, small droplet-use, and no-jet-use basic waveform data inputted to the selectors 64A and 64B are to be selected (are to be used to drive the piezoelectric elements 20), and sequentially outputs the generated selection data using the selection data corresponding to a single drive signal voltage generating unit 34 as a unit.
The data transfer input unit 68 is connected to an output end of the selection data input circuit 66, and is configured by a shift register row and numerous latches 72. The shift register row comprises numerous shift registers 70 that are serially connected and disposed in correspondence to the individual drive signal voltage generating units 34. The shift register row transfers, in accordance with a transfer clock, the selection data (printing data) sequentially outputted from the selection data input circuit 66. The latches 72 are connected to output ends of the individual shift registers 70 in the shift register row, retain the selection data outputted from the shift registers 70, and input the selection data to control signal input ends of the selectors 64A and 64B.
The head drive unit 60 is also provided with calculation units 80A and 80B and a comparison unit 82. An input end of the calculation unit 80A is connected to an input end of the data transfer input unit 68, that is, to the output end of the selection data input circuit 66. Consequently, the printing data outputted from the selection data input circuit 66 are sequentially inputted to the calculation unit 80A.
As shown in
The T-FF 86 is configured such that the aforementioned inversion operation is conducted when a printing clock representing whether or not to allow execution of a printing cycle is at a high level and such that the output is reset to “0” when the printing clock becomes a low level. As shown in
Further, when the printing clock becomes a low level, the 1-bit register 84 outputs the stored 1-bit data to the comparison unit 82 and imports and retains the output of the T-FF 86.
An output end of the data transfer input unit 68 is connected to an input end of the calculation unit 80B. Consequently, the printing data outputted from the data transfer input unit 68 are sequentially inputted to the calculation unit 80B. It will be noted that the printing data are inputted to the calculation unit 80B delayed a number of clocks corresponding to the number of registers (bit storage number) in the shift register row of the data transfer input unit 68 after the printing data have been inputted to the calculation unit 80A.
As shown in
Next, the operation of the present embodiment will be described. First, the drive control of the liquid ejection head 10 by the head drive unit 60 will be described.
In the head drive unit 60 according to the present embodiment, the selection data are generated and sequentially outputted on the basis of image data by the selection data input circuit 66 prior to the ejection of the ink droplets from the liquid ejection head 10. The selection data sequentially outputted from the selection data input circuit 66 are transferred by the shift register row of the data transfer input unit 68 and retained in the latches 72, whereby the selection data are inputted to the selectors 64A and 64B of the corresponding drive signal voltage generating units 34.
Further, the basic waveform data generation/input circuits 62A to 62D repeatedly read, 1 bit at a time, and sequentially output the basic waveform data A and B (any of the large droplet-use, medium droplet-use, small droplet-use and no-jet-use basic waveform data) stored in the internal memories at a timing synchronized with a predetermined clock signal. The large droplet-use, medium droplet-use, small droplet-use and nojet-use basic waveform data A outputted from the basic waveform data generation/input circuits 62A to 62D are transferred by the shift register rows A of the shift register groups 28A to 28D and inputted at timings shifted by one period each according to the time of the predetermined clock signal to the selectors 64A of the individual drive signal voltage generating units 34. Further, the large droplet-use, medium droplet-use, small droplet-use and no-jet-use basic waveform data B outputted from the basic waveform data generation/input circuits 62A to 62D are transferred by the shift register rows B of the shift register groups 28A to 28D and inputted at timings shifted by one period each according to the time of the predetermined clock signal to the selectors 64B of the individual drive signal voltage generating units 34.
Of the large droplet-use, medium droplet-use, small droplet-use and no-jet-use basic waveform data inputted to the selectors 64A and 64B via the shift register groups 28A to 28D from the basic waveform data generation/input circuits 62A to 62D, the selectors 64A and 64B output, to the booster circuits 36A and 36B, the basic waveform data whose selection has been instructed by the selection data inputted to the control signal input ends via the data transfer input unit 68 from the selection data input circuit 66.
Thus, as shown in
The individual nozzles 18 of the liquid ejection head 10 the ink from which droplets are to be ejected, and the liquid droplet amounts of the ink droplets to be ejected, are dependent on the waveform of the drive signal voltage applied to the corresponding piezoelectric element 20, and the sizes of the dots to be formed on the recording medium by the ink droplets ejected from the individual nozzles 18 are dependent on the liquid droplet amounts of the ink droplets ejected from the individual nozzles 18. For this reason, the head drive unit 60 according to the present embodiment can switch the liquid droplet amounts of the ink droplets ejected from the individual nozzles 18 to achieve dot diameter modulation where the sizes of the dots to be formed on the recording medium by the ink droplets ejected from the individual nozzles 18 are switched for each individual nozzle 18 (individual piezoelectric element 20) and in accordance with the image to be formed on the recording medium, and can improve, with this dot diameter modulation, the image quality of the image that is formed on the recording medium.
Next, the malfunction detection control by the head drive unit 60 will be described.
As shown in
The printing data sequentially outputted from the selection data input circuit 66 are transferred 1 bit at a time in accordance with the transfer clock shown in
Then, when the input of the printing data of the number of registers in the shift register row of the data transfer input unit 68 ends, the printing clock becomes a low level and the printing cycle ends. At this time, the 1-bit data that had been stored in the 1-bit register 84 are outputted to the comparison unit 82, the output of the T-FF 86 of the calculation unit 80A is newly stored in the 1-bit register 84, and the T-FF 86 is reset.
When, for example, the number of registers in the shift register row of the data transfer input unit 68 is equivalent to 256 bits, printing data of 256 bits are outputted from the selection data input circuit 66 in one printing cycle. Thus, the T-FF 86 of the calculation unit 80A calculates parity data with respect to the printing data from the 1st bit to the 256th bit, and as shown in
Similarly, when printing cycle 2 is started and printing data beginning with the 257th bit are outputted from the selection data input circuit 66, the printing data beginning with the 257th bit are sequentially transferred by the data transfer input unit 68 and inputted to the T-FF 86 of the calculation unit 80A. Further, the printing data beginning with the 1st bit are inputted to the T-FF 86 of the calculation unit 80B. Then, when the printing data from the 257th bit to the 512th bit are sequentially transferred by the data selection transfer unit 68, the printing clock becomes a low level and printing cycle 2 ends. Thus, in the T-FF 86 of the calculation unit 80A, parity data with respect to the printing data from the 257th bit to the 512th bit are calculated, and as shown in
When printing cycle 2 ends, the comparison unit 82 compares the parity data with respect to the printing data from the 1st bit to the 256th bit outputted from the 1-bit register 84 of the calculation unit 80A and the parity data with respect to the printing data from the 1st bit to the 256th bit outputted from the T-FF 86 of the calculation unit 80B. When both match, the comparison unit 82 determines that the head drive unit 60 is not malfunctioning and continues the printing operation as is. When both do not match, the comparison unit 82 determines that the head drive unit 60 has malfunctioned, due to the aforementioned effect of power supply noise or the like, and executes a predetermined processing.
This predetermined processing can include, for example, at least one of: processing that outputs a clear instruction signal instructing the execution of processing that clears all of the registers in the head drive unit 60 to a device that processes this; processing that outputs an error signal representing the fact that an error has occurred to an unillustrated control device in the body of the inkjet printer; and processing that outputs, to an unillustrated power supply device that supplies power to the head drive unit 60, a power stop signal instructing the stop of the supply of power. From printing cycle 3 below onward is the same.
It will be noted that the invention may also be configured such that, rather than immediately outputting an error signal or the like when the parity data outputted from the calculation unit 80A and the parity data outputted from the calculation unit 80B do not match (when an error has occurred), an error signal or the like is outputted when instances where both sets of parity data do not match continue to occur a predetermined number of times, and such that in other cases an error signal or the like is not outputted and operation is continued as is.
The predetermined number of times is set to a value determined where it is preferable to continue the printing operation when the number of times an error occurs is less than this number of times, and the error is an accidental error resulting from spike noise or the like. Specifically, it is preferable to set the predetermined number of times of two times.
This is due to the following reason. That is, in the case of an inkjet printer, it is inherently easy for noise to arise in the integrated circuit because: a large current flows inside the integrated circuit disposed with the drive device that drives the inkjet printer due to the generation of the energy that jets the liquid droplets; and the distance between the power supply internally disposed in the inkjet printer body and the integrated circuit disposed in the recording head is large. Consequently, if an error is detected only one time, there is the potential for this error to be the result of accidental spike noise. In this case, sometimes it is better to not regard this as a malfunction and to continue the printing operation. For example, even if a few number of pixels are in error, it is preferable to not stop the printing operation as long as there is no conspicuous deterioration in the output image. Conversely, if an error is continuously detected two or more times, the potential for the apparatus itself to be damaged (e.g., damage to the integrated circuit resulting from latch up) and to lead to remarkable deterioration in the output image is high, so that it is preferable to stop the printing operation. That is, it is preferable to avoid stopping the apparatus more than necessary in response to the condition.
By controlling in this manner, the apparatus can be stopped only when absolutely necessary, and printing efficiency can be prevented from dropping.
Table 1 shows output values of the T-FF 86 of the calculation unit 80A and output values of the 1-bit register 84 of the calculation unit 80A at points in time t1, t2 and t3 when there is no malfunction when an odd number of “1”s (high level) are included in printing data of 256 bits outputted in printing cycle 1, an even number of “1”s are included in printing data of 256 bits outputted in printing cycle 2, and an odd number of “1”s are included in printing data of 256 bits outputted in printing cycle 3.
As is apparent from Table 1, when there is no malfunction, the output value of the T-FF 86 of the calculation unit 80A at a certain point in time becomes the output value of the 1-bit register 84 of the calculation unit 80A and the output value of the T-FF 86 of the calculation unit 80B after one more printing cycle. Consequently, the comparison unit 82 compares the output value of the 1-bit register 84 of the calculation unit 80A and the output value of the T-FF 86 of the calculation unit 80B from t2 on when two printing cycles have ended.
Incidentally, as mentioned above, the liquid ejection head 10 is driven by plural head drive units 60, and each head drive unit 60 executes the above-described malfunction detection control. For this reason, a number of wires (for outputting the error signals and power stop signals) corresponding to the number of head drive units 60 becomes necessary, but as shown in
In this manner, the calculation units 80A and 80B are connected to both ends of the data transfer input unit 68 that sequentially transfers the printing data, and parity data of the printing data are calculated and compared to detect whether or not the printing data have been normally transferred, to thereby detect malfunction of the head drive unit 60. Thus, malfunction of the head drive unit 60 can be reliably detected by the drive device itself. For this reason, the processing burden of the control device in the body of the inkjet printer can be alleviated. Further, by disposing the OR circuit 88 as shown in
A case was described above where the data transfer input unit 68 sequentially transferred the printing data from the left side to the right side in
Further, a case was described above where the calculation unit 80A was configured by the 1-bit register 84 and the T-FF 84 and where the calculation unit 80B was configured by the T-FF 86. However, the calculation unit 80A may be configured by an n-bit counter that counts the number of times of launch edges of printing data of 2n bits (where n is a positive integer) outputted from the selection data input circuit 66 in one printing cycle (i.e., counts the number of “1”s) and by an n-bit counter that stores the n-bit data, and the calculation unit 80B may be configured by an n-bit register.
For example, when printing data of 256 bits are outputted from the selection data input circuit 66 in one printing cycle as described above, the calculation unit 80A may be configured by an 8-bit register 90 that stores 8-bit data and by an 8-bit counter 92, as shown in
Table 2 shows, in decimal numerals, output values of the 8-bit counter 92 of the calculation unit 80A, output values of the 8-bit register 90 of the calculation unit 80A, and output values of the 8-bit counter 92 of the calculation unit 80B at points in time t1, t2 and t3 when there is no malfunction when 256 “1”s are included in printing data of 256 bits outputted in printing cycle 1, ten “1”s are included in printing data of 256 bits outputted in printing cycle 2, and not even one “1” is included in printing data of 256 bits outputted in printing cycle 3.
Because the calculation units are configured by n-bit counters and/or n-bit registers in this manner, not just the fact that a malfunction is occurring but also the number of bits that do not match can be ascertained, and the status of a malfunction can be ascertained in greater detail.
Further, a case was described above where the calculation units 80A and 80B were disposed at both ends of the data transfer input unit 68 as shown in
The calculation unit 80C is connected such that when the number of registers in the shift register row of the data transfer input unit 68 is 256 bits, for example, the output of the register in the center of the shift register row of the data transfer input unit 68 (i.e., the 128th register counted from the register at the left end of the data transfer input unit 68 in
Because the shift register row is divided in this manner and it is determined whether or not the printing data have been normally transferred per divided section, malfunction of the head drive unit 60 can be rapidly detected. It will be noted that, although the shift register row is divided into sections in the case of
While the present invention has been illustrated and described with respect to some specific embodiments thereof, it is to be understood that the present invention is by no means limited thereto and encompasses all changes and modifications which will become possible within the scope and spirits of the present invention.
Number | Date | Country | Kind |
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2005-304813 | Oct 2005 | JP | national |
This application claims priority under 35 USC 199 from Japanese Patent Application No. 2005-304,813, the disclosure of which is incorporated by reference herein.