Patent Application
20190379157
Embodiments of the present disclosure relate to a drive loading jig for inserting a drive into, and removing a drive from, a host device.
The computer environment paradigm has shifted to ubiquitous computing systems that can be used anytime and anywhere. As a result, the use of portable electronic devices, such as mobile phones, digital cameras, and notebook computers has rapidly increased. These portable electronic devices generally use a memory system having memory device(s), that is, data storage device(s). The data storage device is used as a main memory device or an auxiliary memory device of the portable electronic devices.
Data storage devices used as memory devices provide excellent stability, durability, high information access speed, and low power consumption, since they have no moving parts. Examples of data storage devices having such advantages include universal serial bus (USB) memory devices, memory cards having various interfaces, and solid state drives (SSD).
The SSD may include flash memory components and a controller, which includes the electronics that bridge the flash memory components to the SSD input/output (I/O) interfaces. The SSD controller may include an embedded processor that executes functional components such as firmware. The SSD functional components are typically device specific, and in most cases, can be updated.
One type of SSD, known as an M.2 SSD, where M.2 is a form factor, is a relatively flat, rectangular shaped device. An M.2 SSD is adapted to be inserted into an M.2 slot in a computer, server or other compatible host. An M.2 drive does not include a protective case. Much like dynamic random access memory (DRAM) dual in-line memory modules (DIMMs), components mounted on an M.2 SSD are fully exposed, and as a result, can be easily knocked loose or damaged by external forces introduced during handling and installation. Moreover, the printed circuit board (PCB) of the M.2 drive can be damaged as a result of bending when the drive is inserted into, or removed from, the host without proper handling.
An M.2 drive needs to endure multiple insertion and removal cycles during various testing stages, i.e., manufacturing and integration testing. Additional handling is needed during final deployment. Ten insertion and removal cycles is not uncommon.
With this amount of handling, not only is damage to the drive a very real possibility, damage to event critical components may not even be detected until after occurrence of such critical event. The severity of the damage may extend to compromising important data stored in the drive.
Thus, a safer, more reliable way of loading drives, such as M.2 drives, into its host is needed. In this context embodiments of the present invention arise.
An aspect of the present invention includes drive loading jigs. One such drive loading jig comprises a first wall having a first slot and a first stopper formed therein; a second side wall having a second slot and a second stopper formed therein; and a rear wall joining the first and second side walls. The first and second side walls define an opening at an opposite end of the drive loading jig with respect to the rear wall. Each of the first and second slots includes multiple restraining walls configured to restrain a drive, when positioned in the drive loading jig, from bending with respect to a plane parallel to a major surface of the drive and from moving in a direction substantially perpendicular to the major surface. The first and second stoppers are configured to define a maximum insertion depth of the drive.
Another aspect of the present invention includes a drive carrier assembly. One such assembly comprises a drive loading jig and an adapter card. The drive loading jig comprises a first wall having a first slot and a first stopper formed therein, a second side wall having a second slot and a second stopper formed therein, and a rear wall joining the first and second side walls. The adapter card comprises a major surface adapted to support the drive loading jig when loaded with a drive, and a connector disposed on the major surface and configured to connect with a connector interface on the drive.
Further aspects of the present invention include methods of using a drive loading jig to insert a drive into a host. One such method comprises aligning a key-way on the drive with a key-way on the drive loading jig; aligning an insertion end of the drive with an opening of the drive loading jig to orient longitudinal edges of the drive with slots formed along a length of a drive loading jig; inserting the drive into the drive loading jig to an insertion depth defined by stoppers in the drive loading jig, such that the longitudinal edges of the drive are secured in their respective slots, and such that a connector interface of the drive is exposed at the opening of the drive loading jig; positioning the drive loading jig with the drive inserted therein such that the length of the drive loading jig with respect to a mating surface of a connector on a host is at a specific angle within a set insertion angle range; and inserting the connector interface of the drive, while in the drive loading jig, into the connector on the host, maintaining the drive loading jig at the specific angle.
Additional aspects of the present invention will become apparent from the following description.
Various embodiments are described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and thus should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure is thorough and complete and fully conveys the scope of the present invention to those skilled in the art. Moreover, reference herein to “an embodiment,” “another embodiment,” or the like is not necessarily to only one embodiment, and different references to any such phrase are not necessarily to the same embodiment(s). Throughout the disclosure, like reference numerals refer to like parts in the figures and embodiments of the present invention.
The invention can be implemented in numerous ways, including as a device, a process and a system. In this specification, operations or processing steps may be referred to as techniques. In general, the order of the steps of disclosed processes may be altered within the scope of the invention. Unless stated otherwise, a component such as a processor or a memory described as being suitable for performing a task may be implemented as a general component that is temporarily configured to perform the task at a given time or a specific component that is manufactured to perform the task. As used herein, the term ‘processor’ or the like refers to one or more devices, circuits, and/or processing cores suitable for processing data, such as computer program instructions.
A detailed description of embodiments of the invention is provided below along with accompanying figures that illustrate aspects of the invention. The invention is described in connection with such embodiments, but the invention is not limited to any embodiment. The scope of the invention is limited only by the claims. The invention encompasses numerous alternatives, modifications and equivalents within the scope of the claims. Numerous specific details are set forth in the following description in order to provide a thorough understanding of the invention. These details are provided for the purpose of example; the invention may be practiced according to the claims without some or all of these specific details. For clarity, technical material that is known in technical fields related to the invention has not been described in detail so that the invention is not unnecessarily obscured.
Referring to
The memory controller 100 may control overall operations of the semiconductor memory device 200.
The semiconductor memory device 200 may perform one or more erase, program, and read operations under the control of the memory controller 100. The semiconductor memory device 200 may receive a command CMD, an address ADDR and data DATA through input/output (I/O) lines. The semiconductor memory device 200 may receive power PWR through a power line and a control signal CTRL through a control line. The control signal CTRL may include a command latch enable (CLE) signal, an address latch enable (ALE) signal, a chip enable (CE) signal, a write enable (WE) signal, a read enable (RE) signal, and the like.
The memory controller 100 and the semiconductor memory device 200 may be integrated in a single semiconductor device such as a solid state drive (SSD). The SSD may include a storage device for storing data therein. When the semiconductor memory system 10 is used in an SSD, operation speed of a host (not shown) coupled to the memory system 10 may remarkably improve.
The memory controller 100 and the semiconductor memory device 200 may be integrated in a single semiconductor device such as a memory card. For example, the memory controller 100 and the semiconductor memory device 200 may be so integrated to configure a PC card of personal computer memory card international association (PCMCIA), a compact flash (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC), a reduced-size multimedia card (RS-MMC), a micro-size version of MMC (MMCmicro), a secure digital (SD) card, a mini secure digital (miniSD) card, a micro secure digital (microSD) card, a secure digital high capacity (SDHC) card, and/or a universal flash storage (UFS).
In another embodiment, the memory system 10 may be provided as one of various components in an electronic device, such as a computer, an ultra-mobile PC (UMPC), a workstation, a net-book computer, a personal digital assistant (PDA), a portable computer, a web tablet PC, a wireless phone, a mobile phone, a smart phone, an e-book reader, a portable multimedia player (PMP), a portable game device, a navigation device, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a 3-dimensional television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device of a data center, a device capable of receiving and transmitting information in a wireless environment, a radio-frequency identification (RFID) device, as well as one of various electronic devices of a home network, one of various electronic devices of a computer network, one of electronic devices of a telematics network, or one of various components of a computing system.
Referring to
The host device may be implemented with any one of various kinds of electronic devices. In some embodiments, the host device may include an electronic device, such as a desktop computer, a workstation, a three-dimensional (3D) television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, and/or a digital video recorder and a digital video player. In some embodiments, the host device may include a portable electronic device, such as a mobile phone, a smart phone, an e-book, an MP3 player, a portable multimedia player (PMP), and/or a portable game player.
The memory device 200 may store data to be accessed by the host device.
The memory device 200 may be implemented with a volatile memory device, such as a dynamic random access memory (DRAM) and/or a static random access memory (SRAM) or a non-volatile memory device, such as a read only memory (ROM), a mask ROM (MROM), a programmable ROM (PROM), an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a ferroelectric random access memory (FRAM), a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), and/or a resistive RAM (RRAM).
The controller 100 may control storage of data in the memory device 200. For example, the controller 100 may control the memory device 200 in response to a request from the host device. The controller 100 may provide data read from the memory device 200 to the host device, and may store data provided from the host device into the memory device 200.
The controller 100 may include a storage 110, a control component 120, which may be implemented as a processor, e.g., a central processing unit (CPU), an error correction code (ECC) component 130, a host interface (I/F) 140 and a memory interface (I/F) 150, which are coupled through a bus 160.
The storage 110 may serve as a working memory of the memory system 10 and the controller 100, and store data for driving the memory system 10 and the controller 100. When the controller 100 controls operations of the memory device 200, the storage 110 may store data used by the controller 100 and the memory device 200 for such operations as read, write, program and erase operations.
The storage 110 may be implemented with a volatile memory such as a static random access memory (SRAM) or a dynamic random access memory (DRAM). As described above, the storage 110 may store data used by the host device in the memory device 200 for the read and write operations. To store the data, the storage 110 may include a program memory, a data memory, a write buffer, a read buffer, a map buffer, and the like.
The control component 120 may control general operations of the memory system 10, and a write operation or a read operation for the memory device 200, in response to a write request or a read request from the host device. The control component 120 may drive firmware, which is referred to as a flash translation layer (FTL), to control general operations of the memory system 10. For example, the FTL may perform operations, such as logical-to-physical (L2P) mapping, wear leveling, garbage collection, and/or bad block handling. The L2P mapping is known as logical block addressing (LBA).
The ECC component 130 may detect and correct errors in the data read from the memory device 200 during the read operation. The ECC component 130 may not correct error bits when the number of the error bits is greater than or equal to a threshold number of correctable error bits, and instead may output an error correction fail signal indicating failure in correcting the error bits.
The ECC component 130 may perform an error correction operation based on a coded modulation, such as a low-density parity-check (LDPC) code, a Bose-Chaudhuri-Hocquenghem (BCH) code, a turbo code, a turbo product code (TPC), a Reed-Solomon (RS) code, a convolution code, a recursive systematic code (RSC), a trellis-coded modulation (TCM), and a block coded modulation (BCM).
The host interface 140 may communicate with the host device through one or more of various interface protocols, such as a universal serial bus (USB), a multi-media card (MMC), a peripheral component interconnect express (PCI-e or PCIe), a small computer system interface (SCSI), a serial-attached SCSI (SAS), a serial advanced technology attachment (SATA), a parallel advanced technology attachment (PATA), an enhanced small disk interface (ESDI), and an integrated drive electronics (IDE).
The memory interface 150 may provide an interface between the controller 100 and the memory device 200 to allow the controller 100 to control the memory device 200 in response to a request from the host device. The memory interface 150 may generate control signals for the memory device 200 and process data under the control of the control component or CPU 120. When the memory device 200 is a flash memory such as a NAND flash memory, the memory interface 150 may generate control signals for the memory and process data under the control of the CPU 120.
The memory device 200 may include a memory cell array 210, a control circuit 220, a voltage generation circuit 230, a row decoder 240, a page buffer 250, which may be in the form of an array of page buffers, a column decoder 260, and an input/output circuit 270. The memory cell array 210 may include a plurality of memory blocks 211 which may store data. The voltage generation circuit 230, the row decoder 240, the page buffer (array) 250, the column decoder 260 and the input/output circuit 270 may form a peripheral circuit for the memory cell array 210. The peripheral circuit may perform a program, read, or erase operation of the memory cell array 210. The control circuit 220 may control the peripheral circuit.
The voltage generation circuit 230 may generate operation voltages of various levels. For example, in an erase operation, the voltage generation circuit 230 may generate operation voltages of various levels such as an erase voltage and a pass voltage.
The row decoder 240 may be in electrical communication with the voltage generation circuit 230, and the plurality of memory blocks 211. The row decoder 240 may select at least one memory block among the plurality of memory blocks 211 in response to a row address RADD generated by the control circuit 220, and transmit operation voltages supplied from the voltage generation circuit 230 to the selected memory blocks.
The page buffer (array) 250 may be in electrical communication with the memory cell array 210 through bit lines BL (shown in
The column decoder 260 may transmit data to, and receive data from, the page buffer (array) 250, and may also exchange data with the input/output circuit 270.
The input/output circuit 270 may transmit to the control circuit 220 a command and an address, received from an external device (e.g., the memory controller 100), transmit data from the external device to the column decoder 260, or output data from the column decoder 260 to the external device, through the input/output circuit 270.
The control circuit 220 may control the peripheral circuit in response to the command and the address.
Referring to
The exemplary memory block 211 may further include a plurality of cell strings 221 respectively coupled to bit lines BL0 to BLm−1. The cell string of each column may include one or more drain selection transistors DST and one or more source selection transistors SST. In the illustrated embodiment, each cell string has one DST and one SST. In a cell string, a plurality of memory cells or memory cell transistors MC0 to MCn−1 may be serially coupled between the selection transistors DST and SST. Each of the memory cells may be formed as a multi-level cell (MLC) storing data information of multiple bits.
The source of the SST in each cell string may be coupled to a common source line CSL, and the drain of each DST may be coupled to the corresponding bit line. Gates of the SSTs in the cell strings may be coupled to the SSL, and gates of the DSTs in the cell strings may be coupled to the DSL. Gates of the memory cells across the cell strings may be coupled to respective word lines. That is, the gates of memory cells MC0 are coupled to corresponding word line WL0, the gates of memory cells MC1 are coupled to corresponding word line WL1, etc. The group of memory cells coupled to a particular word line may be referred to as a physical page. Therefore, the number of physical pages in the memory block 211 may correspond to the number of word lines.
As previously noted, the page buffer 250 may be in the form of a page buffer array including a plurality of page buffers 251 that are coupled to the bit lines BL0 to BLm−1. The page buffers 251 may operate in response to page buffer control signals. For example, the page buffers 251 my temporarily store data received through the bit lines BL0 to BLm−1 or sense voltages or currents of the bit lines during a read or verify operation.
In some embodiments, the memory blocks 211 may include a NAND-type flash memory cell. However, the memory blocks 211 are not limited to such cell type, but may include NOR-type flash memory cell(s). Memory cell array 210 may be implemented as a hybrid flash memory in which two or more types of memory cells are combined, or one-NAND flash memory in which a controller is embedded inside a memory chip.
Many memory systems 100 are in the configuration of an SSD, e.g., an M.2 SSD, in the form of a non-rigid, thin, rectangular element, similar in shape to a stick of gum. M.2 SSD's are 22 mm wide and come in various lengths depending on their specific form factor designation. A surface of the SSD contains a PCB and other components. Such SSDs are somewhat fragile, and as a consequence, are prone to damage, even from slight mishandling. Embodiments of the present invention are directed to tools and methods for improving handling of such SSDs.
In accordance with embodiments of the present invention, a drive loading jig and methods of using the same are provided. Use of the jig to insert a drive into, and remove it from, a host advantageously greatly decreases the likelihood that the PCB or components of the drive will be damaged as a result of mishandling. From the user's standpoint, the drive loading jig takes at least some of the guesswork out of the installation and removal processes. The design and rigidity of the loading jig prevents inadvertent bending of the PCB of the drive that may otherwise easily occur during installation or removal.
As can be seen, the M.2 drive 40 is a relatively flat, rectangular piece. The M.2 drive 40 includes a PCB and various functional components, such as those described in connection with
Referring to
If the drive 40 is not inserted at a proper insertion angle, it may not sit in the host connector 51 properly. This may prompt the user or operator to apply force to the drive 40 in an effort to better position the drive 40 into the host connector 51, which may, in turn, damage the PCB of the drive 40 and/or components thereof. Such mishandling is even more likely to lead to a problem when the operator needs to insert or remove hundreds of drives as part of a batch testing or assembly process.
Thus, according to embodiments of the present invention, a drive loading jig 60, as shown in
As shown in
When the drive 40 is fully inserted into the drive loading jig 60, as shown in
As shown in
Referring to
The restraint walls, particularly the top and bottom restraint walls 71a-T, 71b-T, 71a-B and 71b-B, cooperate to support the longitudinal edges of the drive 40, e.g., M.2 drive, on both its top and bottom surfaces when the drive 40 is inserted into the jig 60. Such support reduces the risk of excess bending of the PCB in the positive (+) and negative (−) Z directions shown in
Overall, the slots 65a, 65b including their respective sets of walls (71a-T, 71a-S, 71a-B) and 71b-T, 71b-S, 71b-B) are dimensioned to accommodate components on the drive 40, to ensure that the drive 40 slides with little or no resistance into and out of the loading jig 60, and to prevent the drive 40 from excessively bending, i.e., to the point of being damaged or inoperable, during installation and removal.
Instances which can cause bending of the PCB of the M.2 drive 40, leading to drive failures, can occur during installation of the M.2 drive 40 into an M.2 drive adapter card 80, which is shown in
During the installation process, it is possible for the operator to attempt to over-insert the drive 40 into the M.2 connector 81 on the drive adapter card 80, which can cause bending of the PCB of the drive 40, thus causing drive failure. Moreover, if there is misalignment in the initial insertion of the connector interface 41 of the drive 40 into the connector 81, the act of moving or swinging the drive 40 down to engage it with the fastening feature 82 of the adapter card 80 may also cause bending of the PCB of the drive 40, which in turn may cause drive failure. Other types of mishandling of the drive 40 during installation may also occur. For example, using a finger to push down on the mid-span of the PCB of the drive 40 while guiding it to the adapter card 80, can cause PCB bending leading to drive failure.
To use the loading jig 60, first the key-way 43 on the drive 40 is aligned with the loading jig key-way 63 on the jig 60 so that the two key-ways are at the same position on the X-axis in
With the drive 40 so placed in the jig 60, the operator may then fix the drive/jig assembly to the adapter card 80. Initially, the operator may align the jig 60 at least at a 5° inclined angle to the adapter card 80. Additionally, the operator may align the connector interface 41 so that its key-way 43 aligns with a key 81a of the connector 81 on the adapter card 80. Once the jig 60 is so aligned, it is ready to be inserted into the adapter card 80. The operator may insert the drive 40 until its connector interface 41 reaches the proper insertion depth in the connector 81 on the adapter card 80. Then, the loading jig 60 can be swung down into place, positioning the drive 40 in its final installed position in which the mounting cutout 44 of the drive 40 is gripped with the locking or fastening feature 82 of the adapter card 80. The retainer access area 67 of the loading jig 60 may be utilized to allow the jig 60 to be used with different types of locking or fastening features 82, such as screw, snap, slide lock, or spring-finger locking or fastening features.
The jig 60 is designed to be modular, in that it is capable of being scaled to accommodate installation of multiple drives 40 with a single procedure. Additionally, the jig 60 is capable of installing drives 40 to both sides of the adapter card 80 when configured with connectors 81 on both surfaces, as can be seen in
For the purpose of securing the adapter card 80 during the installation process, an adapter card fixture 93 may be employed, as shown in
Initially, at step 1001, the key-way 43 on the drive 40 is aligned with the key-way 63 on the drive loading jig 60. When the drive 40 is inserted into the jig 60, both the alignment key-way 63 on the loading jig 60 and the key-way 43 on the drive 40 are at the same position along the X-axis shown in
At step 1002, the insertion end 42 of the drive 40 is aligned with the open end 64 of the drive loading jig 60 to orient the longitudinal edges of the drive 40 with the slots 65a, 65b along the length of the jig 60. When so aligned, at step 1003, the drive 40 is inserted into the jig 60 to a depth defined by the stoppers 66a, 66b in the jig 60, such that the longitudinal edges of the drive 40 are secured in their respective slots 65a, 65b, and such that the connector interface 41 of the drive 40 is exposed at the open end 64 of the jig 60.
As noted above, the driving loading jig 60 with the drive 40 loaded therein may be used with the drive adapter card 80. In this embodiment, the loading jig/drive assembly is mounted on the adapter card 80.
Thus, in step 1004, the jig/drive assembly is positioned such that the length of the jig 60 (or jig/drive assembly) with respect to a mating surface of the adapter card 80 is within a set insertion angle range, which is at least 5° to the surface. Here, the mating surface of the adapter card 80 may be a major or principle surface thereof, i.e., the surface on which the connector 81 and the locking or fastening feature 82 are mounted. The insertion angle range is at least 5°. In an embodiment, the preferred insertion angle is 20°. In another embodiment, the preferred is 25°+/−5°.
Next, in step 1005, while maintaining the proper angular orientation of the jig/drive assembly with the mating surface of the adapter card 80, the connector interface 41 of the drive 40 is inserted into the connector 81 on the adapter card 80. Then, with the connector interface 41 inserted into the connector 81, in step 1006, the jig/drive assembly is moved or swung downwardly until it is in a parallel position on a major surface of the adapter card 80. In step 1007, the jig/drive assembly is fastened to the adapter card 80 using the fastener feature 82, which is located remotely from the connector 81 to support the other end of the jig/drive assembly.
At step 1008, the loading jig 60 may be removed from the jig/drive assembly. The loading jig 60 may be slid away from the connector end of the drive 40 along the Y-axis shown in
As the foregoing demonstrates, embodiments of the present invention provide tools and techniques for inserting a drive into, and removing it from, a host, which greatly decreases the likelihood that the PCB or components of the drive will be damaged as a result of mishandling. The drive loading jig disclosed herein is easy to use. Moreover, the rigidity of the jig prevents inadvertent bending of the PCB of the drive that may otherwise easily occur during installation or removal.
Although the foregoing embodiments have been described in some detail for purposes of clarity and understanding, the present invention is not limited to the details provided. There are many alternative ways of implementing the invention, as one skilled in the art will appreciate in light of the foregoing disclosure. The disclosed embodiments are thus illustrative, not restrictive.
This application claims the benefit of U.S. Provisional Application No. 62/681,437, filed Jun. 6, 2018, the entire content of which is incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 62681437 | Jun 2018 | US |
