Patent Application
20250232733
This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2024-0006644, filed on Jan. 16, 2024 in the Korean Intellectual Property Office (KIPO), the content of which is herein incorporated by reference in its entirety.
Embodiments of the present inventive concept relate to a display device, and more particularly to a driver including complementary metal-oxide-semiconductor (CMOS) transistors, and a display device including the driver.
A driver (e.g., a gate driver and/or an emission driver) of a display device may sequentially provide signals (e.g., gate signals and/or emission signals) to pixels of a display panel on a row-by-row basis. To sequentially provide the signals on the row-by-row basis, the driver may be implemented in a form of a shift register including a plurality of stages.
In general, each stage of the driver may include only a single type of transistor, for example a p-type metal-oxide-semiconductor (PMOS) transistor. In a case where each stage includes only the PMOS transistor, to output an output signal having a low voltage level, a bootstrapping operation that decreases a voltage of an internal node of the stage to a voltage level lower than the low voltage level should be performed.
Some embodiments provide a driver in which each stage includes complementary metal-oxide-semiconductor (CMOS) transistors.
Some embodiments provide a display device including a driver in which each stage includes CMOS transistors.
According to embodiments, there is provided a driver including a plurality of stages. At least one stage of the plurality of stages includes an input circuit configured to transfer an input signal to a first node in response to at least one of a clock signal and an inverted clock signal, a holding capacitor configured to hold a voltage of the first node, a first inverter configured to generate a voltage of a second node by inverting the voltage of the first node, a second inverter configured to generate a voltage of a third node by inverting the voltage of the second node, a third inverter configured to generate a carry signal by inverting the voltage of the second node, and an output control circuit configured to selectively output the voltage of the third node as an output signal in response to an output enable signal. At least one of the first inverter, the second inverter, the third inverter and the output control circuit includes a p-type metal-oxide-semiconductor (PMOS) transistor and an n-type metal-oxide-semiconductor (NMOS) transistor that are connected in series.
In embodiments, a first active region of the PMOS transistor may include a material different from a material of a second active region of the NMOS transistor.
In embodiments, the first active region of the PMOS transistor may include polycrystalline silicon, and the second active region of the NMOS transistor may include an oxide semiconductor, an organic semiconductor or amorphous silicon.
In embodiments, the NMOS transistor may include a top gate located above the second active region, and a bottom gate located below the second active region. A low gate voltage may be applied to a terminal of the NMOS transistor, and a second low gate voltage lower than the low gate voltage may be applied to the bottom gate of the NMOS transistor.
In embodiments, the output control circuit may output a low gate voltage as the output signal while the output enable signal has a high level, and may output the voltage of the third node as the output signal while the output enable signal has a low level.
In embodiments, the output control circuit may include a first PMOS transistor including a gate which receives the output enable signal, a first terminal connected to the third node, and a second terminal connected to an output node at which the output signal is output, and a first NMOS transistor including a gate which receives the output enable signal, a first terminal connected to a line which transfers a low gate voltage, and a second terminal connected to the output node.
In embodiments, the input circuit may include at least one of a second PMOS transistor including a gate which receives the inverted clock signal, a first terminal which receives the input signal, and a second terminal connected to the first node, and a second NMOS transistor including a gate which receives the clock signal, a first terminal which receives the input signal, and a second terminal connected to the first node.
In embodiments, the holding capacitor may include a first electrode connected to a line which transfers a high gate voltage, and a second electrode connected to the first node.
In embodiments, the first inverter may include a third PMOS transistor including a gate connected to the first node, a first terminal connected to a line which transfers a high gate voltage, and a second terminal connected to the second node, and a third NMOS transistor including a gate connected to the first node, a first terminal connected to a line which transfers a low gate voltage, and a second terminal connected to the second node.
In embodiments, the second inverter may include a fourth PMOS transistor including a gate connected to the second node, a first terminal connected to a line which transfers a high gate voltage, and a second terminal connected to the third node, and a fourth NMOS transistor including a gate connected to the second node, a first terminal connected to a line which transfers a low gate voltage, and a second terminal connected to the third node.
In embodiments, the third inverter may include a fifth PMOS transistor including a gate connected to the second node, a first terminal connected to a line which transfers a high gate voltage, and a second terminal connected to a carry node at which the carry signal is output, and a fifth NMOS transistor including a gate connected to the second node, a first terminal connected to a line which transfers a low gate voltage, and a second terminal connected to the carry node.
In embodiments, the at least one stage may further include a sixth PMOS transistor including a gate which receives a global reset signal, a first terminal connected to a line which transfers a high gate voltage, and a second terminal connected to the first node.
In embodiments, the at least one stage may further include a PMOS boosting buffer, wherein the voltage of the first node has a low level, and the PMOS boosting buffer is configured to output a low gate voltage to the third node.
In embodiments, the PMOS boosting buffer may include a boosting capacitor including a first electrode connected to a carry node at which the carry signal is output, and a second electrode connected to a fourth node, a seventh PMOS transistor including a gate connected to a line which transfers the low gate voltage, a first terminal connected to the first node, and a second terminal connected to the fourth node, and an eighth PMOS transistor including a gate connected to the fourth node, a first terminal connected to the third node, and a second terminal connected to the line which transfers the low gate voltage.
In embodiments, the output control circuit may output the voltage of the third node as the output signal while the output enable signal has a high level, and may output a low gate voltage as the output signal while the output enable signal has a low level.
In embodiments, the output control circuit may include a first NMOS transistor including a gate which receives the output enable signal, a first terminal connected to the third node, and a second terminal connected to an output node at which the output signal is output, and a first PMOS transistor including a gate which receives the output enable signal, a first terminal connected to a line which transfers a low gate voltage, and a second terminal connected to the output node.
According to embodiments, there is provided a driver including a plurality of stages. At least one stage of the plurality of stages includes a first PMOS transistor including a gate which receives an output enable signal, a first terminal connected to a third node, and a second terminal connected to an output node, a first NMOS transistor including a gate which receives the output enable signal, a first terminal connected to a line which transfers a low gate voltage, and a second terminal connected to the output node, a second PMOS transistor including a gate which receives an inverted clock signal, a first terminal which receives an input signal, and a second terminal connected to a first node, a second NMOS transistor including a gate which receives a clock signal, a first terminal which receives the input signal, and a second terminal connected to the first node, a holding capacitor including a first electrode connected to a line which transfers a high gate voltage, and a second electrode connected to the first node, a third PMOS transistor including a gate connected to the first node, a first terminal connected to the line which transfers the high gate voltage, and a second terminal connected to a second node, a third NMOS transistor including a gate connected to the first node, a first terminal connected to the line which transfers the low gate voltage, and a second terminal connected to the second node, a fourth PMOS transistor including a gate connected to the second node, a first terminal connected to the line which transfers the high gate voltage, and a second terminal connected to the third node, a fourth NMOS transistor including a gate connected to the second node, a first terminal connected to the line which transfers the low gate voltage, and a second terminal connected to the third node, a fifth PMOS transistor including a gate connected to the second node, a first terminal connected to the line which transfers the high gate voltage, and a second terminal connected to a carry node, a fifth NMOS transistor including a gate connected to the second node, a first terminal connected to the line which transfers the low gate voltage, and a second terminal connected to the carry node, and a sixth PMOS transistor including a gate which receives a global reset signal, a first terminal connected to the line which transfers the high gate voltage, and a second terminal connected to the first node.
In embodiments, the at least one stage may further include a boosting capacitor including a first electrode connected to the carry node, and a second electrode connected to a fourth node, a seventh PMOS transistor including a gate connected to the line which transfers the low gate voltage, a first terminal connected to the first node, and a second terminal connected to the fourth node, and an eighth PMOS transistor including a gate connected to the fourth node, a first terminal connected to the third node, and a second terminal connected to the line which transfers the low gate voltage.
According to embodiments, there is provided a display device including a display panel including a plurality of pixels, a data driver configured to provide data signals to the plurality of pixels, a gate driver configured to provide gate signals to the plurality of pixels, an emission driver configured to provide emission signals to the plurality of pixels, and a controller configured to control the data driver, the gate driver and the emission driver. At least one of the gate driver and the emission driver includes a plurality of stages. At least one stage of the plurality of stages includes an input circuit configured to transfer an input signal to a first node in response to at least one of a clock signal and an inverted clock signal, a holding capacitor configured to hold a voltage of the first node, a first inverter configured to generate a voltage of a second node by inverting the voltage of the first node, a second inverter configured to generate a voltage of a third node by inverting the voltage of the second node, a third inverter configured to generate a carry signal by inverting the voltage of the second node, and an output control circuit configured to selectively output the voltage of the third node as an output signal in response to an output enable signal. At least one of the first inverter, the second inverter, the third inverter and the output control circuit includes a p-type metal-oxide-semiconductor (PMOS) transistor and an n-type metal-oxide-semiconductor (NMOS) transistor that are connected in series.
In embodiments, the display panel may include a first panel region driven at a first driving frequency, and a second panel region driven at a second driving frequency lower than the first driving frequency. In a first frame period, the controller may generate the output enable signal having a first level during a first time within the first frame period allocated to the first panel region and a second time within the first frame period allocated to the second panel region such that the plurality of stages outputs output signals to both of the first panel region and the second panel region. In a second frame period, the controller may generate the output enable signal having the first level during a third time within the second frame period allocated to the first panel region and a second level different from the first level during a fourth time within the second frame period allocated to the second panel region such that the plurality of stages outputs the output signals to the first panel region and does not output the output signals to the second panel region.
As described above, in a driver and a display device according to embodiments, at least one stage may include an input circuit, a first inverter, a second inverter, a third inverter and an output control circuit, and at least one of the first inverter, the second inverter, the third inverter and the output control circuit may include both of a PMOS transistor and an NMOS transistor, or CMOS transistors. Accordingly, a bootstrapping operation may not be desired or performed in the stage, and power consumption of the driver and the display device may be reduced.
Further, in the driver and the display device according to embodiments, the output control circuit may selectively output an output signal in response to an output enable signal. Accordingly, the driver according to embodiments may be suitable for a display device that performs a multi-frequency driving (MFD) operation.
Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.
The embodiments are described more fully hereinafter with reference to the accompanying drawings. Like or similar reference numerals refer to like or similar elements throughout.
Referring to
The first stage STG1 may receive the start signal FLM as an input signal, and each of the subsequent stages STG2, STG3, STG4, etc. may receive a carry signal of a previous stage as the input signal. For example, the second stage STG2 may receive the first carry signal CR1 of the first stage STG1 as the input signal, the third stage STG3 may receive the second carry signal CR2 of the second stage STG2 as the input signal, and the fourth stage STG4 may receive the third carry signal CR3 of the third stage STG3 as the input signal.
In some embodiments, each odd-numbered stage STG1, STG3, etc. may start outputting the carry signal CR1, CR3, etc. when the clock signal CLK has a high level, and each even-numbered stage STG2, STG4, etc. may start outputting the carry signal CR2, CR4, etc. when the inverted clock signal CLKB has the high level. For example, when the clock signal CLK becomes the high level after the start signal FLM becomes the high level, the first stage STG1 may start outputting the first carry signal CR1 having the high level. When the inverted clock signal CLKB becomes the high level after the first carry signal CR1 becomes the high level, the second stage STG2 may start outputting the second carry signal CR2 having the high level. When the clock signal CLK becomes the high level after the second carry signal CR2 becomes the high level, the third stage STG3 may start outputting the third carry signal CR3 having the high level. When the inverted clock signal CLKB becomes the high level after the third carry signal CR3 becomes the high level, the fourth stage STG4 may start outputting the fourth carry signal CR4 having the high level. In this manner, the plurality of stages STG1, STG2, STG3, STG4, etc. may sequentially output the carry signals CR1, CR2, CR3, CR4, etc. by delaying or shifting the carry signals CR1, CR2, CR3, CR4, etc. by half a period of the clock signal CLK.
Further, each stage STG1, STG2, STG3, STG4, etc. may selectively output its output signal having the high level according to a level of the output enable signal OUT_EN while outputting its carry signal having the high level. For example, while the first carry signal CR1 having the high level is output, the first stage STG1 may output a first output signal OUT1 having the high level in response to the output enable signal OUT_EN having a first level (e.g., a low level in an example of
Referring to
The input circuit INC may transfer an input signal SIN to a first node N1 in response to at least one of a clock signal CLK and an inverted clock signal CLKB. The input signal SIN may be a start signal FLM in a case where the stage 200 is a first stage, or may be a carry signal PCR of a previous stage in a case where the stage 200 is a subsequent stage. In some embodiments, the input circuit INC may be implemented as, but is not limited to, a complementary metal-oxide-semiconductor (CMOS) transmission gate including a p-type metal-oxide-semiconductor (PMOS) transistor and an n-type metal-oxide-semiconductor (NMOS) transistor connected in parallel. In other embodiments, the input circuit INC may include only the PMOS transistor, or may include only the NMOS transistor. The holding capacitor CHOLD may maintain a voltage of the first node N1.
The first inverter INV1 may generate a voltage of a second node N2 by inverting a voltage of the first node N1. The second inverter INV2 may generate a voltage of a third node N3 by inverting the voltage of the second node N2. The third inverter INV3 may generate a carry signal CR by inverting the voltage of the second node N2. Thus, when the first node N1 has a high gate voltage VGH, the voltage of the third node N3 may have a high level, and the carry signal CR having the high level may be output.
The output control circuit OCC may selectively output the voltage of the third node N3 as an output signal OUT in response to the output enable signal OUT_EN. In some embodiments, the output control circuit OCC may output the output signal OUT having a low level while the output enable signal OUT_EN has the high level, and may output the voltage of the third node N3 as the output signal OUT while the output enable signal OUT_EN has the low level. In other embodiments, the output control circuit OCC may output the voltage of the third node N3 as the output signal OUT while the output enable signal OUT_EN has the high level, and may output the output signal OUT having the low level while the output enable signal OUT_EN has the low level.
In each stage 200 of the driver according to embodiments, at least one of the first inverter INV1, the second inverter INV2, the third inverter INV3 and the output control circuit OCC may include a PMOS transistor and an NMOS transistor that are connected in series. In some embodiments, a first active region of the PMOS transistor may include a material different from a material of a second active region of the NMOS transistor. Further, in some embodiments, the NMOS transistor may include a top gate located above the second active region and a bottom gate located below the second active region.
For example, as illustrated in
Further, the bottom gate BML of the NMOS transistor NT may be formed on the second gate insulating layer GI2. For example, the bottom gate BML may include a metal material such as molybdenum, but is not limited thereto. In some embodiments, a terminal (e.g., a third source/drain region SD3 or a fourth source/drain region SD4) of the NMOS transistor NT may receive a low gate voltage that is a low voltage of the input signal SIN, the clock signal CLK, the inverted clock signal CLKB, the carry signal CR and the output signal OUT, and the bottom gate BML of the NMOS transistor NT may receive a second low gate voltage lower than the low gate voltage. In this case, a threshold voltage of the NMOS transistor NT may be increased, and thus a leakage current through the NMOS transistor NT may be reduced. A first interlayer insulating layer ILD1 may be formed on the bottom gate BML. For example, the first interlayer insulating layer ILD1 may include silicon oxide or silicon nitride, but is not limited thereto.
A third source/drain region SD3, the second active region ACT2 and a fourth source/drain region SD4 of the NMOS transistor NT may be formed on the first interlayer insulating layer ILD1. The second active region ACT2 of the NMOS transistor NT may include a material different from the material of the first active region ACT1 of the PMOS transistor PT. For example, the second active region ACT2 of the NMOS transistor NT may include an oxide semiconductor, an organic semiconductor, amorphous silicon, etc. That is, in some embodiments, the first active region ACT1 of the PMOS transistor PT may include polycrystalline silicon, and the second active region ACT2 of the NMOS transistor NT may include an oxide semiconductor, an organic semiconductor or amorphous silicon. Further, in some embodiments, as illustrated in
Each stage of a conventional driver may include only a single type of transistor. For example, in a case where each stage includes only a PMOS transistor, to output an output signal having a low voltage level, a bootstrapping operation that decreases a voltage of an internal node of the stage to a voltage level lower than the low voltage level should be performed. Further, in a case where each stage includes only an NMOS transistor, to output an output signal having a high voltage level, a bootstrapping operation that increases a voltage of an internal node of the stage to a voltage level higher than the high voltage level should be performed.
However, as described above, in each stage 200 of the driver according to embodiments, at least one of the first inverter INV1, the second inverter INV2, the third inverter INV3 and the output control circuit OCC may include both of the PMOS transistor PT and the NMOS transistor NT, or CMOS transistors. Further, in some embodiments, the PMOS transistor PT may output a high voltage (e.g., the high gate voltage VGH), and the NMOS transistor NT may output a low voltage (e.g., the low gate voltage). Accordingly, the bootstrapping operation may not be desired or performed in the stage 200, and power consumption of the driver and a display device including the driver may be reduced.
Further, in the stage 200 of the driver according to embodiments, the output control circuit OCC may selectively output the output signal OUT in response to the output enable signal OUT_EN. Accordingly, the driver according to embodiments may be suitable for a display device that performs a multi-frequency driving (MFD) operation.
Referring to
The input circuit INC may transfer an input signal SIN to a first node N1 in response to at least one of a clock signal CLK and an inverted clock signal CLKB. In some embodiments, the input circuit INC may include a second PMOS transistor PT2 that transfers the input signal SIN to the first node N1 in response to the inverted clock signal CLKB. In other embodiments, the input circuit INC may include a second NMOS transistor NT2 that transfers the input signal SIN to the first node N1 in response to the clock signal CLK. In still other embodiments, as illustrated in
The holding capacitor CHOLD may maintain a voltage of the first node N1 while the second PMOS transistor PT2 and the second NMOS transistor NT2 of the input circuit INC are turned off. In some embodiments, as illustrated in
The first inverter INV1 may generate a voltage of a second node N2 by inverting the voltage of the first node N1. For example, the first inverter INV1 may provide the low gate voltage VGL to the second node N2 when the first node N1 has the high gate voltage VGH, and may provide the high gate voltage VGH to the second node N2 when the first node N1 has the low gate voltage VGL. In some embodiments, the first inverter INV1 may be implemented as a CMOS inverter including a third PMOS transistor PT3 and a third NMOS transistor NT3 that are connected in series between the line which transfers the high gate voltage VGH and the line which transfers the low gate voltage VGL. Further, in some embodiments, the third PMOS transistor PT3 may include a gate connected to the first node N1, a first terminal connected to the line which transfers the high gate voltage VGH, and a second terminal connected to the second node N2. The third NMOS transistor NT3 may include a gate connected to the first node N1, a first terminal connected to the line which transfers the low gate voltage VGL, and a second terminal connected to the second node N2.
The second inverter INV2 may generate a voltage of a third node N3 by inverting the voltage of the second node N2. For example, the second inverter INV2 may provide the low gate voltage VGL to the third node N3 when the second node N2 has the high gate voltage VGH, and may provide the high gate voltage VGH to the third node N3 when the second node N2 has the low gate voltage VGL. In some embodiments, the second inverter INV2 may be implemented as a CMOS inverter including a fourth PMOS transistor PT4 and a fourth NMOS transistor NT4 that are connected in series between the line which transfers the high gate voltage VGH and the line which transfers the low gate voltage VGL. Further, in some embodiments, the fourth PMOS transistor PT4 may include a gate connected to the second node N2, a first terminal connected to the line which transfers the high gate voltage VGH, and a second terminal connected to the third node N3. The fourth NMOS transistor NT4 may include a gate connected to the second node N2, a first terminal connected to the line which transfers the low gate voltage VGL, and a second terminal connected to the third node N3.
The third inverter INV3 may generate a carry signal CR by inverting the voltage of the second node N2. For example, the third inverter INV3 may generate the carry signal CR having the low gate voltage VGL when the second node N2 has the high gate voltage VGH, and may generate the carry signal CR having the high gate voltage VGH when the second node N2 has the low gate voltage VGL. In some embodiments, the third inverter INV3 may be implemented as a CMOS inverter including a fifth PMOS transistor PT5 and a fifth NMOS transistor NT5 that are connected in series between the line which transfers the high gate voltage VGH and the line which transfers the low gate voltage VGL. Further, in some embodiments, the fifth PMOS transistor PT5 may include a gate connected to the second node N2, a first terminal connected to the line which transfers the high gate voltage VGH, and a second terminal connected to a carry node NC at which the carry signal CR is output. The fifth NMOS transistor NT5 may include a gate connected to the second node N2, a first terminal connected to the line which transfers the low gate voltage VGL, and a second terminal connected to the carry node NC.
The sixth PMOS transistor PT6 may transfer the high gate voltage VGH to the first node N1 in response to a global reset signal ESR. In some embodiments, the global reset signal ESR may have a low level when a power-on sequence of a display device is performed and may be simultaneously provided to a plurality of stages of the driver. Thus, the sixth PMOS transistors PT6 of the plurality of stages may transfer the high gate voltage VGH to the first node N1 during the power-on sequence, thereby stabilizing voltages of nodes N1, N2, N3, NC and NO of the plurality of stages. Further, in some embodiments, the sixth PMOS transistor PT6 may include a gate which receives the global reset signal ESR, a first terminal connected to the line which transfers the high gate voltage VGH, and a first terminal connected to the first node N1. Although
The output control circuit OCC may selectively output the voltage of the third node N3 as an output signal OUT in response to an output enable signal OUT_EN. The output control circuit OCC may output the low gate voltage VGL as the output signal OUT regardless of the voltage of the third node N3 while the output enable signal OUT_EN has a high level, or the high gate voltage VGH. However, while the output enable signal OUT_EN has a low level, or the low gate voltage VGL, the output control circuit OCC may output the voltage of the third node N3 as the output signal OUT. In some embodiments, the output control circuit OCC may include a first PMOS transistor PT1 for outputting the voltage of the third node N3 as the output signal OUT, and a first NMOS transistor NT1 for outputting the low gate voltage VGL as the output signal OUT. Further, in some embodiments, the first PMOS transistor PT1 may include a gate which receives the output enable signal OUT_EN, a first terminal connected to the third node N3, and a second terminal connected to an output node NO at which the output signal OUT is output. The first NMOS transistor NT1 may include a gate which receives the output enable signal OUT_EN, a first terminal connected to the line which transfers the low gate voltage VGL, and a second terminal connected to the output node NO.
In some embodiments, as illustrated in
Hereinafter, an example of an operation of the stage 200a will be described with reference to
Referring to
In a case where the output enable signal OUT_EN has the low gate voltage VGL, in a first time period TP1 in which the input signal SIN has the high gate voltage VGH and the clock signal CLK has the high gate voltage VGH, the stage 200a may output the carry signal CR having the high gate voltage VGH and the output signal OUT having the high gate voltage VGH.
For example, in the first time period TP1, as illustrated in
The third PMOS transistor PT3 may be turned off in response to the high gate voltage VGH of the first node N1, the third NMOS transistor NT3 may be turned on in response to the high gate voltage VGH of the first node N1, and the third NMOS transistor NT3 may transfer the low gate voltage VGL to the second node N2. Thus, the second node N2 may have the low gate voltage VGL.
The fourth NMOS transistor NT4 may be turned off in response to the low gate voltage VGL of the second node N2, the fourth PMOS transistor PT4 may be turned on in response to the low gate voltage VGL of the second node N2, and the fourth PMOS transistor PT4 may transfer the high gate voltage VGH to the third node N3. Thus, the third node N3 may have the high gate voltage VGH.
Further, the fifth NMOS transistor NT5 may be turned off in response to the low gate voltage VGL of the second node N2, the fifth PMOS transistor PT5 may be turned on in response to the low gate voltage VGL of the second node N2, and the fifth PMOS transistor PT5 may transfer the high gate voltage VGH to the carry node NC. Thus, the carry signal CR having the high gate voltage VGH may be output at the carry node NC.
In the case where the output enable signal OUT_EN has the low gate voltage VGL, as illustrated in
In other embodiments, in a case where the output enable signal OUT_EN has the high gate voltage VGH as indicated by the dashed line in
For example, in the first time period TP1, as illustrated in
As described above, the stage 200a may output the output signal OUT having the high gate voltage VGH in response to the output enable signal OUT_EN having the low level (or the low gate voltage VGL), and may not output the output signal OUT having the high gate voltage VGH in response to the output enable signal OUT_EN having the high level (or the high gate voltage VGH). Accordingly, the driver including the stage 200a may selectively output the output signals OUT in a period in which the output enable signal OUT_EN has the low level, but may not output the output signals OUT in a period in which the output enable signal OUT_EN has the high level. Thus, the driver including the stage 200a may selectively output the output signals OUT to respective panel regions of a display panel. Therefore, the driver including the stage 200a may be suitable for a display device that performs a multi-frequency driving (MFD) operation that drives the respective panel regions at different driving frequencies.
In a second time period TP2 in which the input signal SIN has the low gate voltage VGL and the clock signal CLK has the high gate voltage VGH, the stage 200a may output the carry signal CR having the low gate voltage VGL and the output signal OUT having the low gate voltage VGL.
For example, in the second time period TP2, as illustrated in
The third NMOS transistor NT3 may be turned off in response to the low gate voltage VGL of the first node N1, the third PMOS transistor PT3 may be turned on in response to the low gate voltage VGL of the first node N1, and the third PMOS transistor PT3 may transfer the high gate voltage VGH to the second node N2. Thus, the second node N2 may have the high gate voltage VGH.
The fourth PMOS transistor PT4 may be turned off in response to the high gate voltage VGH of the second node N2, the fourth NMOS transistor NT4 may be turned on in response to the high gate voltage VGH of the second node N2, and the fourth NMOS transistor NT4 may transfer the low gate voltage VGL to the third node N3. Thus, the third node N3 may have the low gate voltage VGL.
Further, the fifth PMOS transistor PT5 may be turned off in response to the high gate voltage VGH of the second node N2, the fifth NMOS transistor NT5 may be turned on in response to the high gate voltage VGH of the second node N2, and the fifth NMOS transistor NT5 may transfer the low gate voltage VGL to the carry node NC. Thus, the carry signal CR having the low gate voltage VGL may be output at the carry node NC.
As illustrated in
Referring to
When a voltage of a first node N1 has a low level, the PMOS boosting buffer PBB may output a low gate voltage VGL to a third node N3. In some embodiments, the PMOS boosting buffer PBB may include a boosting capacitor CBOOST including a first electrode connected to a carry node NC at which a carry signal CR is output, and a second electrode connected to a fourth node N4, a seventh PMOS transistor PT7 including a gate connected to a line which transfers the low gate voltage VGL, a first terminal connected to the first node N1, and a second terminal connected to the fourth node N4, and an eighth PMOS transistor PT8 including a gate connected to the fourth node N4, a first terminal connected to the third node N3, and a second terminal connected to the line which transfers the low gate voltage VGL.
When the voltage of the first node N1 changes from a high gate voltage VGH to the low gate voltage VGL, the seventh PMOS transistor PT7 may transfer the low gate voltage VGL of the first node N1 to the fourth node N4, and the voltage of the fourth node N4 also may change from the high gate voltage VGH to the low gate voltage VGL. When the voltage of the fourth node N4 changes from the high gate voltage VGH to the low gate voltage VGL, the eighth PMOS transistor PT8 may transfer the low gate voltage VGL to the third node N3, the voltage of the third node N3 also may decrease from the high gate voltage VGH to the low gate voltage VGL. Further, when the voltage of the first node N1 changes from the high gate voltage VGH to the low gate voltage VGL while the carry node NC has the high gate voltage VGH, the first inverter INV1 may provide the high gate voltage VGH to a second node N2, the third inverter INV3 may provide the low gate voltage VGL to the carry node NC, and thus the voltage of the carry node NC may decrease from the high gate voltage VGH to the low gate voltage VGL. When the voltage of the carry node NC connected to the first electrode of the boosting capacitor CBOOST decreases, the voltage of the fourth node N4 connected to the second electrode of the boosting capacitor CBOOST also may decreases from the low gate voltage VGL to a boosted low gate voltage lower than the low gate voltage VGL. This operation that decreases the voltage of the fourth node N4 to the boosted low gate voltage lower than the low gate voltage VGL may be referred to as a boosting operation. In other words, while the first node N1 and the third node N3 have the low gate voltage VGL, the voltage of the fourth node N4 may have the boosted low gate voltage lower than the low gate voltage VGL. Since the fourth node N4 has the boosted low gate voltage, the eighth PMOS transistor PT8 may be fully turned on, and the voltage of the third node N3 may rapidly decrease from the high gate voltage VGH to the low gate voltage VGL. Further, in a case where the output enable signal OUT_EN has the low gate voltage VGL, the output signal OUT at the output node NO also may rapidly decrease from the high gate voltage VGH to the low gate voltage VGL.
Referring to
The output control circuit OCC′ may include a first NMOS transistor NT1′ that outputs the voltage of the third node N3 as the output signal OUT when the output enable signal OUT_EN′ has the high level, and a first PMOS transistor PT1′ that outputs the low gate voltage VGL as the output signal OUT when the output enable signal OUT_EN′ has the low level. In some embodiments, the first NMOS transistor NT1′ may include a gate which receives the output enable signal OUT_EN′, a first terminal connected to the third node N3, and a second terminal connected to an output node NO at which the output signal OUT is output. The first PMOS transistor PT1′ may include a gate which receives the output enable signal OUT_EN′, a first terminal connected to a line which transfers the low gate voltage VGL, and a second terminal connected to the output node NO.
As illustrated in
Referring to
Referring to
The display panel 1010 may include data lines, gate lines, emission lines, and the plurality of pixels PX connected thereto. In some embodiments, each pixel PX may include a light emitting element, and the display panel 1010 may be a light emitting display panel. In some embodiments, the light emitting element may be an organic light emitting diode (OLED). In other embodiments, the light emitting element may be a nano light emitting diode (NED), a quantum dot (QD) light emitting diode, a micro light emitting diode, an inorganic light emitting diode, or any other suitable light emitting element. In other embodiments, the display panel 1010 may be a liquid crystal display (LCD) panel, or any other suitable display panel.
The data driver 1030 may generate the data signals DS based on a data control signal DCTRL and output image data ODAT received from the controller 1090, and may provide the data signals DS to the plurality of pixels PX through the data lines. In some embodiments, the data control signal DCTRL may include, but is not limited to, an output data enable signal, a horizontal start signal, and a load signal. In some embodiments, the data driver 1030 and the controller 1090 may be implemented as a single integrated circuit, and the single integrated circuit may be referred to as a timing controller embedded data driver (TED) integrated circuit. In other embodiments, the data driver 1030 and the controller 1090 may be implemented as separate integrated circuits.
The gate driver 1050 may generate the gate signals GS based on a gate control signals GCTRL received from the controller 1090, and may sequentially provide the gate signals GS to the plurality of pixels PX through the gate lines on a row-by-row basis. The gate control signal GCTRL may include, but is not limited to, a gate start signal and a gate clock signal. In some embodiments, the gate control signal GCTRL may further include an output enable signal OUT_EN for selectively outputting the gate signals GS. Further, in some embodiments, the gate driver 1050 may be a driver 100 of
The emission driver 1070 may generate the emission signals EM based on an emission control signal ECTRL received from the controller 1090, and may sequentially provide the emission signals EM to the plurality of pixels PX through the emission lines on a row-by-row basis. The emission control signal ECTRL may include, but is not limited to, an emission start signal and an emission clock signal. In some embodiments, the emission control signal ECTRL may further include an output enable signal OUT_EN for selectively outputting the emission signals EM. Further, in some embodiments, the emission driver 1070 may be a driver 100 of
The controller 1090 (e.g., a timing controller (TCON)) may receive input image data IDAT and a control signal CTRL from an external host processor (e.g., a graphics processing unit (GPU), an application processor (AP), or a graphics card). In some embodiments, the input image data IDAT may be RGB image data including red image data, green image data and blue image data. In some embodiments, the control signal CTRL may include, but is not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a master clock signal, etc. The controller 1090 may generate the output image data ODAT, the data control signal DCTRL, the gate control signal GCTRL and the emission control signal ECTRL based on the input image data IDAT and the control signal CTRL. The controller 1090 may control an operation of the data driver 1030 by providing the output image data ODAT and the data control signal DCTRL to the data driver 1030, may control an operation of the gate driver 1050 by providing the gate control signal GCTRL to the gate driver 1050, and may control and operation of the emission driver 1070 by providing the emission control signal ECTRL to the emission driver 1070.
The display device 1000 according to embodiments may perform a multi-frequency driving (MFD) operation that drives a plurality of panel regions of the display panel 1010 at different driving frequencies. Further, in the display device 1000 according to embodiments, to perform the MFD operation, at least one of the gate driver 1050 and the emission driver 1070 may be implemented as the driver 100 of
For example, as illustrated in
For example, in a case where the gate driver 1050 includes the stage 200a of
In another example, in a case where the gate driver 1050 includes the stage 200c of
As described above, the gate driver 1050 and/or the emission driver 1070 according to embodiments may selectively output the gate signals GS and/or the emission signals in response to the output enable signal OUT_EN. Accordingly, the gate driver 1050 and/or the emission driver 1070 according to embodiments may be suitable for the display device 1000 that performs the MFD operation.
Referring to
The processor 1110 may perform various computing functions or tasks. The processor 1110 may be an application processor (AP), a micro-processor, a central processing unit (CPU), etc. The processor 1110 may be connected to other components via an address bus, a control bus, a data bus, etc. Further, in some embodiments, the processor 1110 may be further connected to an extended bus such as a peripheral component interconnection (PCI) bus.
The memory device 1120 may store data for operations of the electronic device 1100. For example, the memory device 1120 may include at least one non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistance random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc., and/or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile dynamic random access memory (mobile DRAM) device, etc.
The storage device 1130 may be a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. The I/O device 1140 may be an input device such as a keyboard, a keypad, a mouse, a touch screen, etc., and an output device such as a printer, a speaker, etc. The power supply 1150 may supply power for operations of the electronic device 1100. The display device 1160 may be connected to other components through the buses or other communication links.
In the display device 1160, at least one stage of a driver (e.g., a gate driver and/or an emission driver) may include both of a PMOS transistor and an NMOS transistor. Accordingly, a bootstrapping operation may not be desired or performed in the stage, and power consumption of the driver and the display device 1160 may be reduced. Further, at least one stage of the driver may selectively output an output signal in response to an output enable signal. Accordingly, the driver according to embodiments may be suitable for the display device 1160 that performs a multi-frequency driving (MFD) operation.
The inventive concepts may be applied to any display device 1160, and any electronic device 1100 including the display device 1160. For example, the inventive concepts may be applied to a smart phone, a wearable electronic device, a tablet computer, a mobile phone, a television (TV) (e.g., a digital TV, a 3D TV, etc.), a personal computer (PC), a home appliance, a laptop computer, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation device, etc.
The foregoing is illustrative of embodiments and is not to be construed as limiting thereof. Although a few embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the embodiments without materially departing from the novel teachings and advantages of the present inventive concept. Accordingly, all such modifications are intended to be included within the scope of the present inventive concept as defined in the claims. Therefore, it is to be understood that the foregoing is illustrative of various embodiments and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2024-0006644 | Jan 2024 | KR | national |
