Patent Application
20080191990
1. Field of the Invention
The present invention relates to a driver to which a display panel is connected. This patent application is based on Japanese Patent Application Nos. 2007-028723 and 2007-337633. Their disclosures are incorporated herein by reference.
2. Description of Related Art
A portable terminal such as a mobile phone and a PDA (Personal Digital Assistant) has widespread. A display apparatus with a driver and a display panel is provided for the portable terminal, and a LCD (Liquid Crystal Display) panel is generally adopted as the display panel.
The driver has a dedicated device for holding data, a program control circuit, and a memory for storing a display data. The program control circuit records a display quality specifying data in the dedicated device. The driver displays the display data stored in the memory on the display panel based on the display quality specifying data recorded in the dedicated device. Such a technique is disclosed in Japanese Patent Application Publications (JP-P2003-241730A, and JP-P2004-21067A: first and second conventional examples). In the first conventional example, EEPROM is exemplified as the dedicated device and in the second conventional example, a jumper switch circuit, EPROM, and EEPROM are exemplified as the dedicated device.
The driver sometimes includes a dedicated device used for other applications other than the dedicated device for holding display quality specifying data. In such a case that a plurality of program control circuits are associated with a plurality of dedicated devices, a circuit size of the driver as a whole increases due to the plurality of program control circuits.
In an aspect of the present invention, a driver includes a first memory including a plurality of memory cells and redundant memory cells. An address control circuit replaces a defective memory cell of the plurality of memory cells with one of the redundant memory cells based on a defect address data indicating an address of the defective memory cell. A driving circuit displays on a display panel, a display data stored in the first memory based on a display quality specifying data specifying display quality of the display panel. The display quality specifying data and the defect address data are stored in a second memory.
In another aspect of the present invention, a display apparatus includes the above-mentioned driver and a display panel connected with the driver.
In another aspect of the present invention, a display method of displaying a display data stored in a first memory on a display panel by using a driver which comprises memory cells and redundant memory cells is provide. The display method includes storing a display quality specifying data and a defect address data indicating an address of a defective one of the memory cells, in a second memory; replacing the defective memory cell with one of the redundant memory cells based on the defect address data; and displaying the display data on the display panel based on the display quality specifying data.
The above and other objects, advantages and features of the present invention will be more apparent from the following description of certain embodiments taken in conjunction with the accompanying drawings, in which:
Hereinafter, a driver according to embodiments of the present invention will be described in detail with reference to the attached drawings.
The driver 1 includes a memory 10, an address control circuit 20, a driving circuit 30, an interface (IF) buffer circuit 40, a program control circuit 50, and a nonvolatile memory 60.
The IF buffer circuit 40 is an interface connected to the memory 10, the address control circuit 20, the program control circuit 50, and an external unit.
The memory 10 includes memory cells 11 and redundant memory cells 12-1 to 12-n (n is an integer of “1” or more), which are arranged on a matrix. Here, the redundant memory cell may be single. As the memory, DRAM (Dynamic Random Access The memory) and SRAM (Static Random Access The memory) are exemplified.
The nonvolatile memory 60 has a display quality specifying data storage section 61 and a defect address data storage section 62. The display quality specifying data storage section 61 includes storage areas 61-1 to 61-m (m is an integer of “1” or more) and the defect address data storage section 62 includes storage areas 62-1 to 62-n. The storage areas 62-1 to 62-n of the defect address data storage section 62 correspond to the storage areas 61-1 to 61-n of the redundant memory cells 12-1 to 12-n.
The program control circuit 50 operates in synchronization with a clock signal (in this case, an internal clock signal). For example, a display quality specifying data W1 that specifies display quality of the display panel 100 is given from an external unit to the program control circuit 50 through the IF buffer circuit 40. In this case, the program control circuit 50 records the display quality specifying data W1 in a storage area 61-i (i is an integer satisfying 1≦i≦m) of the display quality specifying data storage section 61 of the nonvolatile memory 60. For example, it is supposed that each of the memory cells 11 is tested and at least one memory cell among the memory cells 11 is defective. In this case, a defect address data W2 showing the address of the defective memory cell is given from the external unit to the program control circuit 50 through the IF buffer circuit 40. At this time, the program control circuit 50 records the defect address data W2 in a storage area 62-j (j is an integer satisfying 1≦j≦n) of the defect address data storage section 62 of the nonvolatile memory 60. In this way, the display quality specifying data W1 and the defect address data W2 are recorded by using a same storage method.
The address control circuit 20 operates in synchronization with the internal clock signal. The address control circuit 20 replaces defective memory cells 11 with redundant memory cells 12-j based on the defect address data W2 recorded in the storage areas 62-j of the defect address data storage section 62. A display data DA is stored in the memory 10 from the external unit through the IF buffer circuit 40, and an address ADD for displaying one display line on the display panel 100 is given from the external unit to the address control circuit 20 through the IF buffer circuit 40. In this case, the address control circuit 20 outputs display data DL of the display data DA stored in the memory 10, which corresponds to one display line, to the driving circuit 30.
The driving circuit 30 operates in synchronization with the internal clock signal, and has a source driver and a gate driver. The driving circuit 30 displays the display data DL on the display panel 100 based on the display quality specifying data W1 recorded in the display quality specifying data storage section 61.
The nonvolatile memory 60 is either of a flash memory, EPROM, or EEPROM. As shown in
The display quality specifying data W1 is given from the external unit to the program control circuit 50 through the IF buffer circuit 40 (Step S1—YES). In this case, the program control circuit 50 selects a n empty one 61-i of the storage areas of the display quality specifying data storage section 61 of the nonvolatile memory 60 and records the display quality specifying data W1 in the selected storage area 61-i (Step S2). As the display quality specifying data W1, data about fine control of display contrast is exemplified. For example, when the display quality specifying data W1 is a data about adjustment of a counter electrode signal VCOM, the data is recorded in the storage area 61-1 of the display quality specifying data storage section 61. When the display quality specifying data W1 is a data about adjustment of a setup value of an LCD driving voltage, the data is recorded in the storage area 61-2 of the display quality specifying data storage section 61. By providing m display quality specifying data storage areas 61-1 to 61-m, m display quality specifying data W1 can be recorded in the display quality specifying data storage areas 61-1 to 61-m, respectively.
As a test result of each of the plurality of memory cells 11, the defect address data W2 designating the address of a defective one of the memory cells 11 is given from the external unit to the program control circuit 50 through the IF buffer circuit 40 (Step S3—YES). In this case, the program control circuit 50 selects an empty one 62-j of the storage areas of the defect address data storage section 62 of the nonvolatile memory 60 and records the defect address data W2 in the selected area 62-j (Step S4). Since the areas 62-1 to 62-n of the defect address data storage section 62 correspond to the redundant memory cells 12-1 to 12-n, respectively, n defect address data W2 can be recorded in the defect address data storage areas 62-1 to 62-n.
It should be noted that a pair of the steps S1 and S2 and a pair of the steps S3 and S4 are in no particular order.
As described above, the driver 1 according to the first embodiment of the present invention records the display quality specifying data W1 and the defect address data W2 by using the same storage method by the program control circuit 50. This eliminates the necessity of separately fabricating a dedicated device for recording the display quality specifying data W1 and a dedicated device for recording the defect address data W2. Moreover, if the dedicated devices are fabricated separately, circuit scale of the program control circuit 50 becomes large. However, in the present embodiment, because there is no necessity to separately fabricate the dedicated devices, a function of recording the display quality specifying data W1 and a function of recording the defect address data W2 can be made common by the program control circuit 50. As such, the circuit scale of the program control circuit 50 can be reduced, and the circuit scale of the whole driver 1 can also be reduced.
Moreover, the driver 1 of the present invention adopts a flash memory functioning as the nonvolatile memory 60, whose programming method does not adopt laser trimming fuses. When the laser trimming fuse is adopted, it is necessary to provide an opening window for allowing a laser beam to be irradiated on the laser trimming fuse in the driver 1. In such a case, there is a possibility that dust enters in the driver 1 from the outside through the opening window, depending on the mounting process. If dust has accidentally entered, it raises the possibility of causing a short-circuit in the driver 1 during operations after the mounting. On the other hand, when the flash memory is adopted, it is unnecessary to provide the opening window for the driver 1. Moreover, in the flash memory, the display quality specifying data W1 and the defect address data W2 can be recorded by sending the data into the driver 1, not by irradiating the laser light in the driver 1. Therefore, it is possible to program the display device 1 after the mounting.
Moreover, in the driver 1 according to the present embodiment, when the memory 10 is a DRAM as an application of a program for the memory 10, it is possible to relieve the defective memory cell due to degradation of a cell hold property after the mounting.
In the driver according to a second embodiment of the present invention, duplicate description with that in the first embodiment would be omitted.
As shown in
The display quality specifying data W1 is given from the external unit to the program control circuit 50 through the IF buffer circuit 40 (Step S1—YES). In this case, the program control circuit 50 supplies current to the electrical fuses to be cut off among the group of electrical fuses F1 to FN in the storage area 61-i of the display quality specifying data storage section 61 of the nonvolatile memory 60, to record the display quality specifying data W1 in the storage area 61-i (Step S2). For example, it is supposed that N is 12 and the electrical fuses to be cut off are F9 to F11. In this case, each of the electrical fuses F1 to F8 being not cut off represents “0,” and each of the cut-off electrical fuses F9 to F11 represents “1.” Thus, the program control circuit 50 records the display quality specifying data W1 in the group of electrical fuses F1 to FN in the storage area 61-i.
As a test result of each of the plurality of memory cells 11, the defect address data W2 designating the address of the defective one of the plurality of memory cells 11 is given from the external unit to the program control circuit 50 through the IF buffer circuit 40 (Step S3—YES). In this case, the program control circuit 50 supplies current to the electrical fuses to be cut off among the group of electrical fuses F1 to FN in the storage area 62-j of the defect address data storage section 62 of the nonvolatile memory 60, to record the defect address data W2 in the storage area 62-j (Step S4). For example, it is supposed that N is 12 and the electrical fuses to be cut off are F9 to F11. In this case, each of the electrical fuses F1 to F8 being not cut off represents “0,” and each of the cut-off electrical fuses F9 to F11 represents “1.” Since the storage areas 62-1 to 62-n of the defect address data storage section 62 respectively correspond to the redundant memory cells 12-1 to 12-n, n defect address data W2 can be recorded in the defect address data storage areas 62-1 to 62-n.
As described above, the driver 1 of the present invention adopts the groups of electrical fuses F1 to FN as one storage area of the nonvolatile memory 60, whose programming method does not adopt laser trimming fuses. If the laser trimming fuse is adopted, it is necessary to provide an opening window for allowing the laser light to be irradiated on the laser trimming fuse for the driver 1. In this case, there is a possibility that dust enters in the driver 1 from the outside through the opening window, depending on the mounting process. If the dust has accidentally entered, it raises the possibility of causing a short-circuit in the driver 1 during operations after the mounting. On the other hand, in the group of electrical fuses F1 to FN, it is unnecessary to provide the opening window in the driver 1. Moreover, the display quality specifying data W1 and the defect address data W2 can be recorded by sending data into the driver 1 and cutting the electrical fuses that correspond to the data, not by irradiating the laser light in the driver 1. Therefore, it is possible to program the driver 1 after the mounting.
In the driver according to a third embodiment of the present invention, duplicate description with those of the first and second embodiments would be omitted.
In the driver 1 according to a fourth embodiment of the present invention, duplicate description with those of the first to third embodiments would be omitted.
The power-on monitoring circuit 80 monitors the power source 200 (Step S21). When power supply voltage V is supplied from the power source 200 to the driver 1 (step S21—YES), the power-on monitoring circuit 80 outputs a power-on signal PON to the BIST circuit 70 (Step S22). At this time, the steps S11 to S14 described above are executed. That is, in response to the power-on signal PON, the BIST circuit 70 tests each of the plurality of memory cells 11 (Step S11), and outputs the defect address data W2 designating the address of the defective memory cell to the program control circuit 50 (Step S13). The program control circuit 50 records the defect address data W2 in an empty storage area 62-j of the storage areas of the defect address data storage section 62 of the nonvolatile memory 60 (Step S14). In this way, the driver 1 according to the fourth embodiment of the present invention can realize a self restoring function in a final product by combining a power-on self-test and the operations, as an application of the program for the memory 10.
In a fifth embodiment of the present invention, duplicate description with those of the first to fourth embodiments would be omitted.
The display quality represented by the display quality specifying data W1 can be altered by the user operating the input unit 300. At this time, what is required is that the user records the display quality specifying data W1 in the display quality specifying data storage section 61 of the nonvolatile memory 60. However, it is undesirable that the user records it erroneously in the defect address data storage section 62 of the nonvolatile memory 60. Moreover, a case is more undesirable that the display quality specifying data storage section 61 and the defect address data storage section 62 are each made up of the group of electrical fuses F1 to FN (current fusing type fuses), and the display quality specifying data W1 is erroneously recorded in the defect address data storage section 62.
From the above situation, in the fifth embodiment, the user is given an access right to the display quality specifying data storage section 61, but is not given the access right to the defect address data storage section 62. In this case, the program control circuit 50 holds the access right command W1CMD showing the access right to the display quality specifying data storage section 61. An operation related to this will be described.
In the description of a sixth embodiment of the present invention, duplicate description with those of the first to fifth embodiments would be omitted.
Moreover, the driver 1 is further provided with a power-on monitoring circuit 80. The power-on monitoring circuit 80 monitors whether or not the power supply voltage V was supplied from a power source 200 to the driver 1.
The nonvolatile memory 60 represents OTP {One Time PROM (Programmable Read Only The memory)}. The nonvolatile memory 60 includes a plurality of banks 60-1 to 60-4 which are used in this order, and a sense amplifier circuit 63. When this nonvolatile memory 60 is fabricated as a memory chip, the plurality of banks 60-1 to 60-4 and the sense amplifier circuit 63 are fabricated onto an identical memory chip. Here, one of the plurality of banks 60-1 to 60-4, for example, the bank 60-1 is supposed to be valid.
Each of the plurality of banks 60-1 to 60-4 has the storage section of 16×32 bits. The storage section of 16×32 bits is divided into the defect address data storage section 62 of the display quality specifying data storage section 61 of 16×30 bits and the defect address data storage section 62 of 16×2 bits. That is, the display quality specifying data storage section 61 and the defect address data storage section 62 share the sense amplifier circuit 63. The display quality specifying data storage section 61 of 16×30 bits contains a first display quality specifying data storage section 611 of 16×28 bits and a second display quality specifying data storage section 612 of 16×2 bits. For example, the first display quality specifying data storage section w1-1 has 28 storage areas and the second display quality specifying data storage section w1-2 has 2 storage areas. Also, the defect address data storage section 62 of 16×2 bits has 2 storage areas.
The above-mentioned display quality specifying data W1 contains the first display quality specifying data W1-1 of a panel maker who manufactures the display panel 100 and the second display quality specifying data W1-2 of a display device maker who manufactures the driver 1. Therefore, the first display quality specifying data W1-1 is recorded to the first display quality specifying data storage section 611 of the bank 60-1, and the second display quality specifying data W1-2 is recorded to the second display quality specifying data storage section 612 of the bank 60-1. Also, the above-mentioned defect address data W2 is recorded to the defect address data storage section 62 of the bank 60-1.
The program control circuit 50 includes sequencers 51 and 52, a R/W (reed/write) control section 53, a command decoder 54, an OTP logic circuit 55, a panel/display device register 56 and a defect address register 57. The panel/display device register 56 contains a panel register 56-1 and a display device register 56-2. When the power supply voltage V is supplied from the power source 200 to the driver 1, the sequencer 51 outputs a read signal to read the first display quality specifying data W1-1, the second display quality specifying data W1-2, and the defect address data W2 from the first display quality specifying data storage section 611, the second display quality specifying data storage section 612, and the defect address data storage section 62 of the bank 60-1. The sequencer 52 outputs a signal to additionally write customer data (data of the panel maker). However, since the sequencer 52 is not directly related to the present invention, the detailed description of the sequencer 52 is omitted. The R/W control section 53 outputs control signals (read signal, and write signal) to a read instruction, and a write instruction, respectively. The command decoder 54 decodes the inputted read instruction and the write instruction. The OTP logic circuit 55 converts the signals from the sequencers 51 and 52, and the R/W control section 53 into signals suitable for the nonvolatile memory (OTP) 60.
As shown in
The memory 10 is composed of SRAM (Static Random Access Memory). In this case, when the power supply voltage V is supplied from the power source 200 to the driver 1, the addresses of defective ones of the memory cells 11 in the memory 10 must be replaced with the addresses of the redundant memory cells 12 based on the defect address data W2. Therefore, as shown in
The power-on monitoring circuit 80 monitors the power source 200 (Step S41). When the power supply voltage V is supplied to the driver 1 from the power source 200 (Step S41-YES), the power-on monitoring circuit 80 outputs a power-on signal PON to the sequencer 51 (Step S42). The sequencer 51 outputs first to third read signals to the nonvolatile memory 60 through the OTP logic circuit 55 in response to the power-on signal PON for reading out the first display quality specifying data W1-1, the second display quality specifying data W1-2, and the defect address data W2 from the first and second display quality specifying data storage sections 611 and 612, and the defect address data storage section 62 in the bank 60-1 (Step S43).
The sense amplifier circuit 63 reads out the first and second display quality specifying data W1-1 and W1-2 and the defect address data W2 from the first and second display quality specifying data storage sections 611 and 612, and the defect address data storage section 62 in the bank 60-1 in response to the first to third read signals, respectively (Step S44). The sense amplifier circuit 63 stores the first and second display quality specifying data W1-1 and W1-2 and the defect address data W2 in the panel register 56-1, the display device register 56-2 and the defect address register 57 (Step S45).
The defect address register 57 is referred to by the address control circuit 20. That is, the address control circuit 20 replaces a defective memory cell of the plurality of memory cell 11 with a redundant memory cell 12 based on the defect address data W2 recorded in the defect address data storage section 62. The address control circuit 20 receives display data DL for one display line from the display data DA stored the memory 10 and outputs it to the driving circuit 30.
The panel register 56-1 and the display device register 56-2 are referred to by the driving circuit 30. That is, the driving circuit 30 displays the display data DL on display panel 100 based on the first and second display quality specifying data W1-1 and W1-2 set in the panel register 56-1 and the display device register 56-2.
In this way, according to the driver 1 in the sixth embodiment of the present invention, when the power supply voltage V is supplied to the driver 1 from the power source 200, the driver 1 can automatically read out the first display quality specifying data W1-1, the second display quality specifying data W1-2 and the defect address data W2 from the first display quality specifying data storage section 611, the second display quality specifying data storage section 612, and the defect address data storage section 62 in the bank 60-1.
In the description of the seventh embodiment, duplicate description with the above-mentioned first to sixth embodiments is omitted.
In the seventh embodiment, the panel maker, the display device maker, and the memory device maker perform tests using testers to carry out image adjustment, image/circuit adjustment, and circuit (memory 10) adjustment, respectively. In this case, as shown in
As described above, the panel maker, the display device maker, the memory device maker use testers at the time of the test, respectively. To distinguish the testers used by the panel maker, the display device maker, the memory device maker, respectively, they are referred to first to third testers 91 to 93. The panel maker, the display device maker, the memory device maker input first to third write instructions from the testers 91 to 93 to the command decoder 54 of program control circuit 50 through the IF buffer circuit 40 (Step S51). The first to third write instructions contain the first and second display quality specifying data W1-1 and W1-2 and the defect address data W2 and addresses of the first and second display quality specifying data storage sections 611 and 612, and an address of the defect address data storage section 62 in the bank 60-1.
The command decoder 54 decodes the first to third write instructions (Step S52). The control section 53 writes the first and second display quality specifying data W1-1 and W1-2 and the defect address data W2 in the first and second display quality specifying data storage sections 612 and 612, and the defect address data storage section 62 in the bank 60-1 through the OTP logic circuit in response to the first to third write instructions decoded by the command decoder 54 (Step S53).
The panel maker, the display device maker, and the memory device maker receive the first to third read instructions from the testers 91 to 93 by the command decoder 54 of the program control circuit 50 through the IF buffer circuit 40 (Step S61). The first to third read instructions contains the first and second display quality specifying data W1-1 and W1-2 and the defect address data W2 together with addresses of the first and second display quality specifying data storage sections 611 and 612, and the defect address data storage section 62 in the bank 60-1.
The command decoder 54 decodes the first to third read instructions (Step S62). The control section 53 outputs first to third read signals to the nonvolatile memory 60 through the OTP logic circuit in response to the first to third read instructions decoded by the command decoder 54 (Step S63). The sense amplifier circuit 63 outputs the first and second display quality specifying data W1-1 and W1-2 and the defect address data W2 read out from the first and second display quality specifying data storage sections 611 and 612 and the defect address data storage section 62 in the bank 60-1 in response to the first to third read signals (Step S64). The sense amplifier circuit 63 stores the first and second display quality specifying data W1-1 and W1-2 and the defect address data W2 in the panel register 56-1, the display device register 56-2 and the defect address register 57, respectively (Step S65).
The defect address register 57 is referred to by the address control circuit 20. That is, the address control circuit 20 replaces a defective memory cell of the plurality of memory cells 11 with a redundant memory cell 12 based on the defect address data W2 set to the defect address data storage section 62, like the usual redundant operation. The address control circuit 20 outputs display data DL for one display line to the driving circuit 30 from the display data DA stored in the memory 10. The panel register 56-1 and the display device register 56-2 are referred to by the driving circuit 30. That is, the driving circuit 30 displays the display data DL on the display panel 100 based on the first and second display quality specifying data W1-1 and W1-2 set in the panel register 56-1 and the display device register 56-2.
In this way, according to the driver 1 according to the seventh embodiment of the present invention, the panel maker, the display device maker, and the memory device maker can check whether the first display quality specifying data W1-1, the second display quality specifying data W1-2, and the defect address data W2 are written in the first display quality specifying data storage section 611, the second display quality specifying data storage section 612, and the defect address data storage section 62 in the bank 60-1 at the time of the tests, respectively. Also, the panel maker, the display device maker, the memory device maker can check whether the first display quality specifying data W1-1, the second display quality specifying data W1-2, and the defect address data W2 are read out from the first display quality specifying data storage section 611, the second display quality specifying data storage section 612, and the defect address data storage section 62 in the bank 60-1 at the time of the tests, respectively.
In the description of the eighth embodiment, duplicate description with the above-mentioned first to seventh embodiments will be omitted.
In the above-mentioned seventh embodiment, the panel maker, the display device maker, and the memory device maker read out the first display quality specifying data W1-1, the second display quality specifying data W1-2 and the defect address data W2 from the first display quality specifying data storage section 611, the second display quality specifying data storage section 612, and the defect address data storage section 62 in the bank 60-1 at the time of the tests, respectively.
On the other hand, in the eighth embodiment, as shown in
The panel maker, the display device maker, and the memory device maker input first to third register read instructions to the command decoder 54 in the program control circuit 50 through the IF buffer circuit 40 from the testers 91 to 93, respectively (Step S71). The first to third register read instructions contain the addresses of the panel register 56-1, the display device register 56-2 and the defect address register 57, respectively.
The command decoder 54 decodes the first to third register read instructions (Step S72). The control section 53 reads the first and second display quality specifying data W1-1 and W1-2 and the defect address data W2 from the panel register 56-1, the display device register 56-2 and the defect address register 57 in response to the first to third register read instructions decoded by the command decoder 54, respectively. The control section 53 outputs the first and second display quality specifying data W1-1 and W1-2 and the defect address data W2 to the testers 91 to 93, respectively (Step S73).
In this way, according to the driver 1 by the 8th embodiment of the present invention, the panel maker, the display device maker, and the memory device maker can check whether the first display quality specifying data W1-1, the second display quality specifying data W1-2, and the defect address data W2 read out from the first display quality specifying data storage section 611, the second display quality specifying data storage section 612, and the defect address data storage section 62 in the bank 60-1 have been set in the panel register 56-1, the display device register 56-2 and the defect address register 57, at the time of the tests, respectively.
In the description of the ninth embodiment, duplicate description with those of the first to eighth embodiments will be omitted.
In the above-mentioned sixth to eighth embodiments, it is sometimes desired to erase the data of the bank 60-1 of the plurality of banks 60-1 to 60-4 in the nonvolatile memory 60. However, when the nonvolatile memory 60 is OTP, it is not possible to erase electrically. In the ninth embodiment, the panel maker changes between the bank 60-1 and the bank 60-2 and uses the bank 60-2 instead of the bank 60-1 for the erasure of the data of the bank 60-1 at the time of the test.
The panel maker inputs an erase instruction to the command decoder 54 of the program control circuit 50 through IF buffer circuit 40 from tester 91 to erase the data of the bank 60-1 valid at present (Step S81). The command decoder 54 decodes the erase instruction (Step S82). The control section 53 makes the bank 60-1 invalid and then makes the bank 60-2 in the plurality of banks 60-1 to 60-4 valid, in response to the erase instruction decoded by the command decoder 54. That is, the valid bank is switched from the bank 60-1 to the bank 60-2 (Step S83). Thus, the first and second display quality specifying data W1-1 and W1-2 and the defect address data W2 can be recorded in the first and second display quality specifying data storage sections 611 and 612, and the defect address data storage section 62 in the bank 60-2.
In this way, when the panel maker inputs the erase instruction for the first time by using the tester 91, the bank 60-1 is made invalid and then the bank 60-2 is made valid. In the same way, when the panel maker inputs the erase instruction for the second time by using the tester 91, the bank 60-2 is made invalid and then the bank 60-3 is made valid. In the same way, when the panel maker inputs the erase instruction for the third time by using the tester 91, the bank 60-3 is made invalid and then the bank 60-4 is made valid. In the driver 1 according to the ninth embodiment of the present invention, the number of banks is 4 and the bank is erasable three times. However, the present invention is not limited to this. By increasing the number of banks, the number of times of the erase operation can be increased.
According to the driver 1 according to the ninth embodiment of the present invention, when the nonvolatile memory 60 is OTP, the panel maker can use the substitution of the bank for the erase operation of the bank at the time of the test.
Although the present invention has been described above in connection with several embodiments thereof, it would be apparent to those skilled in the art that those embodiments are provided solely for illustrating the present invention, and should not be relied upon to construe the appended claims in a limiting sense.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2007-028723 | Feb 2007 | JP | national |
| 2007-337633 | Dec 2007 | JP | national |
