Patent Application
20230048669
This application claims priority to Chinese Patent Applications No. 202011206657.5 filed with the China National Intellectual Property Administration (CNIPA) on Nov. 3, 2020, the disclosure of which is incorporated herein by reference in its entirety.
Embodiments of the present application relate to the field of display technologies, for example, a driver chip, a display screen, and a display device.
A silicon-based display is a combination of a display and a monocrystalline silicon integrated circuit. An obvious feature of the silicon-based display is that pixels in the display are formed on a silicon-based substrate through a complementary metal-oxide-semiconductor (CMOS) process, so that the silicon-based display has characteristics such as a relatively low cost and a relatively small volume.
The silicon-based display generally includes a display screen and a driver chip. The driver chip may drive pixels in the display screen for display. In a conventional process, the driver chip and the display screen are formed on a same silicon-based substrate. However, with development of the display technologies, a display effect of the silicon-based display is continuously improved, so that the driver chip needs to be manufactured by a high-order process. The pixels in the display are manufactured simply by a low-order process. If the display and the driver chip are still formed on the same silicon-based substrate, a manufacturing cost of the silicon-based display is undoubtedly increased. Therefore, how to reduce the manufacturing cost of the silicon-based display and improve a product yield of the silicon-based display under a premise that the silicon-based display may have a high-quality display effect becomes an urgent technical problem to be solved.
Embodiments of the present application provide a driver chip, a display screen, and a display device so as to reduce a manufacturing cost of a silicon-based display and improve a product yield of the silicon-based display.
In a first aspect, the driver chip provided by the embodiments of the present application is configured to drive a silicon-based display screen. The silicon-based display screen includes pixels arranged in M rows and N columns. M and N are each a positive integer.
The driver chip includes a bridge chip and a screen driver chip. The bridge chip includes a first substrate and a first signal processing circuit disposed on one side of the first substrate. The first signal processing circuit includes a signal interface circuit and a drive controller. The screen driver chip includes a second substrate and a second signal processing circuit disposed on one side of the second substrate. The second signal processing circuit includes a signal processor and a data processing circuit.
The signal interface circuit is configured to receive video signals of each frame of picture.
The drive controller is electrically connected to the signal processor. The drive controller is configured to control video signals of P pixels among the video signals of one frame of picture to be output at a first preset transmission speed to the signal processor each time. P is a positive integer, and P<N.
The signal processor is electrically connected to the data processing circuit. The signal processor is configured to convert the video signals of the P pixels into data drive signals and output at a second preset transmission speed data drive signals of Q pixels in the one frame of picture to the data processing circuit each time. Q is a positive integer, and Q≤N.
The data processing circuit is configured to convert the data drive signals into display driving signals, sequentially output the display driving signals to pixels in each row, and control each of the pixels for display.
In a second aspect, the display screen further provided by the embodiments of the present application includes the driver chip.
The second substrate of the screen driver chip includes a display area and a non-display area surrounding the display area. The pixels are configured in the display area, and the second signal processing circuit is configured in the non-display area.
In a third aspect, the display device provided by the embodiments of the present application further includes the display screen.
The embodiments of the present application provide the driver chip, the display screen, and the display device. The driver chip includes the bridge chip and the screen driver chip. The first signal processing circuit having a relatively high transmission speed is disposed on the first substrate of the bridge chip. The second signal processing circuit having a low transmission speed requirement is disposed on the second substrate of the screen driver chip. Therefore, the first signal processing circuit and the second signal processing circuit are formed by using different substrates in different processes, so that the bridge chip may be manufactured by using a high-order process, and the screen driver chip may be manufactured by using a low-order process, thereby being conducive to reducing a manufacturing cost of the driver chip. Meanwhile, the video signals received by the signal interface circuit of the first signal processing circuit in the bridge chip may be output by the drive controller of the first signal processing circuit. The drive controller may control the number of video signals output to the second signal processing circuit in the screen driver chip each time. In such way, if the drive controller of the first signal processing circuit in the bridge chip controls the number of video signals output to the second signal processing circuit to be relatively small each time, the number of signal lines and/or connection terminals electrically connecting the bridge chip and the screen driver chip is relatively small, which is conducive to reducing a risk that the bridge chip cannot transmit the video signals to the screen driver chip due to poor contact of the signal lines and/or the connection terminals, thereby being conducive to improving the accuracy of signal transmission and a production yield of the driver chip.
As shown in
However, when the driver chip 020 and the pixels 010 in the silicon-based display screen are manufactured using different substrates, respectively, the driver chip 020 needs to be electrically connected to the pixels 010 in the silicon-based display screen through corresponding connection terminals and/or signal lines so as to transmit corresponding data drive signals to the pixels 010 and drive the pixels 010 for display. In such way, the connection terminals need to be configured both on a substrate side on which a driver chip is disposed and a substrate side on which the pixels of the silicon-based display screen is disposed, the number of the connection terminals is equivalent to the number of pixels 010 in each row, and/or the signal lines need to be configured between the substrate on which the driver chip is disposed and the substrate on which the pixels of the silicon-based display screen are disposed, and the number of the signal lines is equivalent to the number of pixels 010 in each row. When the number of pixels 010 in each row is relatively large, a relatively large number of signal lines and/or connection terminals need to be disposed. When a yield of the signal lines and the connection terminals is constant, the more the signal lines and/or the connection terminals are disposed, the more unfavorable it is to improve the production yield of the silicon-based display screen, thereby increasing the manufacturing cost of the silicon-based display screen and reducing a display effect of the silicon-based display screen.
To solve above technical problems, an embodiment of the present application provides a driver chip. The driver chip is configured to drive a silicon-based display screen, and the silicon-based display screen includes pixels arranged in M rows and N columns. M and N are each a positive integer. The driver chip includes a bridge chip and a screen driver chip. The bridge chip includes a first substrate and a first signal processing circuit disposed on one side of the first substrate. The first signal processing circuit includes a signal interface circuit and a drive controller. The screen driver chip includes a second substrate and a second signal processing circuit disposed on one side of the second substrate. The second signal processing circuit includes a signal processor and a data processing circuit. The signal interface circuit is configured to receive video signals of each frame of picture. The drive controller is electrically connected to the signal processor. The drive controller is configured to control video signals of P pixels among the video signals of one frame of picture to be output at a first preset transmission speed to the signal processor each time. P is a positive integer, and P<N. The signal processor is electrically connected to the data processing circuit. The signal processor is configured to convert the video signals of the pixels into data drive signals and output at a second preset transmission speed data drive signals of Q pixels in one frame of picture to the data processing circuit each time. Q is a positive integer, and Q≤N. The data processing circuit is configured to convert the data drive signals into display driving signals, sequentially output the display driving signals to pixels in each row, and control each of the pixels for display.
The first signal processing circuit disposed on the first substrate in the bridge chip may decode, transmit, and perform other operations on the video signals received. Therefore, the first signal processing circuit needs to have a relatively high processing speed to meet the high display requirements of the silicon-based display screen. The second signal processing circuit disposed on the second substrate in the screen driver chip may perform storage, digital-to-analog conversion and other operations on signals output from the first signal processing circuit. Therefore, the second signal processing circuit does not need to have a relatively high processing speed.
As described above, according to above technical solutions, on the one hand, the first signal processing circuit and the second signal processing circuit are disposed on the first substrate and the second substrate, respectively, so that the first signal processing circuit formed on the first substrate and the second signal processing circuit formed on the second substrate may be manufactured by using different processes, and thus a high-order process is adopted for the first signal processing circuit with high requirements for manufacturing conditions, and a low-order process is adopted for the second signal processing circuit with low requirements for manufacturing conditions. Therefore, a production cost of the second signal processing circuit may be reduced, and the production yield of the second signal processing circuit may be increased, and thus an overall cost of the driver chip may be reduced, and the production yield of the driver chip may be increased. On the other hand, the driver chip is divided into the bridge chip and the screen driver chip. After the video signals of each frame of picture are received by the signal interface circuit of the first signal processing circuit in the bridge chip, the drive controller of the first signal processing circuit controls the number of video signals output to the second signal processing circuit of the screen driver chip each time, and the drive controller controls the number of video signals output to the signal processor of the second signal processing circuit each time to be smaller than the number of pixels in each row. Compared with a case where the signal processing circuit of the driver chip and the pixels of the silicon-based display screen are manufactured on different substrates, the embodiment of the present application merely uses the connection terminals and/or the signal lines, the number of which is equivalent to the number of video signals output each time, to achieve that the bridge chip and the screen driver chip may be electrically connected to each other, which is conducive to improving the production yield of the driver chip and reducing the production cost of the driver chip. Therefore, the production yield of the silicon-based display screen including the driver chip may be improved and the production cost of the silicon-based display screen including the driver chip may be reduced.
In the embodiment of the present application, the driver chip 100 includes a bridge chip 10 and a screen driver chip 20. The screen driver chip 20 is a chip provided with the pixels 230 of the silicon-based display screen and external circuits of the pixels 230. The bridge chip 10 includes a first substrate 110 and a first signal processing circuit 120 disposed on one side of the first substrate 110, and the screen driver chip 20 includes a second substrate 210 and a second signal processing circuit 220 disposed on one side of the second substrate 210. That is, the first signal processing circuit 120 of the bridge chip 10 and the second signal processing circuit 220 of the screen driver chip 20 are formed on different substrates, so that the first signal processing circuit 120 of the bridge chip 10 and the second signal processing circuit 220 of the screen driver chip 20 may be formed under different process conditions. Therefore, corresponding manufacturing processes may be selected according to respective performance requirements of the first signal processing circuit 120 and the second signal processing circuit 220.
The first signal processing circuit 120 includes at least a signal interface circuit 121 and a drive controller 122. The signal interface circuit 121 may receive the video signals of each frame of picture, and the video signals may drive the pixels 230 in the silicon-based display screen to display. When the signal interface circuit 121 receives the video signals of one frame of picture, the video signals of the frame of picture are usually high-speed serial analog signals. The signal interface circuit 121 converts the analog signals received into corresponding digital signals, and the digital signals are subjected to a high-speed processing process such as decompression through other modules of the first signal processing circuit 120 and output to the second signal processing circuit 220 through the drive controller 122 of the first signal processing circuit 120. The drive controller 122 of the first signal processing circuit 120 may control transmission speeds of the video signals of each frame of picture received by the signal interface circuit 121. That is, the video signals of each frame of picture may be output at the first preset transmission speed to the second signal processing circuit 220. When the transmission speed is relatively high, the number of pixels 230 corresponding to the video signals output each time is relatively small. Therefore, when the drive controller 122 outputs the video signals of each frame of picture at a relatively high first preset transmission speed, the drive controller 122 may output the video signals of P pixels 230 to a signal processor 221 of the second signal processing circuit 220 each time. P is a positive integer, and P<N. That is, the number of pixels 230 corresponding to the video signals output from the drive controller 122 each time is smaller than the number of pixels 230 in each row in the silicon-based display screen.
In this manner, when video signals of each frame of picture received by the signal interface circuit 121 are the high-speed serial analog signals, and the drive controller 122 outputs the video signals of each frame of picture at a relatively high speed, it is favorable to improve a refresh frequency, display brightness and the like of the silicon-based display screen. Meanwhile, when the first signal processing circuit 120 has a relatively high operational speed, the high-order process with relatively high production process conditions and relatively high accuracy requirements is needed to form the first signal processing circuit 120 on the first substrate 110, so that the bridge chip 10 may have a relatively high yield on a premise that the first signal processing circuit 120 formed on the side of the first substrate 110 has a relatively high operational speed bridge chip and thus the manufacturing cost of the bridge chip 10 may be reduced.
The second signal processing circuit 220 includes the signal processor 221 and a data processing circuit 222. The signal processor 221 is electrically connected to the drive controller 122 of the first signal processing circuit 120. The signal processor 221 receives the video signals output from the drive controller 122, converts the video signals received into the data drive signals, and then outputs the data drive signals of Q pixels at the second preset transmission speed to the data processing circuit 222 electrically connected to the signal processor 221. Q is a positive integer, and Q≤N. That is, the number of pixels 230 corresponding to the data drive signals output from the signal processor 221 each time may be smaller than the number of pixels 230 in each row or may be equal to the number of pixels 230 in each row, so that the signal processor 221 may output the data drive signals at a relatively low second preset transmission speed. In this case, the first preset transmission speed may be greater than the second preset transmission speed, and P<Q.
Exemplarily, when the drive controller 122 controls video signals of each frame of picture to be outputted in a form of video signals of thirty-two pixels at a frequency of 45 MHz each time, and the signal processor 221 outputs the data drive signals of sixty-four pixels at a frequency of 22.5 MHz each time, the signal processor 221 merely divides the received video signals of the thirty-two pixels each time into the data drive signals of the sixty-four pixels. That is, the video signals received by the signal processor 221 and the data drive signals output from the signal processor 221 are each the digital signals, and digital-to-analog conversion is not performed. After the signal processor 221 outputs the data drive signals to the data processing circuit 222, the data processing circuit 222 may perform digital-to-analog conversion on the received signals so as to convert the data drive signals into the display driving signals which may directly drive the pixels for display. Moreover, the display driving signals are sequentially provided for pixels in each row through corresponding data signal lines 34 so that the pixels may be displayed according to the display driving signals received by each pixel. According to this configuration, the number of pixels 230 corresponding to the data drive signals output from the signal processor 221 each time may be twice the number of pixels 230 corresponding to the video signals output from the drive controller 122 each time.
In this manner, the signal processor 221 and the data processing circuit 222 of the second signal processing circuit 220 do not need to have a relatively high computation and transmission speed. The signal processor 221 merely needs to divide the video signals received into a corresponding number of data drive signals, and the data processing circuit 222 converts the data drive signals into the display driving signals through the digital-to-analog conversion. Therefore, the second signal processing circuit 220 does not need to have a relatively high computational processing speed, and the second signal processing circuit 220 is formed on the second substrate 210 by simply using the low-order process with relatively low production process conditions and relatively low accuracy requirements so that the manufacturing cost of the screen driver chip 20 is reduced on a premise of ensuring a relatively high yield of the screen driver chip 20.
Exemplarily, the first substrate 110 and the second substrate 210 may each be a silicon-based substrate. The high-order process for forming the first signal processing circuit 120 on the first substrate 110 and the low-order process for forming the second signal processing circuit 220 on the second substrate 210 may each be a CMOS process, but specific formation conditions of the first signal processing circuit 120 and the second signal processing circuit 220 may vary according to respective performances. On the premises that the yields of the bridge chip 10 and the screen driver chip 20 may be improved, and the cost of the bridge chip 10 and the screen driver chip 20 may be reduced, the embodiment of the present application is not specifically limited to these.
In addition, the second signal processing circuit 220 in the screen driver chip 20 uses the low-order process, which is equivalent to the process used by the pixels 230 in the silicon-based display screen. Therefore, the second signal processing circuit 220 in the screen driver chip 20 and the pixels 230 in the silicon-based display screen are both formed on the second substrate 210 under same process conditions, thereby simplifying process steps of the silicon-based display screen and reducing the cost of the silicon-based display screen.
Further, the drive controller 122 of the first signal processing circuit 120 may be electrically connected to the signal processor 221 of the second signal processing circuit 220 through the signal lines and/or the connection terminals. Exemplarily, when the drive controller 122 is electrically connected to the signal processor 221 through the signal lines 31, each signal line 31 may serially output a corresponding number of video signals. That is, the number of signal lines 31 configured to electrically connect the drive controller 122 and the signal processor 221 should be equivalent to the number of pixels 230 corresponding to the video signals output from the drive controller 122 each time. When the drive controller 122 outputs the video signals of P pixels 230 at the first preset transmission speed each time, P signal lines 31 configured to transmit the video signals need to be disposed. The drive controller 122 of the first signal processing circuit 120 may control the number of pixels corresponding to the video signals output to the signal processor 221 of the second signal processing circuit 220 each time. Therefore, when the number of pixels corresponding to the video signals output at a relatively high first transmission speed from the drive controller 122 is relatively small, the number of signal lines 31 configured to electrically connect the drive controller 122 and the signal processor 221 and disposed between the bridge chip 10 and the screen driver chip 20 is relatively small. When the number of signal lines 31 disposed is relatively small, the process of manufacturing the signal lines 31 may be relatively simple, and a qualification rate of the signal lines 31 may be relatively high, which is conducive to improving the accuracy of the video signals output from the drive controller 122 to the signal processor 221, thereby improving the yield of the driver chip 100, reducing the cost and power consumption of the driver chip 100, and further reducing the power consumption and cost of the silicon-based display screen, and improving the display effect of the silicon-based display screen.
In the embodiment of the present application, the signal interface circuit 121 of the first signal processing circuit 120 is, for example, but not limited to, a physical layer (PHY) interface (e.g. PHY chip). A type of the signal interface circuit is not specifically limited by the embodiment of the present application on a premise that the signal interface circuit 121 may receive the high-speed serial analog signals.
Optionally,
The connector 301 configured to electrically connect the bridge chip 10 and the screen driver chip 20 may be provided with corresponding connection terminals, signal lines, and the like. When the drive controller 122 of the first signal processing circuit 120 controls the number of pixels corresponding to the video signals output each time to be relatively small, the connector 301 may be provided with a relatively smaller number of connection terminals and signal lines. In this manner, the design of the connector 301 may be simplified, which is conducive to improving the product yield of the connector 301 and reducing the manufacturing cost of the connector 301. Accordingly, the video signals of each frame of picture generated by the system motherboard may be transmitted to the bridge chip 10 through the connector 302 and received by the signal interface circuit 121 of the bridge chip 10. Exemplarily, the connectors 301 and 302 may include, but are not limited to, a printed circuit board or a flexible circuit board.
Optionally,
The digital signal decoder 123 may decode the video signals of each frame of picture received by the signal interface circuit 121 into eight-bit RGB signals or digital signals of another format (Mobile Industry Processor Interface (MIPI), High Definition Multimedia Interface (HDMI), Video Graphics Array (VGA), NTSC (National Television System Committee), Society of Motion Picture and Television Engineers (SMPTE), or the like), output the decoded video signals at the third preset transmission speed greater than the second preset transmission speed and less than or equal to the first preset transmission speed, and output the video signals of K pixels each time. In this manner, the digital signal decoder 123 needs to have a relatively high decoding speed so that when the higher-order process is used to manufacture the first signal processing circuit 120, requirements on decoding speed of the digital signal decoder 123 may be met, and meanwhile the bridge chip 10 may be ensured to have relatively low power consumption.
Optionally, with continued reference to
The signal correction circuit 124 may include a gamma correction circuit 1241, a saturation and grayscale processing circuit 1242, and a border pixel compensation circuit 1243 which are sequentially electrically connected. In this manner, the gamma correction circuit 1241 may be used to perform gamma correction on the video signals decoded by the digital signal decoder 123 so as to make the displayed picture have a relatively high contrast. The saturation and grayscale processing circuit 1242 is used to perform a biasing adjustment on the video signals having subjected to the gamma correction so as to form final brightness signals input to each pixel unit so that the displayed picture may have relatively high display brightness and the display effect may be improved. In addition, the silicon-based display screen includes not only the pixels for normal display but also virtual pixels disposed at a bezel position. Therefore, the border pixel compensation circuit 1243 is needed to provide the video signals of the virtual pixels disposed at the bezel position so that the display driving signals finally output may be in one-to-one correspondence with the pixels in the silicon-based display screen to improve the display effect of the silicon-based display screen.
Optionally,
The drive controller 122 of the first signal processing circuit 120 outputs the video signals of P pixels to the signal processor 221 of the second signal processing circuit 220 each time and meanwhile outputs the row synchronization signals and the data write control signals to the signal processor 221, so that the signal processor 221 may distinguish the video signals of each pixel 230 and each row of pixels 230 according to the row synchronization signals and the data write control signals and output the data drive signals of each row of pixels to the storage circuit 2221 for storage. Although the drive controller 122 merely outputs the video signals of P pixels each time, the video signals of the pixels may be distinguished by the row synchronization signals and the data write control signals output from the drive controller. Thus, P signal lines 31 for transmitting the video signals of P pixels, one signal line 321 for transmitting the row synchronization signals, one signal line 323 for transmitting the column synchronization signals and one signal line 322 for transmitting the data write control signals need to be configured between the bridge chip 10 and the screen driver chip 20. That is, (P×i×j+3) signal lines are configured between the bridge chip 10 and the screen driver chip 20, so that when the number of pixels corresponding to the video signals output from the drive controller 122 each time is relatively small, the number of signal lines configured to electrically connect the bridge chip 10 and the screen driver chip 20 may be reduced, thereby simplifying the design of the driver chip, ensuring the accuracy of signal transmission between circuits of the driver chip, reducing the power consumption, and improving the display effect. Where i denotes the number of sub-pixels included in each pixel, and j denotes the number of bytes of each video signal. For example, each pixel may include three sub-pixels. That is, i is equal to 3. Each video signal may have 8 bits, that is, j is equal to 8, which is merely taken as an example. On the premise that core application points of the embodiment of the present application may be achieved, the embodiment of the present application does not specifically limit values of i and j.
Meanwhile, after the storage circuit 2221 stores the data drive signals of one row of pixels, the signal processor 221 may output corresponding clock trigger signals to the storage circuit 2221 so that the storage circuit 2221 may simultaneously output the data drive signals of one row of pixels to the digital-to-analog conversion circuit 2222. The digital-to-analog conversion circuit 2222 may convert the data drive signals into the display driving signals that may directly drive the pixels 230, and output the display driving signals to pixels in each row 230 at the preset drive timing through the data driver 2223, so as to drive pixels in each row 230 to emit light and display each frame of picture.
Optionally,
Optionally, still referring to
Optionally, still referring to
The pixel mentioned in the embodiment of the present application may be a sub-pixel or a pixel circuit including a plurality of different sub-pixels, which is not specifically limited by the embodiment of the present application on the premise that the core application points of the embodiment of the present application can be achieved.
Optionally, with continued reference to
Exemplarily, each pixel 230 may include three sub-pixels 231, 232, and 233 of different colors, and the colors of the sub-pixels 231, 232, and 233 may include, for example, but not limited to, red, green, and blue. In this case, each multiplex gating circuit 240 may include three switching circuits 241, and each switching circuit 241 may include a transistor. In this manner, when the transistor of the switching circuit 241 is an N-channel metal-oxide semiconductor (NMOS) and signals transmitted by the clock signal line 35 electrically connected to the switching circuit 241 are at a high level, the transistor of the switching circuit 241 can be controlled to turn on so that the display driving signals output from the data processing circuit 222 can be transmitted through the transistor turned on to a corresponding column of sub-pixels. When the transistor of the switching circuit 241 is a P-channel metal-oxide semiconductor (PMOS) and the signals transmitted by the clock signal line 35 electrically connected to the switching circuit 241 are at a low level, the transistor of the switching circuit 241 can be controlled to turn on so that the display driving signals output from the data processing circuit 222 can be transmitted through the transistor turned on to a corresponding column of sub-pixels.
Correspondingly, a clock signal output terminal of the data processing circuit 222 is electrically connected to each of the clock signal lines 35. The data processing circuit 222 can output different second clock control signals to the clock signal lines 35 so that each of the switching circuits 241 is turned on or off under control of each of the second clock control signals. When the second clock control signals control the switching circuits 241 to turn on, the display driving signals are controlled to be transmitted to all columns of sub-pixels in a one-to-one correspondence.
The embodiment of the present application further provides a display screen. The display screen includes the driver chip provided by the embodiments of the present application. Therefore, the display screen includes technical features of the driver chip provided by the embodiments of the present application and beneficial effects of the driver chip provided by the embodiments of the present application. For similarities, refer to description of the driver chip provided by the embodiments of the present application, and repetition is not made herein.
Exemplarily,
The embodiments of the present application further provide a display device. The display device includes the display screen provided by the embodiment of the present application. Therefore, the display device has technical features and beneficial effects of the display screen provided by the embodiment of the present application. For similarities, refer to description of the display screen provided by the embodiment of the present application, and repetition is not made herein.
Exemplarily,
| Number | Date | Country | Kind |
|---|---|---|---|
| 202011206657.5 | Nov 2020 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2021/083264 | 3/26/2021 | WO |
