The invention relates to a driver circuit, more specifically, to a driver circuit configured to drive a display panel.
An electronic device with a display function typically includes a display panel and a driver chip. The driver chip is configured to drive the display panel to display an image. The driver chip is connected to the display panel through a fan-out area to output display data to drive the display panel. In order to reduce the length of the fan-out area between the driver chip and the display panel, extended connecting lines of the display panel may be laid out in the active area of the display panel. However, for the driver chip to drive a display panel with this layout, the sequence of the data outputted to the display panel must be changed so that the display data could properly drive the pixels on the display panel.
The invention is directed to a driver circuit, capable of rearranging display data to adaptively drive the display panel. In addition, the length of the fan-out area can be reduced.
An embodiment of the invention provides a driver circuit including a switch circuit and a source driver circuit. The switch circuit is configured to receive an input display data and output an output display data according to two control signals. The input display data and the output display data have different data arrangement. The source driver circuit is coupled to the switch circuit. The source driver circuit is configured to output the output display data to drive a display panel via the switch circuit. An applying sequence of the two control signals is adjusted according to at least one adjustment signal, and the two control signals are applied to switch sets of the switch circuit according to the applying sequence.
To make the aforementioned more comprehensible, several embodiments accompanied with drawings are described in detail as follows.
The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.
Embodiments are provided below to describe the disclosure in detail, though the disclosure is not limited to the provided embodiments, and the provided embodiments can be suitably combined. The term “coupling/coupled” or “connecting/connected” used in this specification (including claims) of the application may refer to any direct or indirect connection means. For example, “a first device is coupled to a second device” should be interpreted as “the first device is directly connected to the second device” or “the first device is indirectly connected to the second device through other devices or connection means.” In addition, the term “signal” can refer to a current, a voltage, a charge, a temperature, data, electromagnetic wave or any one or multiple signals.
The driver circuit 110 is configured to drive the display panel 120 to display images. The driver circuit 110 includes a source driver circuit 116 and a switch circuit 117. The source driver circuit 116 is configured to output driving signals to drive the display panel 120 to display images. The switch circuit 117 includes a first switch unit 117_1 and a second switch unit 117_2. The first switch unit 117_1 and the second switch unit 117_2 are respectively disposed at the output end and the input end of the source driver circuit 116. The first switch unit 117_1 and the second switch unit 117_2 are controlled by control signals MUX1 and MUX2 to rearrange received display data to corresponding data lines DL.
In an embodiment, the switches of the first switch unit 117_1 and the second switch unit 117_2 may be implemented as metal oxide semiconductor field effect transistors (MOSFET). The MOSFETs on the driver circuit 110, e.g. display driver integrated circuit (DDIC), have characteristics of lower operating voltages, lower on-resistances, and lower power consumption.
The driver circuit 110 may include a controller circuit (not shown) to generate the control signals MUX1 and MUX2. The controller circuit may be a processor having computational capability. Alternatively, the controller circuit may be designed through hardware description languages (HDL) or any other design methods for digital circuits familiar to people skilled in the art and may be hardware circuits implemented through a field programmable gate array (FPGA), a complex programmable logic device (CPLD), or an application-specific integrated circuit (ASIC). In addition, enough teaching, suggestion, and implementation illustration for hardware structures of the controller circuit can be obtained with reference to common knowledge in the related art. In another embodiment, the controller circuit may be disposed in an application processor of the electronic device 100.
In the present embodiment, the electronic device 100 may be an electronic device having a display function, a touch sensing function and/or a fingerprint sensing function. In an embodiment, the electronic device 100 may be, but not limited to, a smartphone, a non-smart phone, a wearable electronic device, a tablet computer, a personal digital assistant, a notebook and other portable electronic devices that can operate independently and have the display function, the touch sensing function and/or the fingerprint sensing function. In an embodiment, the electronic device 100 may be, but not limited to, a portable or un-portable electronic device in a vehicle intelligent system. In an embodiment, the electronic device 100 may be, but not limited to, intelligent home appliances such as, a television, a computer, a refrigerator, a washing machine, a telephone, an induction cooker, a table lamp and so on.
In the present embodiment, since the first switch unit 117_1 and the second switch unit 117_2 for data rearrangement are both disposed in the driver circuit 110, the length L of the fan-out area 130 can be reduced. In addition, in order to further reduce the length L of the fan-out area 130, a layout of data lines DL of the display panel 120 may be implemented in a manner of fan-out in active area (FIAA). In the present embodiment, FIAA layout is adopted for data lines DL, and thus the length L of the fan-out area 130 of
The switch circuit 417 is configured to receiving an input display data DD_IN and output an output display data DD_OUT according to two control signals MUX1 and MUX2. The input display data DD_IN and the output display data DD_OUT have different data arrangement. An applying sequence of the two control signals MUX1 and MUX2 is adjusted according to at least one adjustment signal CTRm and/or CTRdm. The two control signals MUX1 and MUX2 are applied to switch sets SW_1 to SW_6 of the switch circuit 417 according to the applying sequence.
To be specific, the switch circuit 417 includes a first switch unit 417_1 and a second switch unit 417_2. The second switch unit 417_2 is disposed at an input end of the source driver circuit 416. The second switch unit 417_2 is configured to receive the input display data DD_IN, and output the input display data DD_IN according to the two control signals MUX1 and MUX2. The first switch unit is disposed at an output end of the source driver circuit 416. The first switch unit is configured to receive the input display data DD_IN from the source driver circuit 416, and output the output display data DD_OUT according to the two control signals MUX1 and MUX2. The output display data DD_OUT will be written into corresponding pixels.
The first switch unit 417_1 includes a plurality of first switch sets SW_1, SW_2, and SW_3. Each of the first switch sets SW_1, SW_2, and SW_3 is controlled by the two control signals MUX1 and MUX2. Compared to the second switch set SW_3, the applying sequence of the control signals MUX1 and MUX2 are adjusted, and the control signals MUX1 and MUX2 are applied to the first switch sets SW_1 and SW_2 according to the adjusted applying sequence. The applying sequence of the control signals MUX1 and MUX2, which are applied to the first switch set SW_3, remains unchanged.
On the other hand, the second switch unit 417_2 includes a plurality of second switch sets SW_4, SW_5, and SW_6. Each of the second switch sets SW_4, SW_5, and SW_6 also is controlled by the two control signals MUX1 and MUX2. Corresponding to the first switch unit 417_1, in the second switch unit 417_2, the applying sequence of the control signals MUX1 and MUX2 are also adjusted, and the control signals MUX1 and MUX2 are applied to the second switch sets SW_4 and SW_5 according to the adjusted applying sequence. The applying sequence of the control signals MUX1 and MUX2, which are applied to the second switch set SW_6, remains unchanged.
In the present embodiment, the applying sequence of the control signals MUX1 and MUX2 applied to the first switch set SW_3 and the second switch set SW_6 can be deemed as a first applying sequence (a preset applying sequence). The applying sequence of the control signals MUX1 and MUX2 applied to the first switch set SW_1 and SW_2 and the second switch set SW_4 and SW_5 can be deemed as a second applying sequence. CTRm=1 and CTRdm=1 indicate that the applying sequence is adjusted from the first applying sequence to the second applying sequence. CTRm=0 and CTRdm=0 indicate that the applying sequence remains unchanged changed and keeps the first applying sequence.
As a result, in order to output a display data having the same arrangement as the output display data DD_OUT, the input display data DD_IN is rearranged to match the output display data DD_OUT via the switch circuit 417.
To be specific,
Taking the display data Dm−3 to Dm+4 of the input display data DD_IN for example, the positions P1 to P8 correspond to the source pads S1 to S8. Each two neighboring display data are grouped as a data set. Each data set has corresponding switch sets and adjustment signals CTRm and CTRdm. For example, the two neighboring display data Dm+1 and Dm are grouped as the data set D4, and the data set D4 has corresponding switch sets SW_4 and SW_1. The switch set SW_4 serves as a multiplexer circuit, and the switch set SW_1 serves as a demultiplexer circuit.
The second adjustment signal CTRm indicates whether the applying sequence of the control signals MUX1 and MUX2 is adjusted. When CTRm=0 (second state), the applying sequence of the control signals MUX1 and MUX2 is not adjusted. When CTRm=1 (first state), the applying sequence of the control signals MUX1 and MUX2 is adjusted.
The first adjustment signal CTRdm indicates whether the applying sequence of the control signals MUX1 and MUX2 is adjusted. When CTRdm=0, the applying sequence of the control signals MUX1 and MUX2 is not adjusted. When CTRdm=1, the applying sequence of the control signals MUX1 and MUX2 is adjusted.
In
The operating method of other switches can refer to that of the switches 601 to 604, and no further description will be provided herein. In an embodiment, the driver circuit 510 may include a register circuit (not shown) to set the adjustment signals CTRm and CTRdm. The adjustment of the control signals MUX1 and MUX2 is controlled by the adjustment signals CTRm and CTRdm to allow flexibility in the data arrangement of the output display data DD_OUT to meet the design requirements of the display panel.
The adjustment signals CTRm and CTRdm can be set independently for each switch set. Alternatively, the adjustment signals CTRm and CTRdm can be set repeatedly for multiple switch sets. For example, each two to eight switch sets are set to have the same adjustment signals CTRm and CTRdm.
For all switch sets of the second switch unit 717_2, CTRm=0. The two control signals MUX1 and MUX2 are applied to the neighboring second switch sets in the same applying sequence, e.g. the first applying sequence. For all switch sets of the first switch unit 717_1, it starts from CTRdm=0, and CTRdm=0 and CTRdm=1 are alternately changed. The two control signals MUX1 and MUX2 are applied to the neighboring first switch sets in different applying sequences, e.g. the first applying sequence and the second applying sequence. The output display data DD_OUT is outputted in a time-division manner.
The control signals MUX1 and MUX2 are adjusted and applied to the switch sets SW_81, SW_82 and SW_83, and the source pads S3, S4, S7, S8, S11 and S12 can respectively output the display data Dm, Dm−1, Dm+4, Dm+3, Dm−4 and Dm−5. For all switch sets of the second switch unit 817_2, CTRm=0. For all switch sets of the first switch unit 817_1, it starts from CTRdm=0, and CTRdm=0 and CTRdm=1 are alternately changed. The output display data DD_OUT is outputted in a time-division manner.
The control signals MUX1 and MUX2 are adjusted and applied to the switch sets SW_91, SW_92 and SW_93, and the source pads S1, S2, S5, S6, S9 and S10 can respectively output the display data Dm, Dm+1, Dm−2, Dm+3, Dm−4 and Dm+5. For all switch sets of the second switch unit 917_2, CTRm=0. For all switch sets of the first switch unit 917_1, it starts from CTRdm=1, and CTRdm=1 and CTRdm=0 are alternately changed. The output display data DD_OUT is outputted in a time-division manner.
In summary, in the embodiment of the invention, the data sequence of the display data outputted from the driver circuit is rearranged to adaptively drive the display panel via the switch circuit. Two control signals are applied to control conduction states of the switch circuit, and the applying sequence of the two control signals is adjusted according to at least one adjustment signal. As a result, the input display data is rearranged to match the output display data via the switch circuit. In addition, since the switch circuit for data rearrangement are both disposed in the driver circuit, the length of the fan-out area can be reduced.
It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations provided that they fall within the scope of the following claims and their equivalents.
This application is a continuation-in-part application of and claims the priority benefit of a prior application Ser. No. 18/540,889, filed on Dec. 15, 2023. This application also claims the priority benefit of U.S. provisional application Ser. No. 63/673,800, filed on Jul. 22, 2024. The entirety of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.
Number | Date | Country | |
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63673800 | Jul 2024 | US |
Number | Date | Country | |
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Parent | 18540889 | Dec 2023 | US |
Child | 18950136 | US |