Patent Application
20170084234
This disclosure relates to display driver circuits with shared nodes.
Electromechanical systems (EMS) include devices having electrical and mechanical elements, actuators, transducers, sensors, optical components such as mirrors and optical films, and electronics. EMS devices or elements can be manufactured at a variety of scales including, but not limited to, microscales and nanoscales. For example, microelectromechanical systems (MEMS) devices can include structures having sizes ranging from about a micron to hundreds of microns or more. Nanoelectromechanical systems (NEMS) devices can include structures having sizes smaller than a micron including, for example, sizes smaller than several hundred nanometers. Electromechanical elements may be created using deposition, etching, lithography, and/or other micromachining processes that etch away parts of substrates and/or deposited material layers, or that add layers to form electrical and electromechanical devices.
One type of EMS device is called an interferometric modulator (IMOD). The term IMOD or interferometric light modulator refers to a device that selectively absorbs and/or reflects light using the principles of optical interference. In some implementations, an IMOD display element may include a pair of conductive plates, one or both of which may be transparent and/or reflective, wholly or in part, and capable of relative motion upon application of an appropriate electrical signal. For example, one plate may include a stationary layer deposited over, on or supported by a substrate and the other plate may include a reflective membrane separated from the stationary layer by an air gap. The position of one plate in relation to another can change the optical interference of light incident on the IMOD display element. IMOD-based display devices have a wide range of applications, and are anticipated to be used in improving existing products and creating new products, especially those with display capabilities.
In some implementations, each IMOD may include a movable element (e.g., a mirror) that can be moved to positions to reflect light at particular wavelengths. Row driver and column driver circuits can provide voltages to terminals of transistors and/or electrodes of the IMOD and in a particular sequence such that the movable element is properly positioned.
Row driver circuits can be implemented with thin film transistors (TFTs) on the glass of a display device rather than with traditional CMOS in silicon. Implementing the row driver circuits with TFTs is advantageous because it can make it possible to have a narrower bezel thanks to reduced number of routing lines than using an off-glass CMOS chip. However, TFT implementations can have higher power dissipation, and it is required to minimize the bezel width to get a compact form factor.
The systems, methods and devices of this disclosure each have several innovative aspects, no single one of which is solely responsible for the desirable attributes disclosed herein.
One innovative aspect of the subject matter described in this disclosure can be implemented in a circuit capable of biasing a first charge node and electrically coupling the biased charge node with buffer charge nodes of a set of output buffers in a first phase, and capable of sequentially electrically coupling the buffer charge nodes of the output buffers of the set of output buffers in a second phase occurring after the first phase, the first charge node floating during the second phase, and corresponding outputs of the output buffers being sequentially asserted during the second phase.
In some implementations, the set of output buffers can include a first buffer comprising a first switch having a first terminal and a second terminal, the first terminal coupled with the first charge node; a second switch having a first terminal and a second terminal, the first terminal coupled with the first charge node, and the second terminal coupled with the second terminal of the first switch to define a first buffer charge node of the buffer charge nodes.
In some implementations, the first switch can have a control terminal coupled with a first clock, and the second switch can have a control terminal coupled with a second clock, the second switch turned on by the second clock during the first phase, the first switch turned on by the first clock during the second phase.
In some implementations, the circuit can have a third switch having a first terminal, a second terminal, and a control terminal, the control terminal coupled with the first buffer charge node, the first terminal coupled with the first clock, the second terminal to provide a first output of the corresponding outputs of the output buffers.
In some implementations, the circuit can have a fourth switch having a first terminal and a control terminal, the first terminal coupled with the second terminal of the third switch, the control terminal coupled with a second charge node.
In some implementations, the circuit can have a capacitor having a first terminal and a second terminal, the first terminal coupled with the first buffer charge node, and the second terminal coupled with the second terminal of the third switch.
In some implementations, the set of output buffers can include a first output buffer and a second output buffer, the second phase includes a first period and a second period, an output of the first output buffer asserted and an output of the second output de-asserted during the first period, the output of the first output buffer de-asserted and the output of the second output asserted during the second period.
In some implementations, the first output buffer can include a first buffer charge node and the second output buffer includes a second buffer charge node, the first buffer charge node electrically coupled with the charge node in the first period, the second buffer charge node electrically coupled with the charge node in the second period.
In some implementations, the circuit can have a display including a plurality of display elements; a processor that is configured to communicate with the display, the processor being configured to process image data; and a memory device that is configured to communicate with the processor.
In some implementations, the circuit can have a driver circuit including the circuit and configured to send at least one signal to the display; and a controller configured to send at least a portion of the image data to the driver circuit.
In some implementations, the circuit can have an image source module configured to send the image data to the processor, wherein the image source module includes a component selected from the group consisting of at least one of a receiver, a transceiver, and a transmitter.
In some implementations, the corresponding outputs of the output buffers being sequentially asserted during the second phase can include assertions of a first row signal, a carry signal, and a second row signal, the carry signal asserted after the first row signal and before the second row signal.
Another innovative aspect of the subject matter described in this disclosure can be implemented in a circuit having a latch circuit capable of driving a charge node in a first operation and floating the charge node in a second operation; a first output buffer coupled with the charge node, the first output buffer having a first output buffer charge node; and a second output buffer coupled with the charge node, the first output buffer having a second output buffer charge node, wherein both the first output buffer charge node and the second output buffer charge node are driven using the charge node during the first operation, and one of the first output buffer charge node and the second output buffer charge node is driven using the charge node during the second operation to assert an output signal corresponding to an output of the one of the first output buffer charge node and the second output buffer charge node.
In some implementations, the first output buffer can have a first switch having a first terminal and a second terminal, the first terminal coupled with the charge node; a second switch having a first terminal and a second terminal, the first terminal coupled with the charge node, and the second terminal coupled with the second terminal of the first switch to define the first output buffer charge node.
In some implementations, the first switch can have a control terminal coupled with a first clock, and the second switch has a control terminal coupled with a second clock, the second switch turned on by the second clock during the first phase, the first switch turned on by the first clock during the second phase.
In some implementations, the second output buffer can have a third switch having a first terminal and a second terminal, the first terminal coupled with the charge node; a fourth switch having a first terminal and a second terminal, the first terminal coupled with the charge node, and the second terminal coupled with the second terminal of the third switch to define the second buffer charge node.
In some implementations, the third switch can have a control terminal coupled with a third clock, and the fourth switch has a control terminal coupled with the second clock, the fourth switch turned on by the second clock during the first phase, the third switch turned on by the third clock during the second phase after the first switch is turned on.
In some implementations, the circuit can have a third output buffer coupled with the charge node.
Another innovative aspect of the subject matter described in this disclosure can be implemented in method comprising driving a charge node of a circuit; turning on a first switch of a first output buffer and a second switch of a second output buffer to drive a first output buffer charge node of the first output buffer and a second output buffer charge node of the second output buffer; floating the charge node; turning off the first switch and the second switch; and turning on a third switch of the first output buffer to drive the first output buffer charge node based on the floating charge node, wherein the second output buffer charge node is floating.
In some implementations, the method can comprise asserting an output of the first output buffer responsive to the third switch turning on.
Details of one or more implementations of the subject matter described in this disclosure are set forth in the accompanying drawings and the description below. Although the examples provided in this disclosure are primarily described in terms of EMS and MEMS-based displays the concepts provided herein may apply to other types of displays such as liquid crystal displays, organic light-emitting diode (“OLED”) displays, and field emission displays. Other features, aspects, and advantages will become apparent from the description, the drawings and the claims. Note that the relative dimensions of the following figures may not be drawn to scale.
Like reference numbers and designations in the various drawings indicate like elements.
The following description is directed to certain implementations for the purposes of describing the innovative aspects of this disclosure. However, a person having ordinary skill in the art will readily recognize that the teachings herein can be applied in a multitude of different ways. The described implementations may be implemented in any device, apparatus, or system that can be configured to display an image, whether in motion (such as video) or stationary (such as still images), and whether textual, graphical or pictorial. More particularly, it is contemplated that the described implementations may be included in or associated with a variety of electronic devices such as, but not limited to: mobile telephones, multimedia Internet enabled cellular telephones, mobile television receivers, wireless devices, smartphones, Bluetooth® devices, personal data assistants (PDAs), wireless electronic mail receivers, hand-held or portable computers, netbooks, notebooks, smartbooks, tablets, printers, copiers, scanners, facsimile devices, global positioning system (GPS) receivers/navigators, cameras, digital media players (such as MP3 players), camcorders, game consoles, wrist watches, clocks, calculators, television monitors, flat panel displays, electronic reading devices (e.g., e-readers), computer monitors, auto displays (including odometer and speedometer displays, etc.), cockpit controls and/or displays, camera view displays (such as the display of a rear view camera in a vehicle), electronic photographs, electronic billboards or signs, projectors, architectural structures, microwaves, refrigerators, stereo systems, cassette recorders or players, DVD players, CD players, VCRs, radios, portable memory chips, washers, dryers, washer/dryers, parking meters, packaging (such as in electromechanical systems (EMS) applications including microelectromechanical systems (MEMS) applications, as well as non-EMS applications), aesthetic structures (such as display of images on a piece of jewelry or clothing) and a variety of EMS devices. The teachings herein also can be used in non-display applications such as, but not limited to, electronic switching devices, radio frequency filters, sensors, accelerometers, gyroscopes, motion-sensing devices, magnetometers, inertial components for consumer electronics, parts of consumer electronics products, varactors, liquid crystal devices, electrophoretic devices, drive schemes, manufacturing processes and electronic test equipment. Thus, the teachings are not intended to be limited to the implementations depicted solely in the Figures, but instead have wide applicability as will be readily apparent to one having ordinary skill in the art.
Active matrix flat panel displays such as active matrix liquid crystal displays, organic light emission displays, and interferometric modulator (IMOD) displays can use thin film transistors (TFTs) on glass substrates to implement driver circuits providing a sequence of voltages to terminals of transistors and/or electrodes of display elements, such as IMODs. Implementing the row driver circuits with TFTs is advantageous because it can make it possible to have a narrower bezel thanks to reduced number of routing lines than using an off-glass CMOS chip. However, TFT implementations can have higher power dissipation, and it is required to reduce the bezel width to get a compact form factor for the display.
Some implementations of the subject matter described in this disclosure reduce the area used to implement driver circuits, which results in a narrow border width of the bezel of the display. An integrated bias driver circuit can be used to provide a voltage to bias terminals of multiple rows of IMODs in the display. Additionally, an integrated row driver circuit and integrated gate driver circuit can include a latch stage providing a shared node to multiple output buffers that can sequentially use the shared node to drive their respective outputs.
Particular implementations of the subject matter described in this disclosure can be implemented to realize one or more of the following potential advantages. Reducing the number of TFTs used to implement driver circuits may result in reduced costs, decreased power requirements, and narrower bezel around the display, resulting in a sleeker device.
An example of a suitable EMS or MEMS device or apparatus, to which the described implementations may apply, is a reflective display device. Reflective display devices can incorporate interferometric modulator (IMOD) display elements that can be implemented to selectively absorb and/or reflect light incident thereon using principles of optical interference. IMOD display elements can include a partial optical absorber, a reflector that is movable with respect to the absorber, and an optical resonant cavity defined between the absorber and the reflector. In some implementations, the reflector can be moved to two or more different positions, which can change the size of the optical resonant cavity and thereby affect the reflectance of the IMOD. The reflectance spectra of IMOD display elements can create fairly broad spectral bands that can be shifted across the visible wavelengths to generate different colors. The position of the spectral band can be adjusted by changing the thickness of the optical resonant cavity. One way of changing the optical resonant cavity is by changing the position of the reflector with respect to the absorber.
The IMOD display device can include an array of IMOD display elements which may be arranged in rows and columns. Each display element in the array can include at least a pair of reflective and semi-reflective layers, such as a movable reflective layer (i.e., a movable layer, also referred to as a mechanical layer) and a fixed partially reflective layer (i.e., a stationary layer), positioned at a variable and controllable distance from each other to form an air gap (also referred to as an optical gap, cavity or optical resonant cavity). The movable reflective layer may be moved between at least two positions. For example, in a first position, i.e., a relaxed position, the movable reflective layer can be positioned at a distance from the fixed partially reflective layer. In a second position, i.e., an actuated position, the movable reflective layer can be positioned more closely to the partially reflective layer. Incident light that reflects from the two layers can interfere constructively and/or destructively depending on the position of the movable reflective layer and the wavelength(s) of the incident light, producing either an overall reflective or non-reflective state for each display element. In some implementations, the display element may be in a reflective state when unactuated, reflecting light within the visible spectrum, and may be in a dark state when actuated, absorbing and/or destructively interfering light within the visible range. In some other implementations, however, an IMOD display element may be in a dark state when unactuated, and in a reflective state when actuated. In some implementations, the introduction of an applied voltage can drive the display elements to change states. In some other implementations, an applied charge can drive the display elements to change states.
The depicted portion of the array in
In
The optical stack 16 can include a single layer or several layers. The layer(s) can include one or more of an electrode layer, a partially reflective and partially transmissive layer, and a transparent dielectric layer. In some implementations, the optical stack 16 is electrically conductive, partially transparent and partially reflective, and may be fabricated, for example, by depositing one or more of the above layers onto a transparent substrate 20. The electrode layer can be formed from a variety of materials, such as various metals, for example indium tin oxide (ITO). The partially reflective layer can be formed from a variety of materials that are partially reflective, such as various metals (e.g., chromium and/or molybdenum), semiconductors, and dielectrics. The partially reflective layer can be formed of one or more layers of materials, and each of the layers can be formed of a single material or a combination of materials. In some implementations, certain portions of the optical stack 16 can include a single semi-transparent thickness of metal or semiconductor which serves as both a partial optical absorber and electrical conductor, while different, electrically more conductive layers or portions (e.g., of the optical stack 16 or of other structures of the display element) can serve to bus signals between IMOD display elements. The optical stack 16 also can include one or more insulating or dielectric layers covering one or more conductive layers or an electrically conductive/partially absorptive layer.
In some implementations, at least some of the layer(s) of the optical stack 16 can be patterned into parallel strips, and may form row electrodes in a display device as described further below. As will be understood by one having ordinary skill in the art, the term “patterned” is used herein to refer to masking as well as etching processes. In some implementations, a highly conductive and reflective material, such as aluminum (Al), may be used for the movable reflective layer 14, and these strips may form column electrodes in a display device. The movable reflective layer 14 may be formed as a series of parallel strips of a deposited metal layer or layers (orthogonal to the row electrodes of the optical stack 16) to form columns deposited on top of supports, such as the illustrated posts 18, and an intervening sacrificial material located between the posts 18. When the sacrificial material is etched away, a defined gap 19, or optical cavity, can be formed between the movable reflective layer 14 and the optical stack 16. In some implementations, the spacing between posts 18 may be approximately 1-1000 μm, while the gap 19 may be approximately less than 10,000 Angstroms (Å).
In some implementations, each IMOD display element, whether in the actuated or relaxed state, can be considered as a capacitor formed by the fixed and moving reflective layers. When no voltage is applied, the movable reflective layer 14 remains in a mechanically relaxed state, as illustrated by the display element 12 on the left in
The processor 21 can be configured to communicate with an array driver 22. The array driver 22 can include a row driver circuit 24 and a column driver circuit 26 that provide signals to, for example a display array or panel 30. The cross section of the IMOD display device illustrated in
In some implementations, a frame of an image may be created by applying data signals in the form of “segment” voltages along the set of column electrodes, in accordance with the desired change (if any) to the state of the display elements in a given row. Each row of the array can be addressed in turn, such that the frame is written one row at a time. To write the desired data to the display elements in a first row, segment voltages corresponding to the desired state of the display elements in the first row can be applied on the column electrodes, and a first row pulse in the form of a specific “common” voltage or signal can be applied to the first row electrode. The set of segment voltages can then be changed to correspond to the desired change (if any) to the state of the display elements in the second row, and a second common voltage can be applied to the second row electrode. In some implementations, the display elements in the first row are unaffected by the change in the segment voltages applied along the column electrodes, and remain in the state they were set to during the first common voltage row pulse. This process may be repeated for the entire series of rows, or alternatively, columns, in a sequential fashion to produce the image frame. The frames can be refreshed and/or updated with new image data by continually repeating this process at some desired number of frames per second.
The combination of segment and common signals applied across each display element (that is, the potential difference across each display element or pixel) determines the resulting state of each display element.
As illustrated in
When a hold voltage is applied on a common line, such as a high hold voltage VCHOLD_H or a low hold voltage VCHOLD_L, the state of the IMOD display element along that common line will remain constant. For example, a relaxed IMOD display element will remain in a relaxed position, and an actuated IMOD display element will remain in an actuated position. The hold voltages can be selected such that the display element voltage will remain within a stability window both when the high segment voltage VSH and the low segment voltage VSL are applied along the corresponding segment line. Thus, the segment voltage swing in this example is the difference between the high VSH and low segment voltage VSL, and is less than the width of either the positive or the negative stability window.
When an addressing, or actuation, voltage is applied on a common line, such as a high addressing voltage VCADD_H or a low addressing voltage VCADD_L, data can be selectively written to the modulators along that common line by application of segment voltages along the respective segment lines. The segment voltages may be selected such that actuation is dependent upon the segment voltage applied. When an addressing voltage is applied along a common line, application of one segment voltage will result in a display element voltage within a stability window, causing the display element to remain unactuated. In contrast, application of the other segment voltage will result in a display element voltage beyond the stability window, resulting in actuation of the display element. The particular segment voltage which causes actuation can vary depending upon which addressing voltage is used. In some implementations, when the high addressing voltage VCADD_H is applied along the common line, application of the high segment voltage VSH can cause a modulator to remain in its current position, while application of the low segment voltage VSL can cause actuation of the modulator. As a corollary, the effect of the segment voltages can be the opposite when a low addressing voltage VCADD_L is applied, with high segment voltage VSH causing actuation of the modulator, and low segment voltage VSL having substantially no effect (i.e., remaining stable) on the state of the modulator.
In some implementations, hold voltages, address voltages, and segment voltages may be used which produce the same polarity potential difference across the modulators. In some other implementations, signals can be used which alternate the polarity of the potential difference of the modulators from time to time. Alternation of the polarity across the modulators (that is, alternation of the polarity of write procedures) may reduce or inhibit charge accumulation that could occur after repeated write operations of a single polarity.
During the first line time 60a: a release voltage 70 is applied on common line 1; the voltage applied on common line 2 begins at a high hold voltage 72 and moves to a release voltage 70; and a low hold voltage 76 is applied along common line 3. Thus, the modulators (common 1, segment 1), (1,2) and (1,3) along common line 1 remain in a relaxed, or unactuated, state for the duration of the first line time 60a, the modulators (2,1), (2,2) and (2,3) along common line 2 will move to a relaxed state, and the modulators (3,1), (3,2) and (3,3) along common line 3 will remain in their previous state. In some implementations, the segment voltages applied along segment lines 1, 2 and 3 will have no effect on the state of the IMOD display elements, as none of common lines 1, 2 or 3 are being exposed to voltage levels causing actuation during line time 60a (i.e., VCREL−relax and VCHOLD_L−stable).
During the second line time 60b, the voltage on common line 1 moves to a high hold voltage 72, and all modulators along common line 1 remain in a relaxed state regardless of the segment voltage applied because no addressing, or actuation, voltage was applied on the common line 1. The modulators along common line 2 remain in a relaxed state due to the application of the release voltage 70, and the modulators (3,1), (3,2) and (3,3) along common line 3 will relax when the voltage along common line 3 moves to a release voltage 70.
During the third line time 60c, common line 1 is addressed by applying a high address voltage 74 on common line 1. Because a low segment voltage 64 is applied along segment lines 1 and 2 during the application of this address voltage, the display element voltage across modulators (1,1) and (1,2) is greater than the high end of the positive stability window (i.e., the voltage differential exceeded a characteristic threshold) of the modulators, and the modulators (1,1) and (1,2) are actuated. Conversely, because a high segment voltage 62 is applied along segment line 3, the display element voltage across modulator (1,3) is less than that of modulators (1,1) and (1,2), and remains within the positive stability window of the modulator; modulator (1,3) thus remains relaxed. Also during line time 60c, the voltage along common line 2 decreases to a low hold voltage 76, and the voltage along common line 3 remains at a release voltage 70, leaving the modulators along common lines 2 and 3 in a relaxed position.
During the fourth line time 60d, the voltage on common line 1 returns to a high hold voltage 72, leaving the modulators along common line 1 in their respective addressed states. The voltage on common line 2 is decreased to a low address voltage 78. Because a high segment voltage 62 is applied along segment line 2, the display element voltage across modulator (2,2) is below the lower end of the negative stability window of the modulator, causing the modulator (2,2) to actuate. Conversely, because a low segment voltage 64 is applied along segment lines 1 and 3, the modulators (2,1) and (2,3) remain in a relaxed position. The voltage on common line 3 increases to a high hold voltage 72, leaving the modulators along common line 3 in a relaxed state. Then, the voltage on common line 2 transitions back to the low hold voltage 76.
Finally, during the fifth line time 60e, the voltage on common line 1 remains at high hold voltage 72, and the voltage on common line 2 remains at the low hold voltage 76, leaving the modulators along common lines 1 and 2 in their respective addressed states. The voltage on common line 3 increases to a high address voltage 74 to address the modulators along common line 3. As a low segment voltage 64 is applied on segment lines 2 and 3, the modulators (3,2) and (3,3) actuate, while the high segment voltage 62 applied along segment line 1 causes modulator (3,1) to remain in a relaxed position. Thus, at the end of the fifth line time 60e, the 3×3 display element array is in the state shown in
In the timing diagram of
In some implementations, the packaging of an EMS component or device, such as an IMOD-based display, can include a backplate (alternatively referred to as a backplane, back glass or recessed glass) which can be configured to protect the EMS components from damage (such as from mechanical interference or potentially damaging substances). The backplate also can provide structural support for a wide range of components, including but not limited to driver circuitry, processors, memory, interconnect arrays, vapor barriers, product housing, and the like. In some implementations, the use of a backplate can facilitate integration of components and thereby reduce the volume, weight, and/or manufacturing costs of a portable electronic device.
The backplate 92 can be essentially planar or can have at least one contoured surface (e.g., the backplate 92 can be formed with recesses and/or protrusions). The backplate 92 may be made of any suitable material, whether transparent or opaque, conductive or insulating. Suitable materials for the backplate 92 include, but are not limited to, glass, plastic, ceramics, polymers, laminates, metals, metal foils, Kovar and plated Kovar.
As shown in
The backplate components 94a and/or 94b can include one or more active or passive electrical components, such as transistors, capacitors, inductors, resistors, diodes, switches, and/or integrated circuits (ICs) such as a packaged, standard or discrete IC. Other examples of backplate components that can be used in various implementations include antennas, batteries, and sensors such as electrical, touch, optical, or chemical sensors, or thin-film deposited devices.
In some implementations, the backplate components 94a and/or 94b can be in electrical communication with portions of the EMS array 36. Conductive structures such as traces, bumps, posts, or vias may be formed on one or both of the backplate 92 or the substrate 20 and may contact one another or other conductive components to form electrical connections between the EMS array 36 and the backplate components 94a and/or 94b. For example,
The backplate components 94a and 94b can include one or more desiccants which act to absorb any moisture that may enter the EMS package 91. In some implementations, a desiccant (or other moisture absorbing materials, such as a getter) may be provided separately from any other backplate components, for example as a sheet that is mounted to the backplate 92 (or in a recess formed therein) with adhesive. Alternatively, the desiccant may be integrated into the backplate 92. In some other implementations, the desiccant may be applied directly or indirectly over other backplate components, for example by spray-coating, screen printing, or any other suitable method.
In some implementations, the EMS array 36 and/or the backplate 92 can include mechanical standoffs 97 to maintain a distance between the backplate components and the display elements and thereby prevent mechanical interference between those components. In the implementation illustrated in
Although not illustrated in
In alternate implementations, a seal ring may include an extension of either one or both of the backplate 92 or the substrate 20. For example, the seal ring may include a mechanical extension (not shown) of the backplate 92. In some implementations, the seal ring may include a separate member, such as an O-ring or other annular member.
In some implementations, the EMS array 36 and the backplate 92 are separately formed before being attached or coupled together. For example, the edge of the substrate 20 can be attached and sealed to the edge of the backplate 92 as discussed above. Alternatively, the EMS array 36 and the backplate 92 can be formed and joined together as the EMS package 91. In some other implementations, the EMS package 91 can be fabricated in any other suitable manner, such as by forming components of the backplate 92 over the EMS array 36 by deposition.
The implementation of display module 710 in display array 30 may include a variety of different designs. As an example, display module 710 in the fourth row includes switch 720 and display unit 750. Display module 710 may be provided a row signal, reset signal, and a bias signal from row driver circuit 24. Display module 710 may also be provided a column (or data) signal and a common signal from column driver circuit 26. Display unit 750 may be coupled with switch 720, such as a transistor with its gate coupled to the row signal and its drain coupled with the column signal. Each display unit 750 may include an IMOD display element as a pixel.
Some IMODs are three-terminal devices that use a variety of signals.
In
Movable element 870 can be positioned at points, or locations, between Vbias electrode 855 and Vcom electrode 865 to provide light at a specific wavelength at each specific point. In particular, voltages applied to Vbias electrode 855, Vd electrode 860, and Vcom electrode 865 may determine the position of movable element 870. Voltages for Vreset 895, Vcolumn 820 (which is applied to Vd electrode 860 if transistor T1810 is turned on), Vrow 830, Vcom electrode 865, and Vbias 896 (to be applied to Vbias electrode 855) may be provided by driver circuits such as row driver circuit 24 and column driver circuit 26. In some implementations, Vcom electrode 865 may be coupled to ground rather than driven by row driver circuit 24 or column driver circuit 26, as depicted in
In
Generally, Vreset 895 is asserted (or applied by providing a voltage pulse from low to high voltage) by row driver circuit 24 (e.g., initiated by driver controller 29, or another controller, providing signals to row driver circuit 24 to begin) to turn on transistor T1810 to short Vcom electrode 865 and Vd electrode 870 to position movable element 870 to a reset position. Vreset 895 can then be de-asserted (e.g., switched from a high voltage to a low voltage to turn off transistor T1810) and column driver circuit 26 can provide Vcolumn 820 (at a voltage based on the intended position to move movable element 870 towards) and row driver circuit 24 can assert Vrow 830 such that transistor T1810 is turned on and the voltage on Vcolumn 820 is applied to Vd electrode 860 of display unit 750. The voltage of Vbias 896 can also be changed to provide different voltages on Vbias electrode 855. For example, before Vreset 895 is asserted, row driver circuit 24 can apply a 0 V Vbias 896 to have Vbias electrode 855 also be 0 V, but change Vbias 896 to a higher or lower voltage following the application of Vcolumn 820 and Vrow 830 based on a polarity of display unit 750 (e.g., the directions of the electric fields between the electrodes of display unit 750). This process may occur row-by-row until each movable element 870 in each row of display modules 710 is positioned. For example, Vreset 895 for a first row of display modules 710 may be asserted, followed by a second row, followed by a third row, and so on until each row of display modules 710 have had their corresponding Vreset 895 asserted. Likewise, Vrow 830 for rows of display modules 710 can also be asserted row-by-row. Vrow 830 for one row may be asserted while Vreset 895 for another row is also asserted at the same or similar times. Vbias 896 may also be asserted row-by-row.
In some applications, each row of display modules 710 is provided Vrow 830, Vreset 895, and Vbias 896 from separate IGD 801, IRD 802, and IBD 803 circuits, respectively.
Driver chip 804 in
In
Though not shown, other pairs of rows (e.g., rows m+1 and m+3) may be provided corresponding voltages for Vbias electrodes 855 of the display units 750 of display modules 710 of the rows from other IBDs 803 similar to the implementation shown in
Some of the functionality of the integrated bias driver circuit in
In
Vbias(m) 920 and Vbias(m+2) 925 can be asserted based on a timing relationship with the assertion of Vrow 830 and Vreset 895 for rows m and m+2, as well as other signals from prior and subsequent rows.
For example, In
Next, at times 1165 and 1170, Vrow(m) 1115 and Vrow(m+2) 1120 can be asserted, respectively, by an IGD to provide a voltage to Vd electrode 860 of display units 750 of display modules 710 in rows m and m+2. The IGD providing Vrow 830 voltages for row m+4 of display units 750 can also assert CaG(m+4) when Vrow 830 is asserted for row m+4. CaG(m+4) is also provided as an input to IBD 803 as a trigger to transition Vbias(m) 920 and Vbias(m+2) 925 from BIASM to either BIASH or BIASL. For example, at time 1175 in
As a result, transitioning Vbias(m) 920 and Vbias(m+2) 925 to BIASM at time 1150 based on the assertion of CaR(m−4) 915 (i.e., before the assertion of Vreset(m) 1105) and transitioning Vbias(m) 920 and Vbias(m+2) 925 based on the assertion of CaG(m+4) 930 (i.e., after the assertion of Vrow(m+2) 1120) may allow rows m and m+2 to be reset and a voltage provided to the corresponding Vd electrodes 860 such that IBD 803 can provide both Vbias(m) 920 and Vbias(m+2) 925 with the same circuit at the same or similar times, resulting in fewer TFTs. That is, ensuring that Vbias(m) 920 and Vbias(m+2) 925 transition to a voltage of BIASM before any one of them is reset (through assertions of Vreset(m) 1105 and Vreset(m+2) 1110), and transition Vbias(m) 920 and Vbias(m+2) 925 from BIASM to BIASH or BIASL after rows m and m+2 receive the row signals (through assertions of Vrow(m) 1115 and Vrow(m+2) 1120) allows for the IBD to provide Vbias(m+2) 925 and Vbias(m) 920 together.
The number of TFTs used to implement IGDs and IRDs in
The circuit schematic of
In
In more detail,
Additionally, since CKL11470 is high at time 1605, transistors T2, U2, and V2 in output buffers 1485a-c turn on, charging output buffer charge nodes Qbuffer 1515a-c with the voltage of charge node Q 1450, and therefore, output buffer charge nodes Qbuffer 1515a-c also go high with charge node Q 1450. As a result, charge node Q 1450 and output buffer charge nodes Qbuffer 1515a-c are all charged based on the assertion of the carry signal (CaG(m−4) 1310 in
Additionally, transistors T3, U3, and V3 in output buffers 1485a-c also turn on because, as previously discussed, output buffer charge nodes Qbuffer 1515a-c are all high. As a result, the voltages on CK11465, CK21475, and CKL01480 are provided on output buffer output nodes 1510a-c, which results in Vrow(m) 1320, Vrow(m+2) 1325, and CaG(m+2) 1305 all being low because CK11465, CK21475, and CKL01480 are all low at time 1605. Transistors T4, U4, and V4 of output buffers 1485a-c are turned off at time 1605 because node QB 1455 of the shared latch is low, as previously discussed.
Next, at time 1610, CKL11470 goes low, resulting in both transistors N1 and N2 of the shared latch in
At time 1610, CK21475 and CKL01480 are also low. Accordingly, transistor U1 in output buffer 1485b in
Next, at time 1615, CK11465 goes low and CKL01480 goes high. As a result, transistor T1 of output buffer 1485a in
In some implementations, asserting CaG(m) 1305 at a time between the assertions of Vrow(m) 1320 and Vrow(m+2) 1325 can reduce the number of clock signals used to assert the outputs of output buffer 1485a-c.
Next, at time 1625, CKL11470 goes high, resulting in transistors N1 and N2 in
Output buffers 1485a-c include capacitors 1505a-c that may benefit bootstrapping. However, in some implementations, capacitors 1505a-c may be removed. In some implementations, some output buffers may include a capacitor, but other output buffers may not. For example, output buffer 1485a may include capacitor 1505a, but output buffers 1485b and 1485c may not include capacitors 1505b and 1505c, respectively.
Using the shared latch with multiple output buffers 1485a-c can reduce the number of TFTs, for example, by 20%.
The display device 40 includes a housing 41, a display 30, an antenna 43, a speaker 45, an input device 48 and a microphone 46. The housing 41 can be formed from any of a variety of manufacturing processes, including injection molding, and vacuum forming. In addition, the housing 41 may be made from any of a variety of materials, including, but not limited to: plastic, metal, glass, rubber and ceramic, or a combination thereof. The housing 41 can include removable portions (not shown) that may be interchanged with other removable portions of different color, or containing different logos, pictures, or symbols.
The display 30 may be any of a variety of displays, including a bi-stable or analog display, as described herein. The display 30 also can be configured to include a flat-panel display, such as plasma, EL, OLED, STN LCD, or TFT LCD, or a non-flat-panel display, such as a CRT or other tube device. In addition, the display 30 can include an IMOD-based display, as described herein.
The components of the display device 40 are schematically illustrated in
The network interface 27 includes the antenna 43 and the transceiver 47 so that the display device 40 can communicate with one or more devices over a network. The network interface 27 also may have some processing capabilities to relieve, for example, data processing requirements of the processor 21. The antenna 43 can transmit and receive signals. In some implementations, the antenna 43 transmits and receives RF signals according to the IEEE 16.11 standard, including IEEE 16.11(a), (b), or (g), or the IEEE 802.11 standard, including IEEE 802.11a, b, g, n, and further implementations thereof. In some other implementations, the antenna 43 transmits and receives RF signals according to the Bluetooth® standard. In the case of a cellular telephone, the antenna 43 can be designed to receive code division multiple access (CDMA), frequency division multiple access (FDMA), time division multiple access (TDMA), Global System for Mobile communications (GSM), GSM/General Packet Radio Service (GPRS), Enhanced Data GSM Environment (EDGE), Terrestrial Trunked Radio (TETRA), Wideband-CDMA (W-CDMA), Evolution Data Optimized (EV-DO), 1×EV-DO, EV-DO Rev A, EV-DO Rev B, High Speed Packet Access (HSPA), High Speed Downlink Packet Access (HSDPA), High Speed Uplink Packet Access (HSUPA), Evolved High Speed Packet Access (HSPA+), Long Term Evolution (LTE), AMPS, or other known signals that are used to communicate within a wireless network, such as a system utilizing 3G, 4G or 5G technology. The transceiver 47 can pre-process the signals received from the antenna 43 so that they may be received by and further manipulated by the processor 21. The transceiver 47 also can process signals received from the processor 21 so that they may be transmitted from the display device 40 via the antenna 43.
In some implementations, the transceiver 47 can be replaced by a receiver. In addition, in some implementations, the network interface 27 can be replaced by an image source, which can store or generate image data to be sent to the processor 21. The processor 21 can control the overall operation of the display device 40. The processor 21 receives data, such as compressed image data from the network interface 27 or an image source, and processes the data into raw image data or into a format that can be readily processed into raw image data. The processor 21 can send the processed data to the driver controller 29 or to the frame buffer 28 for storage. Raw data typically refers to the information that identifies the image characteristics at each location within an image. For example, such image characteristics can include color, saturation and gray-scale level.
The processor 21 can include a microcontroller, CPU, or logic unit to control operation of the display device 40. The conditioning hardware 52 may include amplifiers and filters for transmitting signals to the speaker 45, and for receiving signals from the microphone 46. The conditioning hardware 52 may be discrete components within the display device 40, or may be incorporated within the processor 21 or other components.
The driver controller 29 can take the raw image data generated by the processor 21 either directly from the processor 21 or from the frame buffer 28 and can re-format the raw image data appropriately for high speed transmission to the array driver 22. In some implementations, the driver controller 29 can re-format the raw image data into a data flow having a raster-like format, such that it has a time order suitable for scanning across the display array 30. Then the driver controller 29 sends the formatted information to the array driver 22. Although a driver controller 29, such as an LCD controller, is often associated with the system processor 21 as a stand-alone Integrated Circuit (IC), such controllers may be implemented in many ways. For example, controllers may be embedded in the processor 21 as hardware, embedded in the processor 21 as software, or fully integrated in hardware with the array driver 22.
The array driver 22 can receive the formatted information from the driver controller 29 and can re-format the video data into a parallel set of waveforms that are applied many times per second to the hundreds, and sometimes thousands (or more), of leads coming from the display's x-y matrix of display elements.
In some implementations, the driver controller 29, the array driver 22, and the display array 30 are appropriate for any of the types of displays described herein. For example, the driver controller 29 can be a conventional display controller or a bi-stable display controller (such as an IMOD display element controller). Additionally, the array driver 22 can be a conventional driver or a bi-stable display driver (such as an IMOD display element driver). Moreover, the display array 30 can be a conventional display array or a bi-stable display array (such as a display including an array of IMOD display elements). In some implementations, the driver controller 29 can be integrated with the array driver 22. Such an implementation can be useful in highly integrated systems, for example, mobile phones, portable-electronic devices, watches or small-area displays.
In some implementations, the input device 48 can be configured to allow, for example, a user to control the operation of the display device 40. The input device 48 can include a keypad, such as a QWERTY keyboard or a telephone keypad, a button, a switch, a rocker, a touch-sensitive screen, a touch-sensitive screen integrated with the display array 30, or a pressure- or heat-sensitive membrane. The microphone 46 can be configured as an input device for the display device 40. In some implementations, voice commands through the microphone 46 can be used for controlling operations of the display device 40.
The power supply 50 can include a variety of energy storage devices. For example, the power supply 50 can be a rechargeable battery, such as a nickel-cadmium battery or a lithium-ion battery. In implementations using a rechargeable battery, the rechargeable battery may be chargeable using power coming from, for example, a wall socket or a photovoltaic device or array. Alternatively, the rechargeable battery can be wirelessly chargeable. The power supply 50 also can be a renewable energy source, a capacitor, or a solar cell, including a plastic solar cell or solar-cell paint. The power supply 50 also can be configured to receive power from a wall outlet.
In some implementations, control programmability resides in the driver controller 29 which can be located in several places in the electronic display system. In some other implementations, control programmability resides in the array driver 22. The above-described optimization may be implemented in any number of hardware and/or software components and in various configurations.
As used herein, a phrase referring to “at least one of” a list of items refers to any combination of those items, including single members. As an example, “at least one of: a, b, or c” is intended to cover: a, b, c, a-b, a-c, b-c, and a-b-c.
The various illustrative logics, logical blocks, modules, circuits and algorithm steps described in connection with the implementations disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. The interchangeability of hardware and software has been described generally, in terms of functionality, and illustrated in the various illustrative components, blocks, modules, circuits and steps described above. Whether such functionality is implemented in hardware or software depends upon the particular application and design constraints imposed on the overall system.
The hardware and data processing apparatus used to implement the various illustrative logics, logical blocks, modules and circuits described in connection with the aspects disclosed herein may be implemented or performed with a general purpose single- or multi-chip processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, or, any conventional processor, controller, microcontroller, or state machine. A processor also may be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. In some implementations, particular steps and methods may be performed by circuitry that is specific to a given function.
In one or more aspects, the functions described may be implemented in hardware, digital electronic circuitry, computer software, firmware, including the structures disclosed in this specification and their structural equivalents thereof, or in any combination thereof. Implementations of the subject matter described in this specification also can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions, encoded on a computer storage media for execution by, or to control the operation of, data processing apparatus.
If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. The steps of a method or algorithm disclosed herein may be implemented in a processor-executable software module which may reside on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that can be enabled to transfer a computer program from one place to another. A storage media may be any available media that may be accessed by a computer. By way of example, and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that may be used to store desired program code in the form of instructions or data structures and that may be accessed by a computer. Also, any connection can be properly termed a computer-readable medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above also may be included within the scope of computer-readable media. Additionally, the operations of a method or algorithm may reside as one or any combination or set of codes and instructions on a machine readable medium and computer-readable medium, which may be incorporated into a computer program product.
Various modifications to the implementations described in this disclosure may be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other implementations without departing from the spirit or scope of this disclosure. Thus, the claims are not intended to be limited to the implementations shown herein, but are to be accorded the widest scope consistent with this disclosure, the principles and the novel features disclosed herein. Additionally, a person having ordinary skill in the art will readily appreciate, the terms “upper” and “lower” are sometimes used for ease of describing the figures, and indicate relative positions corresponding to the orientation of the figure on a properly oriented page, and may not reflect the proper orientation of, e.g., an IMOD display element as implemented.
Certain features that are described in this specification in the context of separate implementations also can be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation also can be implemented in multiple implementations separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.
Similarly, while operations are depicted in the drawings in a particular order, a person having ordinary skill in the art will readily recognize that such operations need not be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Further, the drawings may schematically depict one more example processes in the form of a flow diagram. However, other operations that are not depicted can be incorporated in the example processes that are schematically illustrated. For example, one or more additional operations can be performed before, after, simultaneously, or between any of the illustrated operations. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products. Additionally, other implementations are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results.
Some of the examples of circuit schematics described herein use NMOS transistors. However, PMOS transistors can also be used.
Additionally, the circuits described in the examples as driver circuits for displays. However, the circuits can also be used in other scenarios (i.e., other than displays).
