The present invention relates in general to drivers for gas discharge lamps. As is commonly known, a driver for a gas discharge lamp serves to feed the gas discharge lamp with the required amount of current, and receives power itself from AC mains. Conventionally, such a driver comprises three stages: a rectifier and upconverter for converting the AC input voltage to a higher DC output voltage, a downconverter for converting said DC voltage to a lower voltage but higher current, and finally a commutator switching the DC current for the lamp at a relatively low frequency. In a more recent design, the last two stages (i.e. downconverter and commutator) have been integrated into a single stage, referred to as forward commutating stage. Such an integrated stage offers advantages, such as fewer components and a smaller size.
In such a forward commutating stage, one can distinguish between a half-bridge type and a full-bridge type. However, such a forward commutating stage always has at least one chain of two series-connected MOSFET switches, wherein the gas discharge lamp to be driven is connected to the node between said two switches.
During steady state operation, the lamp current in principle has a substantially constant magnitude, but the lamp current changes direction at regular intervals. A full lamp period comprises a first time interval where the lamp current has one direction, and a second time interval where the lamp current has the reverse direction. During each of these intervals, one of said two chain switches is active, while the other is passive. Conventionally, the active switch is switched open (non-conductive state) and closed (conductive state) at a relatively high frequency. During the closed condition of this active switch, current for a lamp circuit is conducted by this active switch and increases in magnitude. During the open condition of this active switch, the lamp circuit current is conducted by a diode in parallel with the other switch, i.e. the passive switch. This diode may be the internal body diode of the MOSFET switch itself. However, this internal body diode behaves badly at relatively high frequencies, especially at the transition from the conductive state to the non-conductive state, which causes relatively much loss of energy. In order to improve this switching behavior, it has already been proposed to add two separate diodes for each MOSFET switch, one diode being series-connected and the other being anti-parallel connected. Then, when the active MOSFET is opened, the lamp circuit current is conducted by said anti-parallel diode, while said series-connected diode blocks the current through said passive switch. However, this design involves two additional components for each MOSFET, while additionally the series-connected diode contributes to energy losses when its corresponding MOSFET is the active MOSFET.
It is a general objective of the present invention to provide an improved driver for a gas discharge lamp. Particularly, it is an objective of the present invention to provide an improved forward commutator device for a gas discharge lamp.
In a first aspect, the present invention is based on the recognition that a MOSFET switch can conduct current in two directions. The present invention utilizes this recognition by using the passive MOSFET itself for conducting the lamp circuit current during those moments that the active MOSFET is open.
Conventionally, the active MOSFET is closed (i.e.: switched to its conductive state, also indicated as the ON state) when the decreasing lamp circuit current reaches a first current level, and this active MOSFET is opened (i.e.: switched to its non-conductive state, also indicated as the OFF state) when the increasing lamp circuit current through the active MOSFET reaches a second, higher current level. Conventionally, the first current level is higher than zero. However, it is advantageous if the active MOSFET would be switched ON at approximately zero lamp current, because then switching losses are minimal. This is especially the case when, in accordance with the above-mentioned first aspect of the present invention, the passive MOSFET is switched ON when the active MOSFET is switched OFF. Thus, there is a need for an accurate current sensor which accurately indicates zero-crossings of the lamp circuit current. It is, of course, possible to use a measuring resistor in series with the lamp circuit current and to measure the voltage across this measuring resistor, but this will involve relatively large resistive losses.
Therefore, it is a further objective of the present invention to provide a relatively simple, accurate current sensor which involves relatively little losses.
Ideally, switching takes place when the lamp circuit current is exactly zero. However, generating a detector signal, sending this detecting signal to a control device for the MOSFET switches, and switching the MOSFET switches, causes a time delay between the moment of detection and the moment of actual switching. Therefore, it is a further objective to provide a zero crossing detector which can already provide a sensor signal shortly before the actual zero crossing.
In accordance with a second aspect of the present invention, a zero-crossing current detector comprises a small transformer having a first transformer winding connected in series with the lamp current. The small transformer is already saturated at relatively small primary currents; then, at the secondary side, no signal will be provided. Only at relatively small currents, i.e. around the zero crossings, the transformer is out of saturation and a signal is provided at its secondary winding.
As mentioned above, the lamp current changes direction at regular intervals. This is referred to as the commutation moment. At the commutation moment, the active MOSFET becomes the passive MOSFET, while the passive MOSFET becomes the active MOSFET. In the state of the art, the commutation moment is determined independently of the actual status of the lamp current. This means that the actual commutation moment is at random with respect to the actual current magnitude, which may lead to undesirable lamp behavior. It is a further objective of the present invention to improve lamp behavior by a better control of the commutation moment. According to a further aspect of the present invention, the commutation moment is selected in synchronization with the high frequency switching of the MOSFET switches. More particularly, the commutation moment is selected to substantially coincide with a zero crossing.
These and other aspects, features and advantages of the present invention will be further explained by the following description of a preferred embodiment of a driver according to the present invention with reference to the drawings, in which same reference numerals indicate same or similar parts, and in which:
A conventional driver has a second stage or downconverter 20, having an input 21 connected to the output 12 of the pre-conditioner 10, and having an output 22 providing a DC output current at a voltage level lower than the output voltage of the pre-conditioner 10. In principle, this DC output current of the downconverter 20 might be provided directly to a lamp 9; however, gas discharge lamps need to be driven in general at an alternating current. For this purpose, conventionally a commutator 30 is present, having an input 31 receiving the DC current generated by the downconverter 20, and providing an alternating DC current at its output 32.
The commutating forward driver 50, hereinafter abbreviated as CFD 50, has two input terminals 51a and 51b for connection to a preconditioner, the first input terminal 51a being maintained at a voltage level higher than the second input terminal 51b, the voltage difference typically being about 400 V. Furthermore, the CFD 50 has two output terminals 52a and 52b for connecting a lamp 9.
A body diode of the MOSFETS 61, 62 is shown at 63, 64, respectively.
The CFD 50 comprises a first MOSFET switch 61 having its source and drain terminals connected between the first input terminal 51a and a first node P, and a second MOSFET switch 62 having its source and drain terminals connected between said first node P and the second input terminal 51b. The CFD 50 further comprises a first capacitor 71 connected between the first input terminal 51a and a second node Q, and a second capacitor 72 connected between this second node Q and the second input terminal 51b. Between said two nodes P and Q, a coil 73 is connected in series with a lamp circuit 99. Lamp output terminals are indicated at 52a and 52b. Said lamp circuit 99 comprises the lamp 9 arranged in series with an ignitor coil, and a filter capacitor arranged in parallel with said series arrangement. Current applied to said lamp circuit 99 will be indicated as lamp circuit current ILC. Said ignitor coil and filter capacitor serve to smoothen the current through the lamp 9, indicated as lamp current IL.
Furthermore, the CFD 50 comprises a control unit 80, having a first output 81 coupled to the gate terminal of the first MOSFET 61, and a second output 82 coupled to the gate terminal of the second MOSFET 62. The control unit 80 is designed to open and close the MOSFET switches 61 and 62 by supplying control signal S1 and S2 at its outputs 81 and 82, as will be clear to a person skilled in the art. Hereinafter, a signal S1, S2 causing a corresponding MOSFET switch to close (conductive state; ON) will be indicated as logical value “1”, whereas a signal S1, S2 causing a corresponding MOSFET switch to open (non-conductive state; OFF) will be indicated as logical value “0”.
The operation of the half-bridge CFD 50 will now be explained, while also referring to
At a certain switching time tH, the control unit 80 changes its first output control signal S1 such that the first MOSFET switches to its non-conductive state. At that moment, the lamp circuit current ILC has a certain magnitude, indicated as IHIGH in
At a later moment in time, indicated as tL in
The first switch 61, which conducts the lamp circuit current during the main phase 43, will also be indicated as the active switch. The other switch 62 will be indicated as passive switch.
In the state of the art, during the first interval, the first switch 61 or active switch 61 is repeatedly switched on and off, while the passive switch 62 remains switched off. In one possible embodiment of the state of the art CFD 50, the coil-driven current I44 flows through the second body diode 64 of the passive second MOSFET 62, as indicated in
In another possible embodiment of the prior art CFD 50, a first external diode 91 is connected in series with the first MOSFET 61, its anode being coupled to the first input terminal 51a and its cathode being coupled to the MOSFET 61. Similarly, a second diode 92 is connected in series with the second MOSFET 62. A third external diode 93 is connected between the first input terminal 51a and the first node P, its cathode being connected to first input terminal 51a and its anode being connected to first node P. Similarly, a fourth external diode 94 is connected between first node P and second input terminal 51b. In such an embodiment, the second diode 92 prevents the flow of coil-driven current through second body diode 64, and the coil-driven current I44 now flows through fourth diode 94, as indicated by arrow A2b.
As discussed in the introduction, both prior art solutions have disadvantages.
To complete the description of the operation of CFD 50, the switching of first MOSFET 61 is repeated continuously until a commutation moment. At such a moment, the first commutation interval 41 ends and the second commutation interval 42 starts (see
It is noted that this timing as illustrated in
An important advantage obtained by using the low-resistive MOSFET channel for conducting current from source to drain is the fact that switching of the MOSFET is much faster than switching of its body diode. Specifically, the MOSFET can be switched off much faster than its body diode, or much faster than any other diode for that matter, so reversed recovery losses are eliminated.
The switching principle proposed by the present invention, based on the use of the MOSFET channel from source to drain, can already be used in principle if the second or lower current level ILOW has an arbitrary value above zero. However, full advantage of the inventive idea is achieved if the lower current level ILOW is equal to zero. This mode of operating a gas discharge lamp is indicated as critical discontinuous mode. In order to be able to accurately switch when the lamp current is close to zero, the inventive CFD 150 preferably comprises a current sensor 100, as illustrated in
The preferred embodiment of a current sensor 100 proposed by the present invention and as illustrated in
The transformer 110, preferably of the toroidal type, is very small, so that its core is saturated even at a relatively small current through its primary winding 111. In such a saturated condition, an increase or decrease of the lamp current through primary winding 111 will not result in a change of magnetic flux within this core, and therefore will not result in any current in the secondary winding 112. However, as soon as the current through the primary winding 111 approaches zero, the transformer 110 comes out of saturation and is capable of generating a voltage peak between the two ends of its secondary winding 112. Depending on the sign of this voltage peak with reference to the central terminal and therefore with reference to the second output terminal 120b, the first diode 113 or the second diode 114 directs this voltage peak via the resistor 115 to the first output terminal 120a. Preferably, a zener diode 116 is connected between the two output terminals 120a and 120b, clamping the voltage level of the output pulse to a desired logical value and thus preventing that the voltage at the first output terminal 120a can rise too high.
During this experiment, a current source was connected to the primary winding 111, the current through the primary winding 111 being indicated as input current IIN in
It is noted that the actual width of the voltage pulse depends, inter alia, on the specific design of the transformer 110. This allows a designer to design the properties of the transformer to suit the requirements of the driver concerned, as will be clear to a person skilled in the art.
It is noted that the switching at time tH from increasing current to decreasing current can be triggered by the current reaching a predetermined current level. Preferably, however, this switching is time-based, in that the first operation phase or main phase 43 has a predetermined duration t43.
A further aspect of the present invention relates to the commutation moments, i.e. the transition from first commutation phase 41 to second commutation phase 42 and vice versa in
A further objective of the present invention is to also overcome this drawback.
To this end, the control unit 180 of the inventive driver 150 preferably is designed to synchronize commutation with zero crossings of the lamp circuit current ILC, i.e. to switch operation from first phase to second phase and vice versa at a moment coinciding with a zero crossing of the lamp circuit current ILC.
An exemplary embodiment of a control unit 180 which provides all the above-mentioned advantages is schematically illustrated in
The design and operation of this exemplary embodiment will now be explained with reference to
The control unit 180 comprises a commutation clock generator 210, having an output 211, providing a square-wave commutation clock signal φCOMM indicating the commutation phases of the lamp current. Typically, the square-wave signal φCOMM has a frequency in the order of about 100 Hz. Alternatively, the control unit 180 may have a clock input terminal (not shown) to receive a commutation clock signal from an external commutation clock generator (not shown).
Since clock generator devices are commonly known, and a conventional clock generator device may be used in implementing the control unit of the present invention, it is not necessary here to discuss the design and operation of such a device in more detail.
The control unit 180 further comprises a first D-type flip-flop device 220, having a signal input 221, a trigger input 222, a set input 225, a reset input 226, a first output 223 providing a first output signal Q223, and a second output 224 providing a second output signal Q224. Furthermore, the control unit 180 comprises a second D-type flip-flop device 230, having a signal input 231, a trigger input 232, a set input 235, a reset input 236, a first output 233 providing a first output signal Q233, and a second output 234 providing a second output signal Q234.
Each flip-flop device 220, 230 has two operative states: in a first operative state, which will be indicated as the H-state, the first output signal Q223, Q233 is logical HIGH while the second output signal Q224, Q234 is logical LOW, whereas in a second operative state, which will be indicated as the L-state, the first output signal Q223, Q233 is logical LOW while the second output signal Q224, Q234 is logical HIGH. Each flip-flop device 220, 230 is designed to operate as follows. As long as the set and reset inputs are both LOW, the operative state is maintained until a trigger signal is received at the trigger input. If a trigger signal is received at the trigger input, an operative state will be set such that the first output takes the logical value of an input signal which is received at that moment at the signal input.
Since flip-flop devices are commonly known, and a conventional flip-flop device may be used in implementing the control unit of the present invention, it is not necessary here to discuss the design and operation of such device in more detail.
The control unit 180 further comprises a first timer device 240, having a trigger input 241 and an output 242 providing a first timer output signal T242. Furthermore, the control unit 180 comprises a second timer device 250, having a trigger input 251 and an output 252 providing a second timer output signal T252. Each timer device has two operative states: in a first operative state, which will be indicated as the L-state, the timer output signal is LOW, whereas in a second operative state, which will be indicated as the H-state, the timer output signal is HIGH. Each timer device is designed to operate as follows. Normally, each timer device is in its L-state. Each timer device, in response to a trigger signal received at its trigger input, waits a predetermined timer period, and then issues a brief HIGH-pulse at its output. The duration of said predetermined timer period has a predetermined value.
Since timer devices are commonly known, and conventional timer devices may be used in implementing the control unit of the present invention, it is not necessary here to discuss the design and operation of such device in more detail.
The control unit 180 further comprises preferably, as shown, a current level detector 260 having an input 261 and an output 262 for providing a current intensity detector signal. The current detector 260 is designed for sensing the lamp current intensity, and for comparing the sensed lamp current intensity with a predetermined high-level threshold. As long as the lamp current intensity is below said predetermined high-level threshold, the current detector 260 is in a first operative state, which will be indicated as the L-state, wherein the current intensity detector signal is LOW. If the lamp current intensity rises above said predetermined high-level threshold, the current detector 260 enters a second operative state, which will be indicated as the H-state, wherein the current intensity detector signal is HIGH.
Since current level detectors are commonly known, and a conventional current level detector may be used in implementing the control unit of the present invention, it is not necessary here to discuss the design and operation of such a current level detector in more detail.
The control unit 180 further comprises a first XNOR device 280 having a first input 281, a second input 282, and an output 283 providing a first control output signal S1, as well as a second XNOR device 290 having a first input 291, a second input 292, and an output 293 providing a second control output signal S2. Each XNOR device has two operative states: in a first operative state, which will be indicated as the L-state, the corresponding output signal S1, S2 is LOW, whereas in a second operative state, which will be indicated as the H-state, the corresponding output signal S1, S2 is HIGH. Each XNOR device is designed to be in its L-state if and when the input signals received at its two inputs have mutually different logical values, and to be in its H-state if and when the input signals received at its two inputs have mutually the same logical value.
Since XNOR devices are commonly known, and a conventional XNOR device may be used in implementing the control unit of the present invention, it is not necessary here to discuss the design and operation of such device in more detail.
Basically, the first flip-flop 220 determines the transition moments tH and tL between the first operational phase 43 and the second operational phase 44. If the first flip-flop 220 is in its H-state, the driver 150 is in its first operational phase 43 (
The first flip-flop 220 enters its H-state at a zero crossing of the lamp current or when a predetermined maximum duration of the L-state has passed, whichever happens first, whereas the first flip-flop 220 enters its L-state at a high level crossing of the lamp current or when a predetermined maximum duration of the H-state has passed, whichever happens first.
In order to assure that the first flip-flop 220 enters its H-state whenever the lamp current crosses zero, the signal input 221 of the first flip-flop 220 is connected to a constant HIGH level source. The trigger input 222 of the first flip-flop 220 is connected to the sensor input 183 of the control unit 180, and thus receives the output signal of the current sensor 100.
The first operational phase 43 may end after a predetermined time, as determined by the second timer 250, or when the lamp circuit current reaches a predetermined current level. The second timer 250 is responsive to the start of the first operational phase 43, and issues a signal pulse at a predetermined time after the start of the first operational phase 43 if by then the circuit current has not reached said predetermined current level yet. The output 252 of the second timer 250 is connected to a first input 271 of an OR gate 270 whose output 273 is connected to the reset input 226 of the first flip-flop 220. Thus, when the second timer 250 emits its signal pulse, the first flip-flop 220 is reset and enters its L-state (moment tH).
The current level detector 260 senses the lamp circuit current, and its output goes HIGH when the lamp circuit current reaches said predetermined current level before said predetermined time has passed. The output 262 of the current level detector 260 is connected to a second input 272 of said OR gate 270. Thus, when the output 262 of the current level detector 260 goes HIGH, the first flip-flop 220 is reset and enters its L-state (moment tH).
The first timer 240 is responsive to the start of the second operational phase 44, and issues a signal pulse at a predetermined time after the start of the second operational phase 44 if by then the current has not passed zero yet. The output 242 of the first timer 240 is connected to the set input 225 of the first flip-flop 220. Thus, when the first timer 240 emits its signal pulse, the first flip-flop 220 is set and enters its H-state (moment tL).
The first XNOR device 280 has its first input 281 coupled to receive the second output signal Q224 of the first flip-flop device 220. The output 283 of the first XNOR device 280 is coupled to the first output 81 of the control unit 180 to provide its output signal S1 as a control signal for the first switch 61. At its second input 282, the first XNOR device 280 receives the commutation signal φCOMM of the commutation clock generator 210. Thus, said output signal S1 is equal to the second output signal Q224 of the first flip-flop device 220, or is inverted, depending on the commutation period. However, the commutation signal φCOMM is not connected directly to the first XNOR device 280 but via the second flip-flop 230 in order to effect a delay until the current crosses zero.
More particularly, the second flip-flop 230 has its signal input 231 connected to the output 211 of the commutation clock generator 210, and has its trigger input 232 connected to the first output 223 of the first flip-flop 220. Thus, at each transistion from the L-state to the H-state of the first flip-flop 220, which will normally take place at a zero crossing of the lamp current, the second flip-flop 230 will enter a state determined by the status of the commutation clock signal φCOMM.
In accordance with the present invention, the second output signal S2 should always be the opposite of the first output signal S1. This can be effected by inverting the first output signal S1 in order to generate the second output signal S2. However, this may involve a timing delay. Therefore, preferably, and as illustrated in
It is noted that it is desirable to assure a brief period of dead time, i.e. a period when both signals S1 and S2 are low, between successive switching periods, in order to avoid possible periods that signals S1 and S2 are high, and thus to prevent that switches 61 and 62 would conduct simultaneously. However, normally this functionality is implemented in the final MOSFET driver, and is not shown here.
Reference is now made to
Let us assume that, initially, the commutation clock signal φCOMM is logical HIGH, that the first flip-flop device 220 is in its L-state (Q223 is LOW, Q224 is HIGH), that the second flip-flop device 230 is in its H-state (Q233 is HIGH, Q234 is LOW), and that the first timer device 250 is in its L-state (T252 is LOW). Then, the first output control signal S1 is LOW and the second output control signal S2 is HIGH, and the lamp current IL decreases (time t1 in
When the lamp circuit current ILC reaches zero, the detector signal SD shows a detection peak (time t2). Triggered by this detection peak, the first flip-flop device 220 enters its H-state (Q223 becomes HIGH, Q224 becomes LOW), so that the first output control signal S1 becomes HIGH and the second output control signal S2 becomes LOW. Thus, as explained earlier, the lamp circuit current ILC rises.
Due to by this rising lamp circuit current ILC, the current sensor 100 generates a second detection peak, as illustrated in
If the first timer device 250 detects that the predetermined ON-time has passed, or the current detector 260 detects that the lamp circuit current ILC reaches a predetermined current level, the first flip-flop device 220 is reset to its L-state (t3 in
This cycle is repeated for as long as the commutation clock signal φCOMM is logical HIGH. If we now assume that the commutation clock signal φCOMM changes from HIGH to LOW, indicating a transition from first commutation phase 41 to second commutation phase 42 in
At that moment, in response to the detector signal SD received at its trigger input 222, the first flip-flop 220 will enter its H-state so that its first output Q223 becomes HIGH, which triggers the second flip-flop 230 to enter its L-state, so that now its first output Q233 becomes low and its second output Q234 becomes HIGH. As a result, the two input signals of each XNOR device 280, 290 change virtually simultaneously, so that the output signal of each XNOR device 280, 290 will be maintained unchanged. In this case, the first output control signal S1 stays LOW and the second output control signal S2 stays HIGH, and the lamp circuit current ILC continues to decrease, i.e. the current magnitude rises but the direction of the current has now been reversed.
This condition of rising lamp circuit current ILC with reversed direction, again corresponding to the main phase 43 of
Thus, the important advantage is achieved that the actual commutation moment (t5) is delayed with respect to the target commutation moment (t4) as indicated by the commutation clock signal φCOMM, such that the actual commutation moment (t5) substantially coincides with a zero crossing of the lamp circuit current ILC.
It should be clear to a person skilled in the art that the present invention is not limited to the exemplary embodiments discussed above, but that various variations and modifications are possible within the protective scope of the invention as defined in the appending claims.
For instance, in the above it has been discussed that in each commutation interval the lamp circuit current varies but continuously has the same direction, i.e. the main operational phase 43 is started before the lamp circuit current ILC reaches zero or, ideally, exactly when the lamp circuit current ILC is equal to zero. However, it may be acceptable to start the main operational phase 43 slightly later, so that the lamp circuit current ILC has passed zero, i.e. effectively has changed direction and in fact its current magnitude is increasing again. In order to take this into account, it will be said that, in the main operational phase 43, the circuit current ILC has a continuously rising level and a substantially constant direction, and that, in the second operational phase 44, the circuit current ILC has a continuously decreasing level and a substantially constant direction.
With reference to
Furthermore, delaying the actual commutation moment so as to make it substantially coincide with a zero crossing of the lamp circuit current ILC has been discussed in conjunction with a preferred embodiment also implementing another important aspect of the present invention, i.e. the simultaneous but opposite driving of the switches 61 and 62. However, delaying the actual commutation moment so as to make it substantially coincide with a zero crossing of the lamp circuit current ILC can also be implemented in a prior art device where only one switch is active and where the “return” current flows through the body diode (64; current A2a in
Furthermore, it is noted that in the branch between nodes P and Q, the order of the lamp 9, the inductor 73 and the detector 100 may be chosen as desired.
Number | Date | Country | Kind |
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02077984.9 | Jul 2002 | EP | regional |
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/IB03/03013 | 7/1/2003 | WO | 1/21/2005 |