The present invention relates to a driver for a plasma display panel. The invention relates more especially to a driver structure that allows the current loops to be reduced during the sustain of the display cells.
Currently, there are plasma display panel (hereafter referred to as PDP) drivers whose elements are divided between two boards, the elements for controlling the sustain electrodes Ys of the display cells being disposed on a first board and the elements for controlling the address-sustain electrodes Yas of the display cells being disposed on a second board. This case is illustrated in
In a same manner, the means for controlling the sustain electrodes Yas of the display cells are assembled on a second board B2. Two switches I3 and I4 are connected in series between a power supply terminal T3 receiving the voltage Vs and a terminal T4 connected to ground. The intermediate point situated between the switches I3 and I4 is connected to a connector CN2 accessing the electrodes Yas of the display cells. In addition, a power-supply and decoupling capacitor C2 is connected across the terminals T3 and T4.
In the sustain phase, the switches I1 and I4 are firstly closed, then the switches I2 and I3 are closed.
In order to reduce the size of these current loops, a known solution is to regroup the 2 parts of the driver onto a single board. This case is illustrated in
The object of the invention is to reduce the size of the current loops in the driver in order to reduce the electromagnetic emissions.
The invention relates to a driver for a plasma display panel comprising a sustain circuit designed to deliver a first sustain pulse signal to the sustain electrodes of the cells of the said display and a second sustain pulse signal to the address-sustain electrodes of the display, the said sustain circuit comprising a first switch connected between a first connector accessing the sustain electrodes of the display cells and a power supply terminal receiving the peak voltage of the said first and second sustain pulse signals, a second switch connected between the said first access connector and ground, a third switch connected between a second connector accessing the address-sustain electrodes of the display cells and the said power supply terminal and a fourth switch connected between the said second access connector and ground, characterized in that it is mounted on a single board and in that the said first and fourth switches, and similarly the said second and third switches, are disposed next to one another in order to reduce the size of the current loops during the sustain of the display cells.
Advantageously, the said first and second access connectors are disposed at the periphery of the board, on the same edge next to one another in order to further reduce the size of the current loops.
According to a preferred embodiment, one of the access connectors is disposed on the front face of the said board and the other on the back face.
According to another embodiment, the said first and second access connectors are incorporated into a single connector.
The invention will be better understood upon reading the description that follows, presented as a non-limiting example and with reference to the appended figures, among which:
According to the invention, the position of the elements in the driver of the PDP is optimized in order to reduce the size of the loops in all three dimensions.
In these figures, the switches I1 and I4 are positioned next to one another, at the same level on the x axis, so as to reduce the loop of the current flowing through them when closed. The same applies to the switches I2 and I3 in order to reduce the loop of the current flowing through them when closed.
Furthermore, the access connectors CN1 and CN2 are disposed, at the periphery of the board, next to one another on the same edge of the board, here on the left-hand edge of the board. Given that all the current loops pass through these two access connectors, this allows the size of these loops to be again reduced. In this preferred embodiment, the connector CN1 is located on the front face of the board and the connector CN2 is located, in the same position in the plane (x,y), on the back face. The track connecting the mid-point situated between the switches I2 and I3 to the connector CN2 is therefore made on the back face of the board together with the track connecting this mid-point to the energy recovery circuit. All the other circuit components and tracks are mounted on the front face of the board and a screw is, for example, provided for linking the track on the back face with the components on the front face.
Accordingly, as can be seen from
The size of the current loops in the z direction is greatly reduced and is essentially determined by the thickness of the board. In the plane (x,y), the size of the current loops is reduced if the switches I1 and I4, and also I2 and I3, are very close to one another and if they are disposed near to the access connectors CN1 and CN2. It should be noted that, in this figure, two power supply terminals T1 and T4 and two ground terminals T2 and T3 are shown in order to simplify the circuit diagram. It is clear that the provision of only one power supply terminal and one ground terminal is possible with additional tracks being used to link the elements connected to the missing terminals to these two terminals.
This solution is valid for an integrated circuit design or for one with discrete components. Near-field measurements demonstrated that the electromagnetic emissions were reduced relative to conventional circuits.
As a variant, the use of a single connector in place of the connectors CN1 and CN2 may be envisaged. In this case, some of the pins of this connector would be assigned to the electrodes Ys and the others to the electrodes Yas.
Number | Date | Country | Kind |
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03/09749 | Aug 2003 | FR | national |