Claims
- 1. A driver/receiver circuit comprising:
- a driver circuit having a power supply terminal, a ground terminal, an input terminal and first and second output nodes, the driver circuit for outputting, based on an input signal on said input terminal, on said first output node, a first output signal which changes between a power supply potential supplied to said power supply terminal and a first potential, and, on said second output node, a second output signal having the same phase as that of said first output signal and which changes between a second potential and a ground potential; and
- a receiver circuit including a first electric circuit having at least a P-channel MOSFET connected between said power supply terminal and an output terminal and having its gate electrically connected to said first output node, and a second electric circuit having at least an N-channel MOSFET connected between said ground terminal and said output terminal and having its gate electrically connected to said second output node, said second electric circuit having a configuration substantially similar to that of said first electric circuit,
- wherein said driver circuit includes:
- a P-channel MOSFET having its source connected to said power supply terminal, its gate connected to said input terminal, and its drain connected to said first output node,
- a first inverter circuit having its input connected to said first output node,
- a first voltage limiting MOSFET of a P-channel type having its source connected to said first output node and its gate connected to an output of said first inverter circuit,
- an N-channel MOSFET having its source connected to said ground terminal, its gate connected to said input terminal, and its drain connected to said second output node,
- a second inverter having its input connected to said second output node, and
- a second voltage limiting MOSFET of an N-channel type having its source connected to said second output node, its gate connected to an output of said inverter circuit, and its drain connected to a drain of said first voltage limiting MOSFET.
- 2. A driver/receiver circuit claimed in claim 1, wherein said driver circuit further includes:
- at least one additional input terminal;
- at least one additional P-channel MOSFET connected in parallel to said first P-channel MOSFET, between said power supply terminal and said first output node, and having its gate connected to said at least one additional input terminal; and
- at least one additional N-channel MOSFET connected in series to said first N-channel MOSFET, between said ground terminal and said second output node, and having its gate connected to said at least one additional input terminal.
- 3. A driver/receiver circuit claimed in claim 1, further including:
- a pull-up element comprising a P-channel MOSFET having its source connected to said power supply terminal, its gate connected to said ground terminal, and its drain connected to said first output node, and
- a pull-down element comprising an N-channel MOSFET having its source connected to said ground terminal, its gate connected to said power supply terminal and its drain connected to said second output node.
- 4. A driver/receiver circuit claimed in claim 1, wherein said receiver circuit includes:
- a P-channel MOSFET having its source connected to said power supply terminal, its gate connected to said first output node of said driver circuit, and its drain connected to said output terminal, and
- an N-channel MOSFET having its source connected to said ground terminal, its gate connected to said second output node of said driver circuit, and its drain connected to said output terminal.
- 5. A driver/receiver circuit claimed in claim 1, wherein said receiver circuit includes:
- a first electric circuit comprising a plurality of P-channel MOSFETs connected between said power supply terminal and said output terminal, and
- a second electric circuit comprising a plurality of N-channel MOSFETs connected between said ground terminal and said output terminal in a connection construction complementary to that of said first electric circuit,
- respective first output nodes of a plurality of driver circuits being connected to a gate of corresponding P-channel MOSFETs in said first electric circuit, and
- respective second output nodes of said plurality of driver circuits being connected to a gate of corresponding N-channel MOSFETs in said second electric circuit.
- 6. A driver/receiver circuit claimed in claim 1, wherein said receiver circuit includes:
- a first electric circuit comprising a plurality of P-channel MOSFETs connected between said power supply terminal and said output terminal, and
- a second electric circuit comprising a plurality of N-channel MOSFETs connected between said ground terminal and said output terminal in a connection construction complementary to that of said first electric circuit,
- a gate of at least one P-channel MOSFET of said P-channel MOSFETs included in said first electric circuit and a gate of an N-channel MOSFET which is included in said second electric circuit and which is complementary to said at least one P-channel MOSFET, being electrically connected to said first output node and said second output node of said driver circuit, and
- a gate of another P-channel MOSFET of said P-channel MOSFETs included in said first electric circuit being connected to a gate of an N-channel MOSFET which is included in said second electric circuit and which is complementary to said another P-channel MOSFET, and also being connected to an output of at least one CMOS circuit connected between said power supply terminal and said ground terminal.
- 7. A driver/receiver circuit claimed in claim 2, wherein said receiver circuit includes:
- a P-channel MOSFET having its source connected to said power supply terminal, its gate connected to said first output node of said driver circuit, and its drain connected to said output terminal, and
- an N-channel MOSFET having its source connected to said ground terminal, its gate connected to said second output node of said driver circuit, and its drain connected to said output terminal.
- 8. A driver/receiver circuit claimed in claim 2, wherein said receiver circuit includes:
- a first electric circuit comprising a plurality of P-channel MOSFETs connected between said power supply terminal and said output terminal, and
- a second electric circuit comprising a plurality of N-channel MOSFETs connected between said ground terminal and said output terminal in a connection construction complementary to that of said first electric circuit,
- respective first output nodes of a plurality of driver circuits being connected to a gate of corresponding P-channel MOSFETs in said first electric circuit, and
- respective second output nodes of said plurality of driver circuits being connected to a gate of corresponding N-channel MOSFETs in said second electric circuit.
- 9. A driver/receiver circuit claimed in claim 2, wherein said receiver circuit includes:
- a first electric circuit comprising a plurality of P-channel MOSFETs connected between said power supply terminal and said output terminal, and
- a second electric circuit comprising a plurality of N-channel MOSFETs connected between said ground terminal and said output terminal in a connection construction complementary to that of said first electric circuit,
- a gate of at least one P-channel MOSFET of said P-channel MOSFETs included in said first electric circuit and a gate of an N-channel MOSFET which is included in said second electric circuit and which is complementary to said at least one P-channel MOSFET, being electrically connected to said first output node and said second output node of said driver circuit, and
- a gate of another P-channel MOSFET of said P-channel MOSFETs included in said first electric circuit being connected to a gate of an N-channel MOSFET which is included in said second electric circuit and which is complementary to said another P-channel MOSFET, and also being connected to an output of at least one CMOS circuit connected between said power supply terminal and said ground terminal.
- 10. A driver/receiver circuit claimed in claim 5, wherein said plurality of P-channel MOSFETs in said first electric circuit have a parallel-connection with respect to one another and said plurality of N-channel MOSFETs in said second electric circuit have a series-connection with respect to one another.
- 11. A driver/receiver circuit claimed in claim 6, wherein said plurality of P-channel MOSFETs in said first electric circuit have a parallel-connection with respect to one another, and said plurality of N-channel MOSFETs in said second electric circuit have a series-connection with respect to one another.
- 12. A driver/receiver circuit claimed in claim 8, wherein said plurality of P-channel MOSFETs in said first electric circuit have a parallel-connection with respect to one another, and said plurality of N-channel MOSFETs in said second electric circuit have a series-connection with respect to one another.
- 13. A driver/receiver circuit claimed in claim 9, wherein said plurality of P-channel MOSFETs in said first electric circuit have a parallel-connection with respect to one another, and said plurality of N-channel MOSFETs in said second electric circuit have a series-connection with respect to one another.
Priority Claims (1)
Number |
Date |
Country |
Kind |
5-337164 |
Dec 1993 |
JPX |
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Parent Case Info
This is a Divisional Application of application Ser. No. 08/365,450 filed Dec. 28, 1994 now U.S. Pat. No. 5,543,744.
US Referenced Citations (9)
Divisions (1)
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Number |
Date |
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Parent |
365450 |
Dec 1994 |
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