Patent Application
20110148841
This application claims priority to Korean Patent Application No. 2009-128920, filed on Dec. 22, 2009, and all the benefits accruing therefrom under 35 U.S.C. §119, the content of which in its entirety is herein incorporated by reference.
1. Field of the Invention
The present invention relates to a driving circuit and a display apparatus having the same. More particularly, the present invention relates to a driving circuit capable of reducing the number of signal transmission lines thereof and a display apparatus having the driving circuit.
2. Description of the Related Art
In general, a liquid crystal display (“LCD”) includes an LCD panel to display an image and a driving circuit to drive the LCD panel.
The LCD panel typically includes a liquid crystal cell formed in each of a plurality of pixel regions and a thin film transistor connected to a gate line, a data line and the liquid crystal cell in each of the plurality of pixel regions.
The driving circuit typically includes a gate driver and a data driver. The gate driver applies signals to the gate line and the data driver applies signals to the data line. The gate driver typically sequentially provides a scan signal to the plurality of gate lines.
The data driver converts a digital data signal to an analog signal using a plurality of gamma voltages each having a different voltage level. In other words, the data driver selects a gamma voltage corresponding to a gray level of the digital data signal and provides the selected gamma voltage to a specific data line of the plurality of data lines in response to at least one control signal.
In the above configuration, the LCD requires a plurality of signal lines to provide the data driver with control signals and gamma voltages, so it is difficult to make the LCD smaller in size.
Exemplary embodiments of the present invention provide a driving circuit capable of reducing the number of signal transmission lines thereof.
Exemplary embodiments of the present invention also provide a display apparatus having the driving circuit.
According to one exemplary embodiment, the driving circuit includes; a timing controller which receives an external signal and outputs an image signal and a control signal for a single frame, a first gamma reference voltage generating circuit which outputs a first gamma reference voltage, a second gamma reference voltage, a third gamma reference voltage and a fourth gamma reference voltage, wherein the third gamma reference voltage and the fourth gamma reference voltage have a different polarity from the first gamma reference voltage and the second gamma reference voltage with respect to a predetermined reference voltage, and a data driver which receives the first to fourth gamma reference voltages, the image signal, and the control signal and outputs a data voltage, wherein the data driver includes; a second gamma reference voltage generating circuit which outputs at least one fifth gamma reference voltage and at least one sixth gamma reference voltage based on the control signal, wherein the fifth gamma reference voltage has a substantially similar voltage level as one of a voltage level of the first gamma reference voltage, a voltage level of the second gamma reference voltage, and a voltage level between the first gamma reference voltage and the second gamma reference voltage and wherein the sixth gamma reference voltage has a substantially similar voltage level as one of a voltage level of the third gamma reference voltage, a voltage level of the fourth gamma reference voltage, and a voltage level between the third gamma reference voltage and the fourth gamma reference voltage, a digital-to-analog (“D/A”) converter which converts the image signal to a first data voltage based on the first gamma reference voltage, second gamma reference voltage and fifth gamma reference voltage and converts the image signal to a second data voltage based on the third gamma reference voltage, fourth gamma reference voltage, and sixth gamma reference voltage, and a selector which receives the first data voltage and the second data voltage to output one of the first data voltage and the second data voltage as the data voltage.
In one exemplary embodiment, the driving circuit may further include a transmission line which connects the timing controller to the data driver to provide the data control signal and the gamma control signal to the data driver during a blank period of an image cycle and to provide the image signal to the data driver during a data transmission period of the image cycle.
According to another exemplary embodiment, the display apparatus includes; a timing controller which receives an external signal to provide an image signal and a control signal for a single frame, a display panel which displays an image in response to the image signal, a first gamma reference voltage generating circuit which outputs a first gamma reference voltage, a second gamma reference voltage, a third gamma reference voltage and a fourth gamma reference voltage, wherein the third gamma reference voltage and the fourth gamma reference voltage having a different polarity from the first gamma reference voltage and the second gamma reference voltage with respect to a predetermined reference voltage, and a data driver which receives the first to fourth gamma reference voltages, the image signal, and the control signal to generate a data voltage, wherein the data driver includes; a second gamma reference voltage generating circuit which outputs at least one fifth gamma reference voltage and at least one sixth gamma reference voltage based on the control signal, the fifth gamma reference voltage having a substantially same voltage level as a voltage level of the first gamma reference voltage, a voltage level of the second gamma reference voltage, or a voltage level between the first gamma reference voltage and second gamma reference voltage and the sixth gamma reference voltage having a substantially same voltage level as a voltage level of the third gamma reference voltage, a voltage level of the fourth gamma reference voltage, or a voltage level between the third gamma reference voltage and the fourth gamma reference voltage, a D/A converter which converts the image signal to a first data voltage based on the first gamma reference voltage, second gamma reference voltage, and fifth gamma reference voltage and converts the image signal to a second data voltage based on the third gamma reference voltage, fourth gamma reference voltage, and sixth gamma reference voltage, and a selector which receives the first data voltage and the second data voltage to output either the first data voltage or the second data voltage as the data voltage.
According to the above, the data control signal and the gamma control signal are transmitted during the blank period of the image signal cycle before the image signal is transmitted, thereby reducing the number of signal transmission lines through which the data control signal and the gamma control signal are transmitted. Moreover, since the gamma reference voltages are generated using the first gamma reference voltage generating circuit and the second gamma reference voltage generating circuit provided in the data driver, the number of signal transmission lines connected between the first gamma reference voltage generating circuit and the data driver can be reduced.
The above and other advantages of the present invention will become readily apparent by reference to the following detailed description when considered in conjunction with the accompanying drawings wherein:
The invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout.
It will be understood that when an element is referred to as being “on” another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” or “includes” and/or “including” when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.
Furthermore, relative terms, such as “lower” or “bottom” and “upper” or “top,” may be used herein to describe one element's relationship to another elements as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in one of the figures is turned over, elements described as being on the “lower” side of other elements would then be oriented on “upper” sides of the other elements. The exemplary term “lower”, can therefore, encompasses both an orientation of “lower” and “upper,” depending on the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as “below” or “beneath” other elements would then be oriented “above” the other elements. The exemplary terms “below” or “beneath” can, therefore, encompass both an orientation of above and below.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Exemplary embodiments of the present invention are described herein with reference to cross section illustrations that are schematic illustrations of idealized embodiments of the present invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as flat may, typically, have rough and/or nonlinear features. Moreover, sharp angles that are illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the present invention.
All methods described herein can be performed in a suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., “such as”), is intended merely to better illustrate the invention and does not pose a limitation on the scope of the invention unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the invention as used herein.
Hereinafter, the present invention will be explained in detail with reference to the accompanying drawings.
Referring to
The LCD panel 110 includes a plurality of gate lines GL1˜GLn, a plurality of data lines DL1˜DLm disposed substantially perpendicular to the gate lines GL1˜GLn, and a plurality of pixels. In the present exemplary embodiment, each of the plurality of pixels have substantially the same structure and function, thus one pixel is depicted as an example for the sake of convenience of explanation. In the present exemplary embodiment, each pixel includes a thin film transistor Tr, a liquid crystal capacitor CLC, and a storage capacitor CST. The thin film transistor Tr includes a gate electrode connected to a corresponding gate line of the plurality of gate lines GL1˜Gln, a source electrode connected to a corresponding data line of the plurality of data lines DL1˜DLm, and a drain electrode connected to the liquid crystal capacitor CLC and the storage capacitor CST. Alternative exemplary embodiments include configurations wherein the storage capacitor CST is omitted.
The timing controller 120 receives an external signal Ex_Sig from an external device (not shown). The timing controller 120 converts a data format of the external signal Ex_Sig into a data format appropriate to an interface between the timing controller 120 and the data driver 140 and outputs an image signal RGB and a control signal CS to the data driver 140. Furthermore, the timing controller 120 outputs a gate control signal GCS to a gate driver 130.
The gate driver 130 sequentially applies gate signals G1˜Gn to the gate lines GL1˜GLn of the LCD panel 110, respectively, in response to the gate control signal GCS provided from the timing controller 120 to sequentially scan the gate lines GL1˜GLn.
The first gamma reference voltage generating circuit 150 receives an analog driving voltage AVDD from an exterior (not shown) and outputs a plurality of gamma reference voltages VGR to the data driver 140.
The data driver 140 generates a plurality of gray scale voltages using the gamma reference voltages VGR provided from the first gamma reference voltage generating circuit 150. The data driver 140 selects data voltages corresponding to the image signal RGB from among the gray scale voltages in response to the image signal RGB from the timing controller 120 and applies the selected data voltages as data signals D1˜Dn to the data lines DL1˜DLm of the liquid crystal panel 110.
If a gate signal is applied to a selected gate line of the plurality of gate lines GL1˜GLn, a thin film transistor Tr connected to the selected gate line is turned on in response to the corresponding gate signal. Thus, the data signal applied to the data line connected to the turned-on thin film transistor Tr is charged in the liquid crystal capacitor CLC and the storage capacitor CST through the turned-on thin film transistor Tr.
The liquid crystal capacitor CLC controls light transmission of a liquid crystal layer including liquid crystal molecules (not shown) disposed in the liquid crystal panel 110 corresponding to the liquid crystal capacitor CLC according to the charged voltage of the liquid crystal capacitor CLC. In the exemplary embodiment where it is present, the storage capacitor CST is charged with the data signal provided through the corresponding data line when the thin film transistor Tr is turned on. Then, the storage capacitor CST applies the charged data signal to the liquid crystal capacitor CLC to maintain the charge of the liquid crystal capacitor CLC when the thin film transistor Tr is turned off. The LCD panel 110 can display a desired image through the above-described method.
Although not shown in
The data driver 140 includes a shift register 240, a latch circuit 245, a digital-to-analog converter (hereinafter, referred to as “D/A” converter) 250, a second gamma reference voltage generating circuit 210 and an output circuit 255. The shift register 240 receives a clock signal CKH and outputs a control signal LCS to the latch circuit 245. The latch circuit 245 stores data line by line in response to the control signal LCS from the shift register 240 and outputs the stored data DS a single line at a time.
The second gamma reference voltage generating circuit 210 receives four gamma reference voltages VGR1˜VGR4 from the first gamma reference voltage generating circuit 150 and a gamma control signal VCS from the timing controller 120 and outputs eight gamma reference voltages VGR1˜VGR8 to the D/A converter 250.
As another exemplary embodiment, the second gamma reference voltage generating circuit 210 may receive four gamma reference voltages VGR1˜VGR4 from the first gamma reference voltage generating circuit 150 and a gamma control signal VCS from the timing controller 120 to generate only four gamma reference voltages VGR5˜VGR8. In such an alternative exemplary embodiment, four gamma reference voltages VGR1˜VGR4 from the first gamma reference voltage generating circuit 150 may be input directly to the D/A converter 250. That is, in such an alternative exemplary embodiment the four gamma voltages VGR1˜VGR4 are input to both the second gamma reference voltage generating circuit 210 and to the D/A converter 250 while the D/A converter converts the four gamma voltages VGR1˜VGR4
The D/A converter 250 receives the eight gamma reference voltages VGR1˜VGR8 from the second gamma reference voltage generating circuit 210, or, in an alternative exemplary embodiment, from the first gamma reference voltage generating circuit 150 and the second gamma reference voltage generating circuit 210, and selects analog data voltages corresponding to the data DS provided from the latch circuit 245. The D/A converter 250 transmits the selected data voltages DV to the output circuit 255 and the output circuit 255 applies the data voltages DV to the data lines DL1˜DLm.
The first gamma reference voltage generating circuit 150 receives the analog driving voltage AVDD to output the first gamma reference voltage VGR1, the second gamma reference voltage VGR2, the third gamma reference voltage VGR3 and the fourth gamma reference voltage VGR4 to the data driver 140, as described above. The first gamma reference voltage VGR1 has a different polarity from that of the fourth gamma reference voltage VGR4 with respect to a predetermined reference voltage and the second gamma reference voltage VGR2 has a different polarity from that of the third gamma reference voltage VGR3 with respect to the predetermined reference voltage. That is, in one exemplary embodiment, the first gamma reference voltage VGR1 has a same polarity as that of the second gamma reference voltage VGR2 with respect to the predetermined reference voltage and the third gamma reference voltage VGR3 has a same polarity as that of the fourth gamma reference voltage VGR4 with respect to the predetermined reference voltage.
The second gamma reference voltage generating circuit 210 receives the first to fourth gamma reference voltages VGR1˜VGR4 from the first gamma reference voltage generating circuit 150. The second gamma reference voltage generating circuit 210 includes a first resistor string 221, a second resistor string 222 (outlined by dashed-line boxes), a first decoder 231, a second decoder 232, a third decoder 233 and a fourth decoder 234.
The first resistor string 221 includes a plurality of first resistors R11-R1k, where k is a natural number, and the first resistors R11-R1k are connected in series between the first and second gamma reference voltages VGR1 and VGR2. The second resistor string 222 includes a plurality of second resistors R21-R2l, where 1 is a natural number, and the second resistors R21-R2l are connected in series between the third and fourth gamma reference voltages VGR1 and VGR2.
In the present exemplary embodiment, the control signal CS output from the timing controller 120 includes a data control signal DCS and a gamma control signal VCS. The timing controller 120 applies the gamma control signal VCS to the first to fourth decoders 231, 232, 233 and 234.
The first and second decoders 231 and 232 respectively output voltages at two different nodes where the first resistors R11-R1k are connected as the fifth gamma reference voltage VGR5 and the sixth gamma reference voltage VGR6 in response to the gamma control signal VCS. The third and fourth decoders 233 and 234 respectively output voltages at two different nodes where the second resistors R21-R2l are connected as the seventh gamma reference voltage VGR7 and the eighth gamma reference voltage VGR8 in response to the gamma control signal VCS. Specifically, the first decoder 231 is connected to all of the nodes between consecutive first resistors R11-R1k corresponding thereto and the second decoder 232 is connected to all of the nodes between consecutive first resistors R11-R1k corresponding thereto, e.g., all remaining first resistor nodes.
The present exemplary embodiment of a D/A converter 250 includes a third resistor string 261, a fourth resistor string 262, a first switch circuit 271 and a second switch circuit 272.
The third resistor string 261 includes a plurality of third resistors R31-R3m, where m is a natural number, and the third resistors R31-R3m are connected in series between the first and second gamma reference voltages VGR1 and VGR2. The first and second decoders 231 and 232 are respectively connected to two different nodes where the third resistors R31-R3m are connected to respectively output the fifth and sixth gamma reference voltages VGR5 and VGR6. The third resistor string 261 receives the first, second, fifth, and sixth gamma reference voltages VGR1, VGR2, VGR5 and VGR6 and the nodes at which the third resistors R31-R3m are connected output a plurality of first gray scale voltages, specifically, the voltage potential at each of the nodes of the third resistor string correspond to the plurality of first gray scale voltages, respectively.
The fourth resistor string 262 includes a plurality of fourth resistors R41-R4n, where n is a natural number, and the fourth resistors R41-R4n are connected in series between the third and fourth gamma reference voltages VGR3 and VGR4. The third and fourth decoders 233 and 234 are respectively connected to two different nodes where the fourth resistors R41-R4n are connected and respectively output the seventh and eighth gamma reference voltages VGR 7 and VGR 8. The fourth resistor string 262 receives the third, fourth, seventh, and eighth gamma reference voltages VGR3, VGR4, VGR7 and VGR8 and the nodes at which the fourth resistors R41-R4n are connected output a plurality of second gray scale voltages, specifically, the voltage potential at each of the nodes of the fourth resistor string correspond to the plurality of second gray scale voltages, respectively.
The first switch circuit 271 includes a plurality of switches and is connected to the nodes where the third resistors R31-R3m are connected to receive the first gray scale voltages. The second switch circuit 272 includes a plurality of switches and is connected to the nodes where the fourth resistors R41-R4n are connected to receive the second gray scale voltages. The first switch circuit 271 receives the data DS from the latch circuit 245 to output one of the first gray scale voltages as a first data voltage DV1 and the second switch circuit 272 receives the data DS from the latch circuit 245 to output one of the second gray scale voltages as a second data voltage DV2.
In one exemplary embodiment, the data driver 140 may further include a selector 290. In such an exemplary embodiment, the control signal CS output from the timing controller 120 may further include a polarity control signal Pol. The selector 290 receives the first data voltage DV1 and the second data voltage DV2 and outputs either the first data voltage DV1 or the second data voltage DV2 as a data voltage DV according to the polarity control signal Pol. The selector 290 may be, but is not limited to, a multiplexer that selects and outputs either the first data voltage DV1 or the second data voltage DV2 in response to the polarity control signal Pol.
In the present exemplary embodiment, although not shown in the figures, a first gamma reference voltage generating circuit 150 receives an analog driving voltage AVDD from an exterior source and outputs a first gamma reference voltage VGR1 and a second gamma reference voltage VGR2 to the data driver 140. The second gamma reference voltage generating circuit 310 includes a first resistor string 320, a first decoder 331 and a second decoder 332 and receives the first and second gamma reference voltages VGR1 and VGR2 from the first gamma reference voltage generating circuit 150.
The first resistor string 320 includes a plurality of first resistors R11-R1i where i is a natural number, and the first resistors R11-R1i are connected in series between the first and second gamma reference voltages VGR1 and VGR2.
The control signal CS output from the timing controller 120 includes a data control signal DCS and a gamma control signal VCS. The timing controller 120 applies the gamma control signal VCS to the first and second decoders 331 and 332 and applies the image signal RGB to the D/A converter 350.
Responsive to the gamma control signal VCS, the first and second decoders 331 and 332 respectively output voltages at two different nodes where the first resistors R11-R1i are connected as a third gamma reference voltage VGR3 and a fourth gamma reference voltage VGR4.
In the present exemplary embodiment, the D/A converter 350 includes a single second resistor string 361 and a single switch circuit 371.
The second resistor string 361 includes a plurality of second resistors R21-R2j, where j is a natural number, and the second resistors R21-R2j are connected in series between the first and second gamma reference voltages VGR1 and VGR2. The first and second decoders 331 and 332 output the third and fourth gamma reference voltages VGR3 and VGR4 from two different nodes where the second resistors R21-R2j are connected, respectively. The second resistor string 361 receives the first to fourth gamma reference voltages VGR1, VGR2, VGR3 and VGR4 and the nodes at which the second resistors R21-R2j are connected output a plurality of gray scale voltages; that is, the voltage potential at each of the nodes of the second resistor string correspond to the plurality of gray scale voltages, respectively.
The switch circuit 371 includes a plurality of switches and is connected to the nodes at which the second resistors R21-R2j are connected to receive the gray scale voltages. The switch circuit 371 receives the data DS from the latch circuit 245 and outputs one of the gray scale voltages as a data voltage DV.
In
The timing controller 120 repeatedly transmits the image signal RGB to the data driver 140 for each frame and a blank period BLK exists between two subsequent frames in the data transmission lines LV0, LV1 and LV2. If a predetermined time period, for example a time period corresponding to one clock period of the first clock signal CLK1, passes after the second clock signal CLK2 becomes high in the blank period BLK, a reset signal RST is applied to the first data transmission line LV0. The reset signal RST becomes low after the reset signal RST is maintained at high state for a time period corresponding to three clock periods of the first clock signal CLK1. Then, if a time period corresponding to 7.5 clock periods of the first clock signal CLK1 passes after the reset signal RST switches to a low state, the image signal RGB begins transmission through the first to third data transmission lines LV0, LV1 and LV2. Hereinafter, a time period for which the image signal RGB is transmitted is referred to as a data transmission period DTP and a time period for which the control signal CS is transmitted from a time at which the reset signal RST becomes low to a time at which the data transmission period DTP starts is referred to as a control signal transmission period CST.
As shown in
For example, the timing controller 120 transmits the data control signal DCS during a time period corresponding to two clock periods of the first clock signal CLK1 at a time point at which 1.5 clock periods of the first clock signal CLK1 passes after the reset signal RST switches to a low state. Then, the timing controller 120 transmits the gamma control signal VCS during a time period corresponding to three clock periods of the first clock signal CLK1. The timing controller 120 may transmit the image signal RGB and the control signal CS at the rising and falling times of the first clock signal CLK1.
In one exemplary embodiment, the control signal CS may further include an error detection signal EDS to detect whether the data control signal DCS and the gamma control signal VCS are transmitted successfully. Exemplary embodiments of the error detection signal EDS may be a checksum value or a parity bit value of the transmitted signals. Moreover, the data driver 140 detects existence of error in the signal transmission by comparing a predetermined value of the transmitted control signal with the error detection signal EDS. If transmission errors of the data control signal DCS and the gamma control signal VCS are detected, the data driver 140 may repeat the output of a data voltage of a previous frame.
In the exemplary embodiment where it is present, the timing controller 120 transmits the error detection signal EDS for a time period corresponding to one clock period after the gamma control signal VCS is transmitted. The number of clock periods required to transmit the data control signal DCS, the gamma control signal VCS, and the error detection signal EDS may be changed and also their transmission order may be changed. Exemplary embodiments include configurations wherein the error detection signal EDS may be transmitted after the data control signal DCS and the gamma control signal VCS are transmitted in order to ensure accurate transmission of the data control signal DCS and the gamma control signal VCS. In the present exemplary embodiment, the first to third data transmission lines LV0, LV1 and LV2 transmit the image signal RGB after the error detection signal EDS is transmitted.
In one exemplary embodiment, the control signals related to the image signal RGB and the data voltage and the polarity control signal Pol may be transmitted during the blank period BLK prior to the data transmission period DTP. Furthermore, in another exemplary embodiment the number of control signals that can be transmitted during the blank period BLK may be changed depending on a time length of the blank period BLK.
The timing controller 120 may further include an encoder (not shown) to encode at least one portion of the image signal RGB or the control signal CS transmitted during the blank period BLK. In addition, the data driver 140 may further include a decoder (not shown) to decode the encoded image signal or the encoded control signal.
According to the above, the number of signal transmission lines in the driving circuit may be reduced, thereby reducing the size of the printed circuit board connecting the timing controller to the data driver. In addition, as the number of the signal transmission lines is reduced, the intervals between the signal transmission lines connected to one driver IC can be wider, to thereby prevent alignment errors occurring when connecting pins of the driver IC to the signal lines.
Although the exemplary embodiments of the present invention have been described, it is understood that the present invention should not be limited to these exemplary embodiments but various changes and modifications can be made by one ordinary skilled in the art within the spirit and scope of the present invention as hereinafter claimed.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2009-0128920 | Dec 2009 | KR | national |
