Driving circuit and method for increasing effective bits of source drivers

Abstract

An LCD driving circuit and method for increasing effective bit(s) of the source driver is disclosed. A reference voltage generator generates a group of compensated reference voltage levels that are interlaced with original reference voltage level of original reference voltage generator. One of the multiple groups of reference voltage levels is selected by one or more least significant bits (LSBs), and is then inputted to digital-to-Analog converter of the source driver under control of the one or more least significant bits (LSBs), thereby effectively and economically enhancing the gray levels of the display on the LCD panel.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

FIG. 1A illustrates an LCD panel driving circuit for increasing effective bits of the source drivers;

FIG. 1B illustrates another LCD panel driving circuit for increasing effective bits of the source drivers;

FIG. 1C shows a block diagram of the source driver of FIG. 1A;

FIG. 2A to FIG. 2C show a simplified example illustrating how an original 2-bit DAC effectively provides 3-bit and 4-bit function;

FIG. 3A illustrates the other LCD panel driving circuit for increasing effective bits of the source drivers;

FIG. 3B shows a block diagram of the source driver of FIG. 3A according to one embodiment of the present invention; and

FIG. 4 shows a simulation of increasing one effective bit from a 6-bit DAC according to the present invention.

Claims

1. A reference voltage controlling method for increasing effective bit of an n-bit digital-to-analog converter (DAC) of a source driver, comprising: generating original multiple reference voltage levels and compensated multiple reference voltage levels;providing one or more least significant bit(s) (LSB) for selecting one of the original multiple reference voltage levels and compensated multiple reference voltage levels in sequence;inputting the selected one of multiple reference voltage levels at a time into the DAC of the source driver; andwherein the original multiple reference voltage levels are not overlapping compensated multiple reference voltage levels.

2. The reference voltage controlling method according to claim 1, wherein the one or more least significant bit(s) (LSB) are belong to one or more control signals from a timing controller.

3. The reference voltage controlling method according to claim 1, wherein the digital-to-analog converter (DAC) includes serially connected resistors therein.

4. The reference voltage controlling method according to claim 3, further comprising a step selectively applying the selected group of voltage levels to some nodes among the serially connected resistors.

5. The reference voltage controlling method according to claim 1, further comprising a step generating a first 2n output voltages from the n-bit DAC as the original voltage levels are selected and inputted into the n-bit DAC.

6. The reference voltage controlling method according to claim 5, further comprising a step generating a second 2n output voltages from the n-bit DAC as the compensated voltage levels are selected and inputted into the n-bit DAC.

7. The reference voltage controlling method according to claim 6, wherein the first 2n output voltages is interlaced with second 2n output voltages.

8. The reference voltage controlling method according to claim 6, wherein the sum of output voltages from DAC of the source driver is no less than 2n+1.

9. A display driving circuit according the driving method of claim 6, said driving circuit comprising: a first reference voltage generator for generating original multiple reference voltage levels;at least one second reference voltage generator for generating compensated multiple reference voltage levels;a selector for selecting one of the multiple voltage levels by the one or more least significant bit(s) (LSB); andthe source driver receiving the selected multiple voltage levels at a time.

10. The display driving circuit according to claim 9, wherein the number of the second reference voltage generators is 2m-1 and m is a positive integer.

11. The display driving circuit according to claim 10, wherein the sum of output voltages from DAC of the source driver is about 2n+m.

12. The display driving circuit according to claim 9, wherein the selector is one of a timing controller, a switch and combined.

13. The display driving circuit according to claim 9, further comprising a timing controller inputting one or more control signals to the first and second reference voltage generators.

14. The display driving circuit according to claim 13, wherein the second reference voltage generator receives the one or more least significant bit or bits belonging to the one or more control signals.

15. The display driving circuit according to claim 9, wherein the digital-to-analog converter (DAC) includes serially connected resistors therein and selectively applies the selected group of voltage levels at some nodes among the serially connected resistors.

16. The display driving circuit according to claim 9, wherein the first reference voltage generator and the second reference voltage generator are embedded together.

17. The display driving circuit according to claim 9, wherein the second reference voltage generator is embedded in the source driver.

18. An LCD source driver, comprising: a data register sequentially sampling input digital video signals;a latch for latching the sampled digital video signals;a digital-to-analog converter for converting the digital video signals to analog video signals, the analog video signals then being outputted to an LCD panel; anda selector which selects one of multiple groups of reference voltages, and sequentially and alternatively provides the selected group of reference voltages to the digital-to-analog converter.

19. The LCD source driver according to claim 18, further comprising a level shifter for shifting voltage level of the latch digital video signals.

20. The LCD source driver according to claim 18, further comprising an output buffer for amplifying the analog video signal from the digital-to-analog converter.

21. The LCD source driver according to claim 19, wherein the selection in the selector is controlled by one or more least significant bit(s) (LSB) supplied from the level shifter.

22. The LCD source driver according to claim 18, further comprising at least one multi-reference voltage generator to generate the multiple groups of reference voltages.