The present application claims the priority to Chinese Patent Application No. 201410836186.4, entitled “DRIVING CIRCUIT, ARRAY SUBSTRATE AND DISPLAY APPARATUS”, filed on Dec. 30, 2014 with the State Intellectual Property Office of People's Republic of China, which is incorporated herein by reference in its entirety.
The disclosure relates to the field of display, and in particular, to a driving circuit, an array substrate and a display apparatus.
In recent years, display apparatuses are popular and widely applied in, for example, mobile phones, tablet PCs, displays and televisions. A conventional display apparatus includes an array substrate, and the array substrate includes data lines, gate lines, pixel electrodes, and a driving circuit and switching elements which are for coupling the pixel electrodes to the data lines and the gate lines. The driving circuit controls the gate lines to turn on the switching elements, and accordingly, data signals from the data lines are input to the pixel electrodes.
Conventionally, the driving circuit generally drives the gate lines row by row, the switching elements controlled by the gate lines can not be turned on simultaneously, and consequently, the pixel electrodes can not discharge simultaneously, thereby resulting in ghosting and image flutter which may negatively affect display quality and user experience.
A problem to be solved by the disclosure is that, the conventional driving circuit can not drive all the gate lines simultaneously to discharge electric charges, thereby resulting in ghosting and image flutter and influencing display quality and user experience.
A driving circuit is provided according to an embodiment of the disclosure, which includes multiple shift register units, at least one scan control unit and at least one all-gate-on unit. An operation of the driving circuit includes a driving phase and a discharging phase; during the driving phase, the at least one scan control unit controls the shift register units to output multiple driving signals successively in a first direction or in a second direction, the first direction being opposite to the second direction; and during the discharging phase, the at least one all-gate-on unit controls the shift register units to output multiple driving signals simultaneously.
The driving circuit according to the embodiment of the disclosure includes the all-gate-on unit and may enable, based on variations of signals input to clock control terminals, all the driving units to output driving signals, thereby solving the problem in the conventional technology that the driving circuit can not control all the gate lines to turn on switching elements simultaneously to discharge electric charges, avoiding ghosting and image flutter, and improving the display quality.
An array substrate is further provided according to an embodiment of the disclosure, which includes gate lines, data lines and pixel regions arranged in an array and located at intersections of the gate lines and the data lines. The array substrate is provided with at least one driving circuit according to the embodiments of the disclosure.
An array substrate is further provided according to an embodiment of the disclosure, which includes a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line, gate lines, data lines and pixel regions arranged in an array and located at intersections of the gate lines and the data lines. The array substrate is provided with two driving circuits according to the embodiments of the disclosure, which are a first driving circuit and a second driving circuit electrical connections among elements of the array substrate according to the embodiment of the disclosure are detailed as follows:
the first clock signal line is electrically connected to the first clock control terminal of each of odd-numbered stages of driving units of the first driving circuit, the third clock control terminal of each of even-numbered stages of driving units of the first driving circuit, the fourth clock control terminal of each of odd-numbered stages of driving units of the second driving circuit and the second clock control terminal of each of even-numbered stages of driving units of the second driving circuit;
the second clock signal line is electrically connected to the second clock control terminal of each of the odd-numbered stages of driving units of the first driving circuit, the fourth clock control terminal of each of the even-numbered stages of driving units of the first driving circuit, the first clock control terminal of each of the odd-numbered stages of driving units of the second driving circuit and the third clock control terminal of each of the even-numbered stages of driving units of the second driving circuit;
the third clock signal line is electrically connected to the third clock control terminal of each of the odd-numbered stages of driving units of the first driving circuit, the first clock control terminal of each of the even-numbered stages of driving units of the first driving circuit, the second clock control terminal of each of the odd-numbered stages of driving units of the second driving circuit and the fourth clock control terminal of each of the even-numbered stages of driving units of the second driving circuit; and
the fourth clock signal line is electrically connected to the fourth clock control terminal of each of the odd-numbered stages of driving units of the first driving circuit, the second clock control terminal of each of the even-numbered stages of driving units of the first driving circuit, the third clock control terminal of each of the odd-numbered stages of driving units of the second driving circuit and the first clock control terminal of each of the even-numbered stages of driving units of the second driving circuit.
A display apparatus is further provided according to an embodiment of the disclosure, which includes the array substrate according to the embodiments of the disclosure and an opposed substrate provided opposite to the array substrate.
The array substrate and the display apparatus according to the embodiments of the disclosure can provide driving signals to all the gate lines simultaneously based on signals input to the clock control terminals, to enable all the pixel electrodes to discharge electric charges, thereby avoiding ghosting and image flutter and improving the display quality.
Embodiments of the disclosure are illustrated in detail hereinafter in conjunction with drawings, to further clarify the aforementioned objects, features and advantages of the disclosure.
In order to fully understand the disclosure, many specific details are given in the following description; while the disclosure may be also implemented in other ways different from ways described in the specification, and the disclosure is not limited to the embodiments disclosed hereinafter.
A driving circuit is provided according to an embodiment of the disclosure. As shown in
During the driving phase S1, the scan control unit 30 controls shift register units Y1, Y2, Y3 and Y4 to output multiple driving signals successively in a first direction or a second direction, where the first direction is opposite to the second direction.
During the discharging phase S2, the all-gate-on unit 40 controls the shift register units 20 to output multiple driving signals simultaneously.
The driving signal is a signal of switching elements, which may initiate a driving to maintain the conduction of electricity to perform discharging. The driving signal may be a high level or a low level. Here it is illustrated by taking a low level driving signal as an example in conjunction with
It should be noted that, the driving circuit in the embodiment of the disclosure includes multiple transistors, and the driving circuit is formed on a glass substrate, a plastics substrate or an electronic paper substrate rather than located in an integrated circuit or a chip. The driving circuit in the embodiment of the disclosure may perform a normal and ordered driving during the driving phase and may perform a simultaneous driving during the discharging phase, to maintain the conduction of electricity to discharge electric charges, thereby avoiding the ghosting and image flutter.
In the disclosure, the number of the shift register units, the number of the at least one scan control unit and the number of the at least one all-gate-on unit may be different or the same. As shown in
The scan control unit 30 includes a first signal output terminal L1 and a second signal output terminal L2. The scan control unit 30 controls the first signal output terminal L1 to output a signal input to the first signal input terminal IN1 or a signal input to the second signal input terminal IN2, and controls the second signal output terminal L2 to output a signal input to the second clock control terminal CK2 or a signal input to the fourth clock control terminal CK4.
The shift register unit 20 includes a trigger signal terminal IN and a reset signal terminal Reset. The trigger signal terminal IN is electrically connected to the first signal output terminal L1 of the scan control unit, and the reset signal terminal Reset is electrically connected to the second signal output terminal L2 of the scan control unit.
The all-gate-on unit 40 is configured to control the shift register unit 20 to continuously output a driving signal. The all-gate-on unit 40 includes a first discharging control terminal E1 and a second discharging control terminal E2. The first discharging control terminal E1 is electrically connected to the first clock control terminal CK1, and the second discharging control terminal E2 is electrically connected to the third clock control terminal CK3.
The all-gate-on unit 40 may be electrically connected to the shift register unit 20 in many ways.
It should be noted that, the all-gate-on unit 40 may be further electrically connected to the reset signal terminal Reset of the shift register unit 20. In this way, the all-gate-on unit 40 may reset the circuit regardless of an operation phase of the shift register unit 20. As shown in
The shift register unit 20 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a first capacitor C1, a second capacitor C2, a first voltage supply V1 and a second voltage supply V2.
A gate of the first transistor T1 is electrically connected to a third clock control terminal CK3, a first electrode of the first transistor T1 is electrically connected to a first signal output terminal L1 of the scan control unit, and a second electrode of the first transistor T1 is electrically connected to a second electrode of the second transistor T2 at a point P. A gate of the second transistor T2 is electrically connected to a second electrode of the third transistor T3 at a point Q, a first electrode of the second transistor T2 is electrically connected to a first electrode of the third transistor T3. A gate of the third transistor T3 is electrically connected to the second electrode of the first transistor T1 at the point P.
A gate of the fourth transistor T4 is electrically connected to a second signal output terminal L2 of the scan control unit, a first electrode of the fourth transistor T4 is electrically connected to the first voltage supply V1, and a second electrode of the fourth transistor T4 is electrically connected to the second electrode of the third transistor T3 at the point Q. A gate of the fifth transistor T5 is electrically connected to the first voltage supply V1, a first electrode of the fifth transistor T5 is electrically connected to the second electrode of the first transistor T1 at the point P, and a second electrode of the fifth transistor T5 is electrically connected to a gate of the sixth transistor T6. A first electrode of the sixth transistor T6 is electrically connected to a first clock control terminal CK1, and a second electrode of the sixth transistor T6 is electrically connected to an output terminal OUT of the shift register unit 20.
A gate of the seventh transistor T7 is electrically connected to the second electrode of the third transistor at the point Q. A first electrode of the seventh transistor T7 is electrically connected to the second voltage supply V2, and a second electrode of the seventh transistor T7 is electrically connected to the output terminal OUT of the shift register unit 20. A first plate of the first capacitor C1 is electrically connected to the second voltage supply V2, and a second plate of the first capacitor C1 is electrically connected to the second electrode of the third transistor at the point Q. A first plate of the second capacitor C2 is electrically connected to the second electrode of the fifth transistor T5, and a second plate of the second capacitor C2 is electrically connected to the output terminal OUT of the shift register unit 20.
As shown in
A gate of the eighth transistor T8 is electrically connected to the second selection control terminal D2U, a first electrode of the eighth transistor T8 is electrically connected to a second signal input terminal IN2, and a second electrode of the eighth transistor T8 is electrically connected to the first signal output terminal L1 of the scan control unit 30.
A gate of the ninth transistor T9 is electrically connected to the first selection control terminal U2D, a first electrode of the ninth transistor T9 is electrically connected to a first signal input terminal IN1, and a second electrode of the ninth transistor T9 is electrically connected to the first signal output terminal L1 of the scan control unit 30.
A gate of the tenth transistor T10 is electrically connected to the second selection control terminal D2U, a first electrode of the tenth transistor T10 is electrically connected to a fourth clock control terminal CK4, and a second electrode of the tenth transistor T10 is electrically connected to a second signal output terminal L2 of the scan control unit 30.
A gate of the eleventh transistor T11 is electrically connected to the first selection control terminal U2D, a first electrode of the eleventh transistor T11 is electrically connected to a second clock control terminal CK2, and a second electrode of the eleventh transistor T11 is electrically connected to the second signal output terminal L2 of the scan control unit 30.
As shown in
A gate of the twelfth transistor T12 is electrically connected to a third clock control terminal CK3, a first electrode of the twelfth transistor T12 is electrically connected to a second electrode of the thirteenth transistor T13, and a second electrode of the twelfth transistor T12 is electrically connected to a trigger signal terminal IN of the shift register unit 20.
A gate of the thirteenth transistor T13 is electrically connected to the first clock control terminal CK1, and a first electrode of the thirteenth transistor T13 is electrically connected to the first voltage supply V1.
A gate of the fourteenth transistor T14 is electrically connected to the first clock control terminal CK1, a first electrode of the fourteenth transistor T14 is electrically connected to the second voltage supply V2, and a second electrode of the fourteenth transistor T14 is electrically connected to the second signal output terminal L2 of the scan control unit 30.
The output terminal of the all-gate-on unit 40 may be connected in many ways. As shown in
As shown in
During the driving phase S1, a first clock signal, a second clock signal, a third clock signal and a fourth clock signal are respectively input to the first clock control terminal CK1, the second clock control terminal CK2, the third clock control terminal CK3 and the fourth clock control terminal CK4. As shown in
During the driving phase S1, explanation is made based on a case that a low level signal is input to the first selection control terminal U2D and a high level signal is input to the second selection control terminal D2U, i.e., a signal input to the first signal input terminal IN1 is input to the trigger signal terminal IN of the shift register unit 20. In other embodiments of the disclosure, a high level signal may be input to the first selection control terminal U2D and a low level signal may be input to the second selection control terminal D2U, i.e., a signal input to the second signal input terminal IN2 is input to the trigger signal terminal IN of the shift register unit 20.
Reference is further made to
During a second duration of T, the third clock signal is at a low level, and each of the first clock signal, the second clock signal and the fourth clock signal is at a high level. In the case that a low level is input to the trigger signal terminal IN, the first transistor T1 and the twelfth transistor T12 are turned on, and a low level input to the trigger signal terminal IN is input to the point P via the first transistor T1. Since the first clock signal is at the high level, the thirteenth transistor T3 is turned off, and the all-gate-on unit 40 does not influence an input to the trigger signal terminal IN of the shift trigger unit 20. The fifth transistor T5 maintains turned on and the low level signal from the point P is transmitted to the gate of the sixth transistor T6 to turn on the sixth transistor T6, the high level of the first clock signal is output from the output terminal of the shift register unit 20, and the second capacitor C2 is charged.
During a third duration of T, the fourth clock signal is at a low level, and each of the first clock signal, the second clock signal and the third clock signal is at a high level. A high level is input to the trigger signal terminal IN, the first transistor T1 is turned off, and a potential of the point P is maintained at a low level. The fifth transistor T5 maintains turned on and transmits the low level signal from the point P to the gate of the sixth transistor T6 to turn on the sixth transistor T6, and the high level of the first clock signal is output from the output terminal of the shift register unit 20.
During a fourth duration of T, the first clock signal is at a low level, and each of the second clock signal, the third clock signal and the fourth clock signal is at a high level. In the case that a high level is input to the trigger signal terminal IN, the first transistor T1 and the fourth transistor T4 are both turned off, the second capacitor C2 discharges to turn on the sixth transistor T6. The point P is maintained at a low level, the seventh transistor T7 is turned off, and the low level of the first clock signal is output from the output terminal OUT, i.e., the low level signal input to the trigger signal terminal is shifted by a time delay of 2T and output by the shift register unit 20.
Still as shown in
Clock control terminals of the respective stages of driving units are connected in the following way. In the first direction, the first clock control terminal of one stage of driving unit is electrically connected to the third clock control terminal of a next stage of driving unit, i.e., the first clock control terminal CK1 of the first stage of driving unit P1 is electrically connected to the third clock control terminal CK3 of the second stage of driving unit P2, and the first clock control terminal CK1 of the second stage of driving unit P2 is electrically connected to the third clock control terminal CK3 of the third stage of driving unit P3. In the first direction, the second clock control terminal of one stage of driving unit is electrically connected to the fourth clock control terminal of a next stage of driving unit, i.e., the second clock control terminal CK2 of the first stage of driving unit P1 is electrically connected to the fourth clock control terminal CK4 of the second stage of driving unit P2, and the second clock control terminal CK2 of the second stage of driving unit P2 is electrically connected to the fourth clock control terminal CK4 of the third stage of driving unit P3. In the first direction, the third clock control terminal of one stage of driving unit is electrically connected to the first clock control terminal of a next stage of driving unit, i.e., the third clock control terminal CK3 of the first stage of driving unit P1 is electrically connected to the first clock control terminal CK1 of the second stage of driving unit P2, and the third clock control terminal CK3 of the second stage of driving unit P2 is electrically connected to the first clock control terminal CK1 of the third stage of driving unit P3. In the first direction, the fourth clock control terminal of one stage of driving unit is electrically connected to the second clock control terminal of a next stage of driving unit, i.e., the fourth clock control terminal CK4 of the first stage of driving unit P1 is electrically connected to the second clock control terminal CK2 of the second stage of driving unit P2, and the fourth clock control terminal CK4 of the second stage of driving unit P2 is electrically connected to the second clock control terminal CK2 of the third stage of driving unit P3. That is to say, the first clock control terminal CK1 of one driving unit is electrically connected to the third clock control terminal CK3 of an adjacent driving unit, and the second clock control terminal CK2 of one driving unit is electrically connected to the fourth clock control terminal CK4 of an adjacent driving unit.
Reference is made to
In the case that a driving operation is performed in the first direction, a signal input to the first signal input terminal IN1 is output from the first signal output terminal L1 of the scan control unit 30. An initial signal is input to the first signal input terminal of a scan control unit 30 which firstly occurs in the first direction, i.e., an initial signal STV1 is input to the first signal input terminal P1-IN1 of the first stage of driving unit P1. A signal input to the second clock control terminal CK2 is output from the second signal output terminal L2 of the scan control unit 30.
In the case that a driving operation is performed in the second direction, a signal input to the second signal input terminal IN2 is output from the first signal output terminal L1 of the scan control unit 30. An initial signal is input to the second signal input terminal of a scan control unit 30 which firstly occurs in the second direction, i.e., an initial signal STV2 is input to the second signal input terminal P3-IN2 of the third stage of driving unit P3. A signal input to the fourth clock control terminal CK4 is output from the second signal output terminal L2 of the scan control unit 30.
During the driving phase S1, a first clock signal, a second clock signal, a third clock signal and a fourth clock signal may be respectively provided to the first clock control terminal, the second clock control terminal, the third clock control terminal and the fourth clock control terminal of the driving unit which firstly occurs in the first direction or in the second direction. During the discharging phase, low level signals are input to the first clock control terminal and the third clock control terminal, and high level signals are input to the first selection control terminal and the second selection control terminal.
During the driving phase S1, a low level signal is input to the first selection control terminal U2D, and a high level signal is input to the second selection control terminal D2U. The signal STV1 input to the first signal input terminal P1-IN1 is shifted by a time delay of 2T and output by the first stage of driving unit P1, the signal output from the first stage of driving unit P1 is shifted by the time delay of 2T and output by the second stage of driving unit P2, and the signal output from the second stage of driving unit P2 is shifted by the time delay of 2T and output by the third stage of driving unit P3. That is to say, in the first direction, the signal input to the first signal input terminal IN1 of one stage of driving unit is shifted by the time delay of 2T and output by the stage of driving unit.
In other embodiments of the disclosure, a high level signal may be input to the first selection control terminal U2D and a low level signal may be input to the second selection control terminal D2U, i.e., a signal input to the second signal input terminal IN2 is input to the trigger signal terminal IN of the shift register unit 20. The signal STV2 input to the second signal input terminal P3-IN2 is shifted by a time delay of 2T and output by the third stage of driving unit P3, the signal output from the third stage of driving unit P3 is shifted by the time delay of 2T and output by the second stage of driving unit P2, and the signal output from the second stage of driving unit P2 is shifted by the time delay of 2T and output by the first stage of driving unit P1. That is to say, in the second direction, the signal provided to the first signal input terminal IN2 of one stage of driving unit is shifted by the time delay of 2T and output by the stage of driving unit, thereby performing the driving operation in the second direction.
During the discharging phase S2, similar to the foregoing timing sequence of the driving circuit, low level signals are input to the first clock control terminal to the fourth clock control terminal, and high level signals are input to the first selection control terminal U2D and the second selection control terminal D2U. In this case, none of signals input to the first signal input terminal IN1, the second signal input terminal IN2, the second clock control terminal CK2 and the fourth clock control terminal CK4 of the scan control unit 30 is input to the shift register unit 20, the twelfth transistor T12 and the thirteenth transistor T13 are turned on by low levels input to the first clock control terminal and the third clock control terminal, and the low level of the first voltage supply V1 is input to the shift register unit 20 to turn on the sixth transistor T6. The fourteenth transistor T14 is turned on, and the high level of the second voltage supply V2 is input to the gate of the fourth transistor T4 to turn off the fourth transistor. In this case, the low level signal input to the first clock control terminal is continuously output from the output terminal OUT of the shift register unit.
An array substrate 100 is further provided according to an embodiment of the disclosure. As shown in
Referring to
Furthermore, the first gate lines 110a are odd-numbered rows of gate lines arranged parallel in a first direction, and the second gate lines 110b are even-numbered rows of gate lines arranged parallel in the first direction.
An array substrate is further provided according to an embodiment of the disclosure. As shown in
The first clock signal line CL1 is electrically connected to a first clock control terminal CK1 of each of odd-numbered stages of driving units of the first driving circuit 140a, a third clock control terminal CK3 of each of even-numbered stages of driving units of the first driving circuit 140a, a fourth clock control terminal CK4 of each of odd-numbered stages of driving units of the second driving circuit 140b and a second clock control terminal CK2 of each of even-numbered stages of driving units of the second driving circuit 140b. That is, the first clock signal line CL1 is electrically connected to the first clock control terminals CK1 of the driving unit L1 and the driving unit L3, the third clock control terminal CK3 of the driving unit L2, the fourth clock control terminals CK4 of the driving unit R1 and the driving unit R3, and the second clock control terminal CK2 of the driving unit R2.
The second clock signal line CL2 is electrically connected to a second clock control terminal CK2 of each of the odd-numbered stages of driving units of the first driving circuit 140a, a fourth clock control terminal CK4 of each of the even-numbered stages of driving units of the first driving circuit 140a, a first clock control terminal CK1 of each of the odd-numbered stages of driving units of the second driving circuit 140b and a third clock control terminal CK3 of each of the even-numbered stages of driving units of the second driving circuit 140b. That is, the second clock signal line L2 is electrically connected to the second clock control terminals CK2 of the driving unit L1 and the driving unit L3, the fourth clock control terminal CK4 of the driving unit L2, the first clock control terminals CK1 of the driving unit R1 and the driving unit R3, and the third clock control terminal CK3 of the driving unit R2.
The third clock signal line CL3 is electrically connected to a third clock control terminal CK3 of each of the odd-numbered stages of driving units of the first driving circuit 140a, a first clock control terminal CK1 of each of the odd-numbered stages of the driving units of the first driving circuit 140a, a second clock control terminal CK2 of each of the odd-numbered stages of driving units of the second driving circuit 140b and a fourth clock control terminal CK4 of each of the even-numbered stages of driving units of the second driving circuit 140b. That is, the third clock signal line CL3 is electrically connected to the third clock control terminals CK3 of the driving unit L1 and the driving unit L3, the first clock control terminal CK1 of the driving unit L2, the second clock control terminals CK2 of the driving unit R1 and the driving unit R3, and the fourth clock control terminal CK4 of the driving unit R2.
The fourth clock signal line CL4 is electrically connected to a fourth clock control terminal CK4 of each of the odd-numbered stages of driving units of the first driving circuit 140a, a second clock control terminal CK2 of each of the even-numbered stages of driving units of the first driving circuit 140a, a third clock control terminal CK3 of each of the odd-numbered stages of driving units of the second driving circuit 140b, and a first clock control terminal CK1 of each of the even-numbered stages of driving units of the second driving circuit 140b. That is, the fourth clock signal line CL4 is electrically connected to the fourth clock control terminals CK4 of the driving unit L1 and the driving unit L3, the second clock control terminal CK2 of the driving unit L2, the third clock control terminals CK3 of the driving unit R1 and the driving unit R3, and the first clock control terminal CK1 of the driving unit R2.
That is to say, in each of the first driving circuit 140a and the second driving circuit 140b, the first clock control terminal CK1 of one driving unit is electrically connected to the third clock control terminal CK3 of an adjacent driving unit, and the second clock control terminal CK2 of one driving unit is electrically connected to the fourth clock control terminal CK4 of an adjacent driving unit.
For the first driving circuit 140a, the first clock signal line CL1 is electrically connected to the first clock control terminal CK1 of a driving unit which firstly occurs in the first direction, i.e., the driving unit L1; the second clock signal line CL2 is electrically connected to the second clock control terminal CK2 of the driving unit L1; the third clock signal line CL3 is electrically connected to the third clock control terminal CK3 of the driving unit L1; and the fourth clock signal line CL4 is electrically connected to the fourth clock control terminal CK4 of the driving unit L1.
For the second driving circuit 140b, the first clock signal line CL1 is electrically connected to the fourth clock control terminal CK4 of a driving unit firstly which occurs in the first direction, i.e., the driving unit R1; the second clock signal line CL2 is electrically connected to the first clock control terminal CK1 of the driving unit R1; the third clock signal line CL3 is electrically connected to the second clock control terminal CK2 of the driving unit R1; and the fourth clock signal line CL4 is electrically connected to the third clock control terminal CK3 of the driving unit R1.
In this way, the timing sequences of the clock control terminals of the driving unit R1, which firstly occurs in the first direction, of the second driving circuit 140b are respectively shifted by a time delay of T relative to the timing sequences of corresponding clock control terminals of the driving unit L1, which firstly occurs in the first direction, of the first driving circuit 140a, and accordingly, the output of the driving unit R1 of the second driving circuit 140b is also delayed with the time delay of T relative to the output of the driving unit L1. Therefore, if driving units of the first driving circuit 140a and drive units of the second driving circuit 140b are arranged alternately, in the first direction, the low level input to one row of gate line is later than that input to a previous row of gate line by the time delay of T, thereby driving the gate lines row by row.
The array substrate also includes two operation modes of a driving phase S1 and a discharging phase S2. It is explained still with a case that the driving operation is performed in the first direction.
During the driving phase S1, a first clock signal, a second clock signal, a third clock signal and a fourth clock signal are respectively input to the first clock signal line CL1, the second clock signal line CL2, the third clock signal line CL3 and the fourth clock signal line CL4. The first clock signal to the fourth clock signal have the same period and waveform, and an (i+1)th clock signal is delayed by a time delay of T relative to an i-th clock signal, where i is a positive integer less than 4. As shown in
During the discharging phase, low level signals are to be input to the first clock control terminal CK1 and the third clock control terminal CK3 of each stage of driving unit of the first driving circuit 140a and the second driving circuit 140b. For the first driving circuit 140a, the first clock signal line CL1 and the third clock signal line CL3 respectively supply signals to the first clock control terminals CK1 and the third clock control terminals CK3; and for the second driving circuit 140b, the second clock signal line CL2 and the fourth clock signal line CL4 respectively supply signals to the first clock control terminals CK1 and the third clock control terminals CK3. Hence, during the discharging phase, low level signals are applied to all of the first clock signal line CL1 to the fourth clock signal line CL4, and high level signals are applied to a U2D signal line and a D2U signal line. In this case, based on the above description of the driving unit and the driving circuit, each stage of driving unit continuously outputs a low level signal to a corresponding gate line.
In the above embodiments of the disclosure, it is illustrated with a case that both the driving phase and the discharging phase are triggered by low levels, i.e., the switching elements in the array substrate are turned on by low levels. In other embodiments of the disclosure, both the driving phase and the discharging phase are triggered by high levels, i.e., the switching elements in the array substrate are turned on by high levels. Simple changes made to the transistors and the circuits still fall within the scope of protection of the disclosure.
In the array substrate according to the embodiments of the disclosure, at least one driving circuit may output driving signals simultaneously to discharge electric charges. Particularly, in an alternately-driven array substrate, driving circuits at the left side and the right side control corresponding transistors to turn on simultaneously. In addition, the array substrate according to the embodiments of the disclosure does not need to be provided with extra control lines or extra control signals, thereby simplifying the driving of the panel and solving the problem of the ghosting and image flutter.
A display apparatus is further provided in the disclosure, which includes the array substrate according to the embodiments of the disclosure and an opposed substrate provided opposite to the array substrate. As shown in
It should be noted that, the above embodiments may be referred to each other and combined to use. Although the preferred embodiments of the disclosure have been disclosed above, they are not used to limit the disclosure. Those skilled in the art can make possible changes and modifications to the technical solutions of the disclosure by utilizing the disclosed method and technical content without departing from the spirit and scope of the disclosure. Hence, all the simple variations, equivalent changes and modifications made to the above embodiments based on the technical essence of the disclosure without departing from the content of the technical solutions of the disclosure fall within the scope of protection of the technical solutions of the disclosure.
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