Patent Application
20240312389
This application claims the priority and benefit of Chinese patent application number 2023102898475, titled “Driving Circuit, Driving Method, and Display Device” and filed Mar. 17, 2023, with China National Intellectual Property Administration, the entire contents of which are incorporated herein by reference.
The present application relates to the field of display technology, and in particular to a driving circuit, a driving method and a display device.
The description provided in this section is intended for the mere purpose of providing background information related to the present application but doesn't necessarily constitute prior art.
In order to solve the problem that the power chip (Power IC) requires many pins when setting by means of analog resistors, hence complicated layout of the printed circuit board (PCB), more and more power chips use the digital method of the integrated circuit bus (Inter-Integrated Circuit, or i2c) to design the chip. However, the power chip designed using this solution may need to set a non-volatile memory (NVM) to store the set configuration information of the power chip, so as to ensure that the configuration information can be saved after power-off, thus avoiding the failure to store the set configuration information of the power chip when the power is off.
However, since an additional non-volatile memory needs to be set in the power chip, the structure of the printed circuit board in the display device is rendered complicated. Furthermore, the test steps are also increased during the packaging test, which increases labor costs and material costs, causing inconvenience.
In view of the above, it is therefore one purpose of the present application to provide a driving circuit, a driving method and a display device, without the need of setting a non-volatile memory in the power chip, thereby reducing labor costs and material costs.
The application discloses a driving circuit. The driving circuit includes a memory, a timing controller and a power chip. The memory is connected to each of the timing controller and the power chip. The power chip includes a first analyzing module and a working module. An input terminal of the first analyzing module is connected to the timing controller. An output terminal of the first analyzing module is connected to the working module. The working module includes a fault output terminal. The timing controller includes a second analyzing module and a reset terminal. An input terminal of the second analyzing module is connected to an output terminal of the memory. The reset terminal is connected to the fault output terminal. During a power-on phase, the timing controller reads and analyzes the driving data in the memory through the second analyzing module, and the timing controller transmits the analyzed driving data to the first analyzing module of the power chip for use by the power chip. In a fault phase, the fault output terminal outputs a fault signal, and the reset terminal receives the fault signal to control the timing controller and the power chip to reset in tandem.
In some embodiments, the working module includes a register, a logic module, a delay control module and a transistor. An input terminal of the register is connected to an output terminal of the first analyzing module. An output terminal of the register is connected to an input terminal of the logic module. An output terminal of the logic module is connected to an input terminal of the delay control module. An output terminal of the delay control module is connected to a gate of the transistor. The power chip further includes a first ground terminal connected to a drain of the transistor. The fault output terminal is connected to a source of the transistor. In the fault phase, the logic module outputs a high-level signal, which is delayed by the delay control module and then output to the gate of the transistor to control the transistor to be turned on, so that the fault output terminal outputs a corresponding fault signal.
In some embodiments, the delay control module includes an inverter, a delay controller and a logic OR gate. Both the input terminal of the inverter and the input terminal of the delay controller are connected to the output terminal of the logic module. Both the output terminal of the inverter and the output terminal of the delay controller are connected to the input terminal of the logical OR gate. The output terminal of the logic OR gate is connected to the gate of the transistor. In the normal display phase, the logic module outputs a low-level signal, and the inverter and delay controller receive the low-level signal output by the logic module and output a low-level signal. At this time, the logic OR gate outputs a low level signal. In the fault phase, the logic module outputs a high level signal, the inverter and the delay controller receive the high level signal output by the logic module, the inverter outputs a high level signal to the logic OR gate, and the delay controller outputs a low level signal to logic OR gate. At this time, the output of the logic OR gate is a low level signal. After a delay of N seconds, the delay controller outputs a high-level signal to the logic OR gate, and the logic OR gate outputs a high-level signal to turn on the transistor. Said N is greater than 0.
In some embodiments, the timing controller includes a reset control module, and the input terminal of the reset control module is connected to the reset terminal. The reset terminal receives the fault signal and sends it to the reset control module, and the reset control module controls the timing controller to reset.
In some embodiments, the driving circuit further includes a power supply interface, a pull-up resistor, a storage capacitor and a second ground terminal. The power supply interface is connected to the input terminal of the pull-up resistor. The output terminal of the pull-up resistor is connected to the reset terminal, to the fault output terminal and to the input terminal of the storage capacitor. The output terminal of the storage capacitor is connected to the second ground terminal.
In some embodiments, the connection between the memory and each of the timing controller and the power chip is an integrated circuit bus connection.
In some embodiments, the memory is a charged erasable programmable read-only memory.
In some embodiments, the driving circuit includes a printed circuit board, where the memory, the timing controller and the power chip are all arranged on the printed circuit board.
The present application further discloses a driving method, which is applied to the above-mentioned driving circuit, comprising steps:
Compared with the solution of setting non-volatile memory in the power chip, this application sets the first analyzing module, the second analyzing module and the memory, where the second analyzing module reads and analyzes the driving data stored in the memory, and transmits the analyzed driving data partially to the first analyzing module for use by the power chip, so that there is no need to set non-volatile memory in the power chip, which reduces labor costs and material costs. Furthermore, the fault output terminal of the power chip is connected to the reset terminal of the timing controller. When the power chip fails, the fault output terminal of the power chip will output a fault signal to the reset terminal, and the reset terminal receives the fault signal to control the timing controller and the power chip to reset in tandem, so that the timing controller does not need to set the readback function, reducing the design complexity of the timing controller.
The accompanying drawings are used to provide a further understanding of the embodiments according to the present application, and constitute a part of the specification. They are used to illustrate the embodiments according to the present application, and explain the principle of the present application in conjunction with the text description. Apparently, the drawings in the following description merely represent some embodiments of the present disclosure, and for those having ordinary skill in the art, other drawings may also be obtained based on these drawings without investing creative efforts. A brief description of the accompanying drawings is provided as follows.
In the drawings: 100, driving circuit; 110, memory; 120, timing controller; 121, second analyzing module; 122, reset control module; 130, power chip; 131, first analyzing module; 132, working module; 133, register; 134, logic module; 135, delay control module; 137, inverter; 138, delay controller; 139, logic OR gate; 140, pull-up resistor; 150, storage capacitor; 160, printed circuit board; 200, display panel; 300, display device.
It should be understood that the terms used herein, the specific structures and function details disclosed herein are intended for the mere purposes of describing specific embodiments and are representative. However, this application may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.
As used herein, terms “first”, “second”, or the like are merely used for illustrative purposes, and shall not be construed as indicating relative importance or implicitly indicating the number of technical features specified. Thus, unless otherwise specified, the features defined by “first” and “second” may explicitly or implicitly include one or more of such features. Terms “multiple”, “a plurality of”, and the like mean two or more. Term “comprising”, “including”, and any variants thereof mean non-exclusive inclusion, so that one or more other features, integers, steps, operations, units, components, and/or combinations thereof may be present or added.
In addition, terms “center”, “transverse”, “up”, “down”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, or the like are used to indicate orientational or relative positional relationships based on those illustrated in the drawings. They are merely intended for simplifying the description of the present disclosure, rather than indicating or implying that the device or element referred to must have a particular orientation or be constructed and operate in a particular orientation. Therefore, these terms are not to be construed as restricting the present disclosure.
Furthermore, as used herein, terms “installed on”, “mounted on”, “connected to”, “coupled to”, “connected with”, and “coupled with” should be understood in a broad sense unless otherwise specified and defined. For example, they may indicate a fixed connection, a detachable connection, or an integral connection. They may denote a mechanical connection, or an electrical connection. They may denote a direct connection, a connection through an intermediate, or an internal connection between two elements. For those of ordinary skill in the art, the specific meanings of the above terms as used in the present application can be understood depending on specific contexts.
The present application will be described in detail below with reference to the accompanying drawings and optional embodiments. It should be noted that, should no conflict is present, the various embodiments or technical features described below can be combined arbitrarily to form new embodiments.
As shown in
During the power-on phase, the timing controller 120 reads and analyzes the driving data located in the memory 110 through the second analyzing module 121, and the timing controller 120 transmits the analyzed driving data to the first analyzing module 131 of the power chip 130 for use by the power chip 130, so that there is no need to set a non-volatile memory 110 in the power chip 130. Compared with the solution of setting the non-volatile memory 110 in the power chip 130, the cost and manufacturing process of the non-volatile memory 110 are saved, thereby reducing the material cost and labor cost of the power chip 130. In the fault phase, the fault output terminal Fault outputs a fault signal, and the reset terminal Reset receives the fault signal to control the timing controller 120 and the power chip 130 to reset in tandem. During this process, the power chip 130 will actively output a fault signal through the fault output terminal Fault. Since the reset terminal Reset of the timing controller 120 is connected to the fault output terminal Fault, the reset terminal Reset of the timing controller 120 will receive the fault signal output by the fault output terminal Fault, so that the timing controller 120 knows that the power chip 130 is in the fault phase at this time. The timing controller 120 can know whether the power chip 130 is in a failure phase without setting the readback function, and the timing controller 120 can also reset in tandem with the power chip 130, reducing the complexity of setting the timing controller 120. That is, the timing controller 120 of the original design can be used without making improvements to the timing controller 120, reducing the setup cost of the driving circuit 100. When the timing controller 120 and the power chip 130 are reset, the timing controller 120 reads and analyzes the driving data located in the memory 110 through the second analyzing module 121, and transmits the analyzed driving data to the first analyzing module 131 of the power chip 130 for use by the power chip 130, to complete the reset and display images normally. It should be noted that the memory 110 stores the first driving data for driving the timing controller 120 and the second driving data for driving the power chip 130, making full use of the space in the memory 110. The first driving data and the second driving data need to be analyzed by the timing controller 120 before they can be used.
In this embodiment, the connection between the memory 110 and each of the timing controller 120 and the power chip 130 is an integrated circuit bus (i2c) connection. Using the i2c communication protocol only needs one data line and one clock line to accomplish half-duplex communication. After the power chip 130 adopts i2c, related settings can be modified through i2c. Both the first analyzing module 131 and the second analyzing module 121 are i2c control modules used for receiving data transmitted via the integrated circuit bus i2c. Furthermore, the timing controller 120 serves as a communication master, and the power chip 130 serves as a communication slave. Since the timing controller 120 has better function expandability than the power chip 130, using it as the communication master device can also effectively reduce the cost of the power chip 130 and make full use of the processing capability of the timing controller 120. The memory 110 is an electrically erasable programmable read-only memory 110 (EEPROM). EEPROM is a user-changeable read-only memory 110, which can erase existing information and reprogram to write new data on special equipment such as computers. It has good stability and security, and has a flexible and wide application range, hence an ideal memory 110 for display driving devices.
Further, the working module 132 includes a register 133 (Register), a logic module 134 (Logic), a delay control module 135 and a transistor. An input terminal of the register 133 is connected to an output terminal of the first analyzing module 131. An output terminal of the register 133 is connected to an input terminal of the logic module 134. An output terminal of the logic module 134 is connected to the input terminal of the delay control module 135. An output terminal of the delay control module 135 is connected to a gate of the transistor. The power chip 130 further includes a first ground terminal GND1, the first ground terminal GND1 being connected to a drain of the transistor. The fault output terminal Fault is connected to a source of the transistor.
In the failure phase, the logic module 134 determines that the power chip 130 is faulty, and accordingly outputs a high-level signal, which is output to the gate of the transistor after being delayed by the delay control module 135 thus controlling the transistor to be turned on, so that the fault output terminal Fault outputs a corresponding fault signal. The reset terminal Reset receives the fault signal so that the timing controller 120 knows that the power chip 130 is faulty at this time, and then the timing controller 120 and the power chip 130 are controlled to reset in tandem to restore the driving data when images are displayed normally. While in the normal display phase, the logic module 134 determines that the power chip 130 is in a normal working state, and accordingly outputs a low level signal, which is output to the gate of the transistor through the delay control module 135. At this time, the transistor is not turned on, the fault output terminal Fault will not output a fault signal, and the reset terminal Reset will not receive a fault signal, so that the timing controller 120 continues to work normally. The setting of the delay control module 135 is intended for the purpose of reserving enough time to allow the voltages of the timing controller 120 and the power chip 130 to drop from high level to low level, and then recover from low level to high level to complete one reset. It should be noted that in the setting of the delay control module 135, the delay value may be set when the power chip 130 is manufactured, or it is also possible to modify the delay value through other external settings, where the specifics will not be described in detail, and designers can select and design according to actual needs.
Specifically, as shown in
During the normal display phase, the logic module 134 determines that the power chip 130 is in a normal working state, and so the logic module 134 outputs a low level signal. At this time, the inverter 137 and the delay controller 138 receive the low-level signal output by the logic module 134 and output a low-level signal to the logical OR gate 139. The logic OR gate 139 then outputs a low level signal to the gate of the transistor after receiving the low level signal. At this time, the transistor will not be turned on, the fault output terminal Fault and the reset terminal Reset are both high-level signals, and the timing controller 120 and the power chip 130 will not reset. During the failure phase, the logic module 134 judges that the power chip 130 is in a failure state, and so the logic module 134 outputs a high level signal. The inverter 137 and the delay controller 138 receive the high-level signal output by logic module 134, and so the inverter 137 outputs a high-level signal to logic OR gate 139. At this time, the delay controller 138 will still output a low level signal to the logic OR gate 139 under its own setting, so that the logic OR gate 139 outputs a low level signal. The transistor is temporarily not turned on, and after the delay N seconds preset by the delay controller 138, the delay controller 138 at this time will output a high level signal to the logic OR gate 139. The logic OR gate 139 receives the high-level signal from the delay controller 138 and from the inverter 137 at the same time, and so outputs a high-level signal to the gate of the transistor to turn on the transistor. At this time, the fault output terminal Fault of the power chip 130 and the reset terminal Reset of the timing controller 120 are low-level signals, and when the timing controller 120 detects that the reset terminal Reset is a low-level signal, it determines that the power chip 130 is in a fault phase at this time, so that the timing controller 120 and the power chip 130 are reset to restore the normal display of images. By setting the delay controller 138, when an abnormal fault occurs in the power chip 130, the power chip 130 will not reset immediately, but will notify the timing controller 120 after a delay of a period of time by the delay controller 138, so as to reserve a time slot for the voltages of the timing controller 120 and the power chip 130 to drop from a high level to a low level. Then the timing controller 120 and the power chip 130 perform the reset operation together, and the voltages of the timing controller 120 and the power chip 130 recover from a low level to a high level to complete the reset. A timing diagram of the reset terminal Reset and the fault output terminal Fault is shown in
Further, the timing controller 120 includes a reset control module 122 (Reset Control), and the input terminal of the reset control module 122 is connected to the reset terminal Reset. When an abnormal fault occurs in the power chip 130, the fault output terminal of the power chip 130 will output a fault signal, that is, output a low level signal as described above. The reset terminal receives the fault signal and sends it to the reset control module 122. After the reset control module 122 detects a fault signal, it controls the timing controller 120 to reset. When the power chip 130 is working normally, the fault output terminal of the power chip 130 outputs a high level signal, and the reset terminal is also a high level signal. When the reset control terminal detects that the reset terminal is a high-level signal, no reset is performed.
As shown in
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reading and parsing, by the timing controller, the driving data located in the memory;
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It should be noted that the limitations of various operations involved in this solution will not be deemed to limit the order of the operations, provided that they do not affect the implementation of the specific solution, so that the operations written earlier may be executed earlier or they may also be executed later or even at the same time. As long as the solution can be implemented, they should all be regarded as falling in the scope of protection of this application.
The technical solutions of the present application can be widely used in various display panels, such as TN (Twisted Nematic) display panels, IPS (In-Plane Switching) display panels, VA (Vertical Alignment) display panels, and MVA (Multi-Domain Vertical Alignment) display panels. Of course, other types of display panels, such as OLED (Organic Light-Emitting Diode) display panels, may also be applicable to the above solutions.
It should be noted that the inventive concept of the present application can be formed into many embodiments, but the length of the application document is limited and so these embodiments cannot be enumerated one by one. The technical features can be arbitrarily combined to form a new embodiment, and the original technical effect may be enhanced after the various embodiments or technical features are combined.
The foregoing description is merely a further detailed description of the present application made with reference to some specific illustrative embodiments, and the specific implementations of the present application will not be construed to be limited to these illustrative embodiments. For those having ordinary skill in the technical field to which this application pertains, numerous simple deductions or substitutions may be made without departing from the concept of this application, and shall all be regarded as falling in the scope of protection of this application.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202310289847.5 | Mar 2023 | CN | national |
