DRIVING CIRCUIT, DRIVING METHOD, AND DISPLAY PANEL

Abstract

A driving circuit, a driving method, and a display panel are disclosed. The driving circuit includes: a timing controller including a first pin; a power management chip including a second pin; a first shared discharge rod, wherein the power management chip is electrically connected to the first shared discharge rod; a second shared discharge rod, wherein the power management chip is electrically connected to the second shared discharge rod. This can avoid issues of abnormal images on the display panel.

Description

FIELD OF THE DISCLOSURE

The present application relates to the technical field of display technologies, and more particularly, to a driving circuit, a driving method, and a display panel.

DESCRIPTION OF RELATED ART

With the continuous improvement of information technology and living standards, people have higher and higher requirements for display quality such as transmittance and viewing angle. To improve the viewing angle, pixels need to be divided into multiple domains, but this will bring about the loss of transmittance. Therefore, the viewing angle and the transmittance are inversely related to benefits. Shared discharge rod technology is a technology that can improve low gray-scale viewing angles. The shared discharge rod technology is to have two shared discharge rods on the display panel. The two shared discharge rods are respectively a positive-polarity shared discharge rod and a negative-polarity shared discharge rod. voltages of the positive-polarity shared discharge rod and the negative-polarity shared discharge rod are inverted in a blanking time interval of each frame following a data signal, thereby improving the display viewing angle.

In a practical application, there are various circuit ways to realize a voltage inversion of the shared discharge rod. The existing solution is to realize a voltage switching through an integrated circuit bus communication between a timing controller and a power management chip. The integrated circuit bus between the timing controller and the power management chip in a circuit system has only one line. In addition to the timing controller and power management chip, the integrated circuit bus is usually connected to other modules, such as a system chip or a programming socket. If the timing controller and the power management chip communicate through the integrated circuit bus, and other modules also issue commands through the integrated circuit bus, it is easy to be disturbed, resulting in issues of abnormal images.

SUMMARY OF INVENTION

Technical Problems

The present application provides a driving circuit, a driving method, and a display panel to solve issues of abnormal images of the display panel.

Solution to Problem

Technical Solutions

The application provides a driving circuit, which includes:

• • a timing controller comprising a first pin;
  • a power management chip comprising a second pin;
  • a first shared discharge rod, wherein the power management chip is electrically connected to the first shared discharge rod;
  • a second shared discharge rod, wherein the power management chip is electrically connected to the second shared discharge rod;
  • wherein the first pin is electrically connected to the second pin, the power management chip is configured to output voltages with opposite polarities to the first shared discharge rod and the second shared discharge rod at the same time, the power management chip is used to invert a voltage of the first shared discharge rod and a voltage of the second shared discharge rod under a control of a level signal of the first pin in a blanking time interval of each frame.

Optionally, in some embodiments of the present application, the timing controller comprises:

• • a controller;
  • a register, wherein the controller is electrically connected to the register, and the register is electrically connected to the first pin.

Optionally, in some embodiments of the present application, the timing controller further comprises:

• • a pulse signal generator electrically connected to the controller.

Optionally, in some embodiments of the present application, the power management chip further comprises:

• • a decoder, wherein an input terminal of the decoder is electrically connected to the
  • a voltage conversion circuit, wherein the voltage conversion circuit comprises a first signal control terminal, a power supply access terminal, a first voltage output terminal, and a second voltage output terminal, the first signal control terminal is electrically connected to an output terminal of the decoder, the first voltage output terminal is electrically connected to the first shared discharge rod, and the second voltage output terminal is electrically connected to the second shared discharge rod. The voltage conversion circuit converts the voltage of the power access terminal into a first voltage and a second voltage, the first voltage and the second voltage are voltages with opposite polarities, and the voltage conversion circuit switches the voltage of the first voltage output terminal and the voltage of the second voltage output terminal between the first voltage and the second voltage under the signal control of the first signal control terminal.

Optionally, in some embodiments of the present application, the voltage conversion circuit includes a step-down control circuit.

Optionally, in some embodiments of the present application, the decoder comprises:

• • a second signal control terminal electrically connected to the pulse signal generator;
  • wherein the decoder is configured to decode the level signal of the first pin under a signal control of the second signal control terminal and then transmits the level signal of the first pin to the first signal control terminal.

Correspondingly, the present application also provides a driving method of a driving circuit, wherein the driving circuit comprises:

• • a timing controller comprising a first pin;
  • a power management chip comprising a second pin;
  • a first shared discharge rod, wherein the power management chip is electrically connected to the first shared discharge rod;
  • a second shared discharge rod, wherein the power management chip is electrically connected to the second shared discharge rod;
  • wherein the first pin is electrically connected to the second pin, the power management chip is configured to output voltages with opposite polarities to the first shared discharge rod and the second shared discharge rod at the same time, the power management chip is configured to invert a voltage of the first shared discharge rod and a voltage of the second shared discharge rod under a control of a level signal of the first pin in a blanking time interval of each frame;
  • wherein the method comprises the following steps:
  • wherein in the blanking time interval of each frame, the timing controller controls the level signal of the first pin to switch between a high level and a low level;
  • wherein the power management chip is configured to invert the voltage of the first shared discharge rod and the voltage of the second shared discharge rod under the control of the level signal of the first pin in the blanking time interval of each frame.

Optionally, in some embodiments of the present application, in the blanking time interval of each frame, the timing controller controlling the level signal of the first pin to switch between the high level and the low level comprises:

• • the timing controller switching the level signal of the first pin between the high level and the low level under a control of a frame start signal of each frame.

Optionally, in some embodiments of the present application, the power management chip configured to invert the voltage of the first shared discharge rod and the voltage of the second shared discharge rod under the control of the level signal of the first pin in the blanking time interval of each frame comprises:

• • in the blanking time interval of each frame, when the level signal of the first pin is at the high level, the power management chip outputs a positive voltage to the first shared discharge rod, and the power management chip outputs a negative voltage to the second shared discharge rod; when the level signal of the first pin is at the low level, the power management chip outputs the negative voltage to the first shared discharge rod, and the power management chip outputs the positive voltage to the second shared discharge rod.

Optionally, in some embodiments of the present application, the power management chip configured to invert the voltage of the first shared discharge rod and the voltage of the second shared discharge rod under the control of the level signal of the first pin in the blanking time interval of each frame comprises:

• • in the blanking time interval of each frame, when the level signal of the first pin is at the high level, the power management chip outputs a negative voltage to the first shared discharge rod, and the power management chip outputs a positive voltage to the second shared discharge rod; when the level signal of the first pin is at the low level, the power management chip outputs the positive voltage to the first shared discharge rod, and the power management chip outputs the negative voltage to the second shared discharge rod.

Optionally, in some embodiments of the present application, the timing controller comprises:

• • a controller;
  • a register, wherein the controller is electrically connected to the register, and the register is electrically connected to the first pin.

Optionally, in some embodiments of the present application, the timing controller further comprises:

• • a pulse signal generator electrically connected to the controller.

Optionally, in some embodiments of the present application, the power management chip further comprises:

• • a decoder, wherein an input terminal of the decoder is electrically connected to the second pin;
  • a voltage conversion circuit, wherein the voltage conversion circuit comprises a first signal control terminal, a power supply access terminal, a first voltage output terminal, and a second voltage output terminal, the first signal control terminal is electrically connected to an output terminal of the decoder, the first voltage output terminal is electrically connected to the first shared discharge rod, and the second voltage output terminal is electrically connected to the second shared discharge rod.

Optionally, in some embodiments of the present application, the decoder comprises:

• • a second signal control terminal electrically connected to the pulse signal generator;
  • wherein the decoder is configured to decode the level signal of the first pin under a signal control of the second signal control terminal and then transmits the level signal of the first pin to the first signal control terminal.

Correspondingly, the present application also provides a display panel, the display panel comprises a plurality of sub-pixels arranged in an array and a driving circuit, wherein the driving circuit comprises:

• • a timing controller comprising a first pin;
  • a power management chip comprising a second pin;
  • a first shared discharge rod, wherein the power management chip is electrically connected to the first shared discharge rod;
  • a second shared discharge rod, wherein the power management chip is electrically connected to the second shared discharge rod;
  • wherein the first pin is electrically connected to the second pin, the power management chip is configured to output voltages with opposite polarities to the first shared discharge rod and the second shared discharge rod at the same time, the power management chip is used to invert a voltage of the first shared discharge rod and a voltage of the second shared discharge rod under a control of a level signal of the first pin in a blanking time interval of each frame;
  • wherein the first shared discharge rod of the driving circuit is electrically connected to the sub-pixels of a first column, and the second shared discharge rod of the driving circuit is electrically connected to the sub-pixels of a second column.

Optionally, in some embodiments of the present application, the timing controller comprises:

• • a controller;
  • a register, wherein the controller is electrically connected to the register, and the register is electrically connected to the first pin.

Optionally, in some embodiments of the present application, the timing controller further comprises:

• • a pulse signal generator electrically connected to the controller.

Optionally, in some embodiments of the present application, the power management chip further comprises:

• • a decoder, wherein an input terminal of the decoder is electrically connected to the second pin;
  • a voltage conversion circuit, wherein the voltage conversion circuit comprises a first signal control terminal, a power supply access terminal, a first voltage output terminal, and a second voltage output terminal, the first signal control terminal is electrically connected to an output terminal of the decoder, the first voltage output terminal is electrically connected to the first shared discharge rod, and the second voltage output terminal is electrically connected to the second shared discharge rod.

Optionally, in some embodiments of the present application, the decoder comprises:

• • a second signal control terminal electrically connected to the pulse signal generator;
  • wherein the decoder is configured to decode the level signal of the first pin under a signal control of the second signal control terminal and then transmits the level signal of the first pin to the first signal control terminal.

ADVANTAGES OF INVENTION

Beneficial Effects

The present application provides a driving circuit, a driving method and a display panel, wherein the driving circuit includes: a timing controller comprising a first pin; a power management chip comprising a second pin; a first shared discharge rod, wherein the power management chip is electrically connected to the first shared discharge rod; a second shared discharge rod, wherein the power management chip is electrically connected to the second shared discharge rod; wherein the first pin is electrically connected to the second pin, the power management chip is configured to output voltages with opposite polarities to the first shared discharge rod and the second shared discharge rod at the same time, the power management chip is used to invert a voltage of the first shared discharge rod and a voltage of the second shared discharge rod under a control of a level signal of the first pin in a blanking time interval of each frame. The present application uses pins to transmit level signals between the timing controller and the power management chip. Then, the power management chip controls the polarity reversal of the voltage of the first shared discharge rod and the voltage of the second shared discharge rod according to the level signal. Therefore, the issues that the level signal is disturbed and causes the display panel to produce abnormal issues can be avoided.

BRIEF DESCRIPTION OF DRAWINGS

Description of Attached Drawings

In order to illustrate the technical solutions in the embodiments of the present application more clearly, the following briefly introduces the accompanying drawings that are used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can also be obtained from these drawings without creative effort.

FIG. 1 is a schematic diagram of a driving circuit provided by the present application.

FIG. 2 is a schematic diagram of a timing controller of a driving circuit provided by the present application.

FIG. 3 is a schematic diagram of a first embodiment of a power management chip of a driving circuit provided by the present application.

FIG. 4 is a schematic diagram of a second embodiment of a power management chip of a driving circuit provided by the present application.

FIG. 5 is a flowchart of a driving method provided by the present application.

FIG. 6 is a schematic diagram of a display panel provided by the present application.

EMBODIMENTS OF INVENTION

Detailed Description of Preferred Embodiments

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

In the description of the present application, it should be understood that the terms “first” and “second” are only used for description purposes and cannot be interpreted as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, features defined as “first” and “second” may expressly or implicitly include one or more of the features. In the description of the present application, “plurality” means two or more, unless otherwise expressly and specifically defined.

The present application provides a driving circuit, a driving method, and a display panel, which will be described in detail below. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments of the present application.

Refer to FIG. 1, which is a schematic diagram of a driving circuit 100 provided by the present application. The present application provides the driving circuit 100, which includes: a timing controller 10, a power management chip 20, a first shared discharge rod 30, and a second shared discharge rod 40.

The timing controller 10 includes a first pin 11. The power management chip 20 includes a second pin 21. The power management chip 20 is electrically connected to the first shared discharge rod 30. The power management chip 20 is electrically connected to the second shared discharge rod 40.

The first pin 11 is electrically connected to the second pin 21. The power management chip 20 simultaneously outputs voltages with opposite polarities to the first shared discharge rod 30 and the second shared discharge rod 40. The timing controller 10 controls the level signal of the first pin 11 to switch between a high level and a low level in a blanking time interval of each frame.

The power management chip 20 is used to invert the polarity of the voltages of the first shared discharge rod 30 and the voltage of the second shared discharge rod 40 in the blanking time interval of each frame under the control of the level signal of the first pin 11.

Specifically, in some embodiments, when the level signal of the first pin 11 is at a high level, the power management chip 20 outputs a positive voltage to the first shared discharge rod 30, and the power management chip 20 outputs a negative voltage to the second shared discharge rod 40. When the level signal of the first pin 11 is at a low level, the power management chip 20 outputs a negative voltage to the first shared discharge rod 30, and the power management chip 20 outputs a positive voltage to the second shared discharge rod 40. The positive voltage is positive 8 volts and the negative voltage is negative 6 volts.

The present application uses the timing controller 10 to control the level signal of the first pin 11 to switch between a high level and a low level in the blanking time interval of each frame, and the first pin 11 is directly electrically connected to the second pin 21. Therefore, the power management chip 20 can directly obtain the signal of the first pin 11. The timing controller 10 does not need to issue instructions to the power management chip 20 through the integrated circuit bus. The power management chip 20 reverses the polarity of the voltage of the first shared discharge rod 30 and the voltage of the second shared discharge rod 40 in the blanking time interval of each frame under the control of the level signal of the first pin 11. Therefore, the present application will not be disturbed by external signals in the process of realizing the inversion of the voltage polarity of the shared discharge rods, thereby solving issues of abnormal images of the display panel 1000.

In some embodiments, the timing controller 10 controls the level signal of the first pin 11 to switch between a high level and a low level according to a frame start signal of each frame. The frame start signal of each frame is located at the beginning of the blanking time interval of each frame. Therefore, after obtaining the frame start signal of each frame, the timing controller 10 can control the level signal of the first pin 11 to switch between the high level and the low level. It is conceivable that the blanking time interval of each frame can also be determined in other ways as long as the timing controller 10 can control the level signal of the first pin 11 to switch between a high level and a low level in the blanking time interval of each frame.

In some other embodiments of the present application, when the level signal of the first pin 11 is at a high level, the power management chip 20 outputs a negative voltage to the first shared discharge rod 30, and the power management chip 20 outputs a positive polarity voltage to the second shared discharge rod 40. When the level signal of the first pin 11 is a low level, the power management chip 20 outputs a positive voltage to the first shared discharge rod 30, and the power management chip 20 outputs a negative voltage to the second shared discharge rod 40.

Refer to FIG. 2, which is a schematic diagram of a timing controller 10 of a driving circuit 100 provided by the present application. In some embodiments, the timing controller 10 includes:

• • a controller 12;
  • a register 13, wherein the controller 12 is electrically connected to the register 13, and the register 13 is electrically connected to the first pin 11.

Specifically, the controller 12 inputs data of a high-level signal or data of a low-level signal to the register 13 in the blanking time interval of each frame. For example, in the blanking time interval of the previous frame, the controller 12 inputs the data of the high-level signal to the register 13. Then, in the blanking time interval of the next frame, the controller 12 inputs the data of the low-level signal to the register 13. Therefore, the timing controller 10 controls the level signal of the first pin 11 to switch between a high level and a low level within the blanking time interval of each frame. The power management chip 20 is electrically connected to the first pin 11 through the second pin 21, so that a high-level signal or a low-level signal can be obtained. Thus, the polarity of the voltage of the first shared discharge rod 30 and the polarity of the voltage of the second shared discharge rod 40 are controlled to be reversed.

Still further, in some embodiments, the timing controller 10 further includes:

• • a pulse signal generator 14 electrically connected to the controller 12.

Specifically, the pulse signal generator 14 is used for generating a frame start signal of each frame. In this way, the pulse signal generator 14 sends the frame start signal of each frame to the controller 12. The controller 12 then inputs the data of the high-level signal or the data of the low-level signal to the register 13 according to the frame start signal of each frame. In an embodiment of the present application, when the controller 12 receives the frame start signal of the previous frame, the controller 12 inputs the data of the high-level signal to the register 13. Then, when the controller 12 receives the frame start signal of the next frame, the controller 12 inputs the data of the low-level signal to the register 13. Thus, the timing controller 10 controls the level signal of the first pin 11 to switch between a high level and a low level according to the frame start signal of each frame. The power management chip 20 is electrically connected to the first pin 11 through the second pin 21, so that a high-level signal or a low-level signal can be obtained. Thus, the polarity of the voltage of the first shared discharge rod 30 and the polarity of the voltage of the second shared discharge rod 40 are controlled to be reversed.

Refer to FIG. 3, which is a schematic diagram of a first embodiment of a power management chip 20 of a driving circuit 100 provided by the present application. In some embodiments, the power management chip 20 further includes:

a decoder 22, wherein an input terminal of the decoder 22 is electrically connected to the second pin 21;

• • a voltage conversion circuit 23 including a first signal control terminal 231, a power access terminal 232, a first voltage output terminal 233, and a second voltage output terminal 234, wherein the first signal control terminal 231 is electrically connected to the output terminal of the decoder 22, the first voltage output terminal 233 is electrically connected to the first shared discharge rod 30, the second voltage output terminal 234 is electrically connected to the second shared discharge rod 40, the voltage conversion circuit 23 converts the voltage of the power access terminal 232 into a first voltage and a second voltage, the first voltage and the second voltage are voltages with opposite polarities, and the voltage conversion circuit 23 switches the voltage of the first voltage output terminal 233 and the voltage of the second voltage output terminal 234 between the first voltage and the second voltage under the signal control of the first signal control terminal 231.

That is, after receiving the level signal of the first pin 11 through the second pin 21 in the blanking time interval of each frame, the decoder 22 decodes the level signal of the first pin 11 to form a control signal. The signal is sent to the first signal control terminal 231 of the voltage conversion circuit 23. The voltage conversion circuit 23 switches the voltage of the first voltage output terminal 233 and the voltage of the second voltage output terminal 234 between the first voltage and the second voltage under the signal control of the first signal control terminal 231. Thus, the polarity inversion of the voltage of the first shared discharge rod 30 and the polarity inversion of the voltage of the second shared discharge rod 40 are controlled within the blanking time interval of each frame.

Further, in some embodiments, the voltage conversion circuit 23 includes a step-down control circuit. The step-down control circuit adopts the circuit of the prior art. The existing step-down control circuit can convert the high level of the power input terminal 232 into multiple voltages. The plurality of voltages include at least a first voltage and a second voltage. The step-down control circuit switches the voltage of the first voltage output terminal 233 and the voltage of the second voltage output terminal 234 between the first voltage and the second voltage under the signal control of the first signal control terminal 231.

Specifically, in an embodiment, when the level signal of the first pin 11 is at a high level, the step-down control circuit outputs a positive voltage to the first shared discharge rod 30, and the step-down control circuit outputs a negative voltage to the second shared discharge rod 40. When the level signal of the first pin 11 is at a low level, the step-down control circuit outputs a negative voltage to the first shared discharge rod 30, and the step-down control circuit outputs a positive voltage to the second shared discharge rod 40.

Refer to FIG. 4, which is a schematic diagram of a second embodiment of a power management chip 20 of a driving circuit 100 provided by the present application. In some embodiments of the present application, the decoder 22 includes:

• • a second signal control terminal 221, wherein the second signal control terminal 221 is electrically connected to the pulse signal generator 14;
  • wherein the decoder 22 is used for decoding the level signal of the first pin 11 under the signal control of the second signal control terminal 221 and then sending it to the first signal control terminal 231.

That is, after receiving the level signal of the first pin 11 through the second pin 21, and at the same time, after the pulse signal generator 14 sends the frame start signal of each frame to the decoder 22, the decoder 22 decodes the level signal of the first pin 11 to form a control signal and sends it to the first signal control terminal 231 of the voltage conversion circuit 23.

Refer to FIG. 1 and FIG. 5, FIG. 5 is a flowchart of a driving method provided by the present application. The embodiment of the present application also provides a driving method based on the above-mentioned driving circuit 100, which includes the following steps:

• • S10, in the blanking time interval of each frame, the timing controller 10 controls the level signal of the first pin 11 to switch between a high level and a low level;
  • S20, the power management chip 20 is configured to invert the voltage of the first shared discharge rod 30 and the voltage of the second shared discharge rod 40 under the control of the level signal of the first pin 11 in the blanking time interval of each frame.

In some embodiments, in the blanking time interval of each frame, the timing controller 10 controlling the level signal of the first pin 11 to switch between the high level and the low level comprises:

• • the timing controller 10 switching the level signal of the first pin 11 between the high level and the low level under a control of a frame start signal of each frame.

The frame start signal of each frame is located at the beginning of the blanking time interval of each frame. Therefore, after obtaining the frame start signal of each frame, the timing controller 10 can control the level signal of the first pin 11 to switch between the high level and the low level. It is conceivable that the blanking time interval of each frame can also be determined in other ways as long as the timing controller 10 can control the level signal of the first pin 11 to switch between a high level and a low level within the blanking time interval of each frame.

In some embodiments, the power management chip 20 configured to invert the voltage of the first shared discharge rod 30 and the voltage of the second shared discharge rod 40 under the control of the level signal of the first pin 11 in the blanking time interval of each frame comprises:

• • in the blanking time interval of each frame, when the level signal of the first pin 11 is at the high level, the power management chip 20 outputs a positive voltage to the first shared discharge rod 30, and the power management chip 20 outputs a negative voltage to the second shared discharge rod 40; when the level signal of the first pin 11 is at the low level, the power management chip 20 outputs the negative voltage to the first shared discharge rod 30, and the power management chip 20 outputs the positive voltage to the second shared discharge rod 40.

In some embodiments, the power management chip 20 configured to invert the voltage of the first shared discharge rod 30 and the voltage of the second shared discharge rod 40 under the control of the level signal of the first pin 11 in the blanking time interval of each frame comprises:

• • in the blanking time interval of each frame, when the level signal of the first pin 11 is at the high level, the power management chip 20 outputs a negative voltage to the first shared discharge rod 30, and the power management chip 20 outputs a positive voltage to the second shared discharge rod 40; when the level signal of the first pin 11 is at the low level, the power management chip 20 outputs the positive voltage to the first shared discharge rod 30, and the power management chip 20 outputs the negative voltage to the second shared discharge rod 40.

Refer to FIG. 6, which is a schematic diagram of a display panel 1000 provided by the present application. Correspondingly, an embodiment of the present application further provides a display panel 1000. The display panel 1000 includes a plurality of sub-pixels 200 arranged in an array and the above-mentioned driving circuit 100. The first shared discharge rod 30 of the driving circuit 100 is electrically connected to the sub-pixels 200 of a first column. The second shared discharge rod 40 of the driving circuit 100 is electrically connected to the sub-pixels 200 of a second column.

The sub-pixels 200 of the first column are adjacent to the sub-pixels 200 of the second column, and the voltages of the first and second shared discharge rods 30 and 40 are inverted in the blanking time interval of each frame following the data signal, thereby improving the display viewing angle.

The display panel provided by the embodiments of the present application has been described in detail above. Specific examples are used herein to illustrate the principles and implementations of the present application. The descriptions of the above embodiments are only used to help understand the method and the core idea of the present application. In addition, for those skilled in the art, according to the idea of the present application, there will be changes in the specific embodiments and application scope. In conclusion, the content of this specification should not be construed as a limitation on this application.

Claims

1. A driving circuit, comprising: a timing controller comprising a first pin;a power management chip comprising a second pin;a first shared discharge rod, wherein the power management chip is electrically connected to the first shared discharge rod;a second shared discharge rod, wherein the power management chip is electrically connected to the second shared discharge rod;wherein the first pin is electrically connected to the second pin, the power management chip is configured to output voltages with opposite polarities to the first shared discharge rod and the second shared discharge rod at the same time, the power management chip is used to invert a voltage of the first shared discharge rod and a voltage of the second shared discharge rod under a control of a level signal of the first pin in a blanking time interval of each frame.

2. The driving circuit of claim 1, wherein the timing controller comprises: a controller;a register, wherein the controller is electrically connected to the register, and the register is electrically connected to the first pin.

3. The driving circuit of claim 2, wherein the timing controller further comprises: a pulse signal generator electrically connected to the controller.

4. The driving circuit of claim 3, wherein the power management chip further comprises: a decoder, wherein an input terminal of the decoder is electrically connected to the second pin;a voltage conversion circuit, wherein the voltage conversion circuit comprises a first signal control terminal, a power supply access terminal, a first voltage output terminal, and a second voltage output terminal, the first signal control terminal is electrically connected to an output terminal of the decoder, the first voltage output terminal is electrically connected to the first shared discharge rod, and the second voltage output terminal is electrically connected to the second shared discharge rod.

5. The driving circuit of claim 4, wherein the decoder comprises: a second signal control terminal electrically connected to the pulse signal generator;wherein the decoder is configured to decode the level signal of the first pin under a signal control of the second signal control terminal and then transmits the level signal of the first pin to the first signal control terminal.

6. A driving method of a driving circuit, wherein the driving circuit comprises: a timing controller comprising a first pin;a power management chip comprising a second pin;a first shared discharge rod, wherein the power management chip is electrically connected to the first shared discharge rod;a second shared discharge rod, wherein the power management chip is electrically connected to the second shared discharge rod;wherein the first pin is electrically connected to the second pin, the power management chip is configured to output voltages with opposite polarities to the first shared discharge rod and the second shared discharge rod at the same time, the power management chip is configured to invert a voltage of the first shared discharge rod and a voltage of the second shared discharge rod under a control of a level signal of the first pin in a blanking time interval of each frame;wherein the method comprises the following steps:wherein in the blanking time interval of each frame, the timing controller controls the level signal of the first pin to switch between a high level and a low level;wherein the power management chip is configured to invert the voltage of the first shared discharge rod and the voltage of the second shared discharge rod under the control of the level signal of the first pin in the blanking time interval of each frame.

7. The driving method of claim 6, wherein in the blanking time interval of each frame, the timing controller controlling the level signal of the first pin to switch between the high level and the low level comprises: the timing controller switching the level signal of the first pin between the high level and the low level under a control of a frame start signal of each frame.

8. The driving method of claim 6, wherein the power management chip configured to invert the voltage of the first shared discharge rod and the voltage of the second shared discharge rod under the control of the level signal of the first pin in the blanking time interval of each frame comprises: in the blanking time interval of each frame, when the level signal of the first pin is at the high level, the power management chip outputs a positive voltage to the first shared discharge rod, and the power management chip outputs a negative voltage to the second shared discharge rod; when the level signal of the first pin is at the low level, the power management chip outputs the negative voltage to the first shared discharge rod, and the power management chip outputs the positive voltage to the second shared discharge rod.

9. The driving method of claim 6, wherein the power management chip configured to invert the voltage of the first shared discharge rod and the voltage of the second shared discharge rod under the control of the level signal of the first pin in the blanking time interval of each frame comprises: in the blanking time interval of each frame, when the level signal of the first pin is at the high level, the power management chip outputs a negative voltage to the first shared discharge rod, and the power management chip outputs a positive voltage to the second shared discharge rod; when the level signal of the first pin is at the low level, the power management chip outputs the positive voltage to the first shared discharge rod, and the power management chip outputs the negative voltage to the second shared discharge rod.

10. The driving method of claim 6, wherein the timing controller comprises: a controller;a register, wherein the controller is electrically connected to the register, and the register is electrically connected to the first pin.

11. The driving method of claim 10, wherein the timing controller further comprises: a pulse signal generator electrically connected to the controller.

12. The driving method of claim 11, wherein the power management chip further comprises: a decoder, wherein an input terminal of the decoder is electrically connected to the second pin;a voltage conversion circuit, wherein the voltage conversion circuit comprises a first signal control terminal, a power supply access terminal, a first voltage output terminal, and a second voltage output terminal, the first signal control terminal is electrically connected to an output terminal of the decoder, the first voltage output terminal is electrically connected to the first shared discharge rod, and the second voltage output terminal is electrically connected to the second shared discharge rod.

13. The driving method of claim 12, wherein the decoder comprises: a second signal control terminal electrically connected to the pulse signal generator;wherein the decoder is configured to decode the level signal of the first pin under a signal control of the second signal control terminal and then transmits the level signal of the first pin to the first signal control terminal.

14. A display panel, wherein the display panel comprises a plurality of sub-pixels arranged in an array and a driving circuit, wherein the driving circuit comprises: a timing controller comprising a first pin;a power management chip comprising a second pin;a first shared discharge rod, wherein the power management chip is electrically connected to the first shared discharge rod;a second shared discharge rod, wherein the power management chip is electrically connected to the second shared discharge rod;wherein the first pin is electrically connected to the second pin, the power management chip is configured to output voltages with opposite polarities to the first shared discharge rod and the second shared discharge rod at the same time, the power management chip is used to invert a voltage of the first shared discharge rod and a voltage of the second shared discharge rod under a control of a level signal of the first pin in a blanking time interval of each frame;wherein the first shared discharge rod of the driving circuit is electrically connected to the sub-pixels of a first column, and the second shared discharge rod of the driving circuit is electrically connected to the sub-pixels of a second column.

15. The display panel of claim 14, wherein the timing controller comprises: a controller;a register, wherein the controller is electrically connected to the register, and the register is electrically connected to the first pin.

16. The display panel of claim 15, wherein the timing controller further comprises: a pulse signal generator electrically connected to the controller.

17. The display panel of claim 16, wherein the power management chip further comprises: a decoder, wherein an input terminal of the decoder is electrically connected to the second pin;a voltage conversion circuit, wherein the voltage conversion circuit comprises a first signal control terminal, a power supply access terminal, a first voltage output terminal, and a second voltage output terminal, the first signal control terminal is electrically connected to an output terminal of the decoder, the first voltage output terminal is electrically connected to the first shared discharge rod, and the second voltage output terminal is electrically connected to the second shared discharge rod.

18. The display panel of claim 17, wherein the decoder comprises: a second signal control terminal electrically connected to the pulse signal generator;wherein the decoder is configured to decode the level signal of the first pin under a signal control of the second signal control terminal and then transmits the level signal of the first pin to the first signal control terminal.