Patent Application
20240363087
This application claims priority under 35 U.S.C. § 119 (a) to Chinese Patent Application No. 202310463117.2, filed Apr. 26, 2023, the entire disclosure of which is incorporated herein by reference.
This disclosure relates to the technical field of a driving circuit for a display panel, in particular to a driving circuit for a display panel, a display device, and a driving method.
Compared with the traditional Cathode Ray Tube (CRT) and plasma television, the Liquid Crystal Display (LCD) television has advantages of power saving, low radiation, small size, light weight, high resolution, etc., which is the mainstream television at present. A driving circuit for an LCD display panel includes multiple pixels, and common voltage lines provide common voltages VCOM for pixel capacitors (Clc) and storage capacitors (Cs) of the pixels, thereby providing reference voltages for a substrate of the liquid crystal display, and data lines provide gray-scale voltages VDATA for the pixels. When the pixel emits light, by controlling a voltage value of the gray-scale voltage VDATA, that is, controlling a voltage difference between the gray-scale voltage VDATA and the common voltage VCOM, the deflection angle of the liquid crystal is controlled, and the luminance of the pixel is further controlled.
The common voltage lines in the driving circuit for the display panel are all connected with each other. In an ideal situation, the VCOM voltages in the driving circuit for the display panel should be the same everywhere. However, because the common voltage line has its own impedance, the farther away from a common voltage source, the greater the voltage attenuation. Therefore, under the same gray-scale voltage VDATA, different brightness will be displayed at different positions of the driving circuit for the display panel, and the user experience is poor.
A first aspect of the disclosure provides a driving circuit for a display panel. The display panel includes a common electrode. The driving circuit includes a common voltage feedback line and N common voltage detection units. The N common voltage detection units are electrically connected to N common voltage collection points of the common electrode in one-to-one correspondence, where the N common voltage collection points are N position points sequentially arranged along a power supply access end of the common electrode to a remote power supply end, and N>1. Each common voltage detection unit includes a switch module and a logic circuit. The switch module includes a first connection end, a second connection end, and a control end, where the first connection end is electrically connected to a common voltage collection point corresponding to the common voltage detection unit, and the second connection end is electrically connected to the common voltage feedback line. The logic circuit is electrically connected to the control end of the switch module. The N logic circuits respectively included in the N common voltage detection units sequentially output control signals to corresponding switch modules, and control N switch modules respectively included in the N common voltage detection units to sequentially turn on, to make the N common voltage collection points sequentially feed back common voltages to the common voltage feedback line through the turned-on switch modules, to sequentially output N common voltages corresponding to the N common voltage collection points through the common voltage feedback line.
A second aspect of the disclosure further provides a display device. The display device includes a housing, a power supply module, a display panel, and the driving circuit of the above. The driving circuit is electrically connected to the display panel and the power supply module, the power supply module is used to provide a working power supply for the driving circuit, the driving circuit is used to drive the display panel to display, and the housing is used to fix the power supply module, the display panel, and the driving circuit.
A third aspect of the disclosure further provides a driving method. The driving method is applied to the driving circuit for the display panel of the above. The display panel includes a common electrode and M rows of sub-pixel units, and the driving method includes: obtaining the N common voltages corresponding to the N common voltage collection points, where the N common voltage collection points are the N position points sequentially arranged along the power supply access end to the remote power supply end of the common electrode, and 1<N≤M; determining a common voltage corresponding to each row of sub-pixel units according to the N common voltages corresponding to the N common voltage collection points; determining a compensation gray-scale value of each sub-pixel unit according to the common voltage corresponding to each row of sub-pixel units; and compensating gray-scale data of a frame to-be-displayed according to the compensation gray-scale value of each sub-pixel unit, and outputting the compensated gray-scale data to the display panel to drive the display panel to display.
A clear and complete description of technical solutions of embodiments of the disclosure will be given below in conjunction with accompanying drawings in the embodiments of the disclosure, and it will be apparent that the described embodiments are only part of rather than all of the embodiments of the disclosure. Based on the embodiments in the disclosure, all other embodiments obtained without creative effort by those of ordinary skill in the art fall within the scope of protection of the disclosure.
In the description of the disclosure, it should be noted that terms “first”, “second”, and the like are used for descriptive purposes only and are not understood to indicate or imply relative importance.
Referring to
The driving circuit 100 includes a common voltage feedback line 12 and N common voltage detection units 11. The N common voltage detection units 11 are electrically connected to N common voltage collection points 2011 of the common electrode in one-to-one correspondence. The N common voltage collection points 2011 are N position points sequentially arranged along a power supply access end 2101 of the common electrode to a remote power supply end, where N>1. The remote power supply end refers to an end of the common electrode away from the power supply access end 2101. For example, as shown in
Specifically, each common voltage detection unit 11 includes a logic circuit 111 and a switch module 112.
The switch module 112 includes a first connection end, a second connection end, and a control end, the first connection end of the switch module 112 is electrically connected to a common voltage collection point 2011 corresponding to the common voltage detection unit 11, and the second connection end of the switch module 112 is electrically connected to the common voltage feedback line 12.
The logic circuit 111 is electrically connected to the control end of the switch module 112.
In operation, the N logic circuits 111 respectively included in the N common voltage detection units 11 sequentially output control signals to corresponding switch modules 112 to control the N switch modules 112 respectively included in the N common voltage detection units 11 to sequentially turn on, to make the N common voltage collection points 2011 sequentially feed back common voltages to the common voltage feedback line 12 through the turned-on switch modules 112, to sequentially output N common voltages corresponding to the N common voltage collection points 2011 through the common voltage feedback line 12.
By arranging the N logic circuits 111, the N switch modules 112, and the common voltage feedback line 12 electrically connected to all the N switch modules 112 and sequentially outputting the control signals to the corresponding switch modules 112 through the N logic circuits 111, the driving circuit 100 provided in the disclosure can control the N switch modules 112 to sequentially turn on, so that the N common voltage collection points 2011 sequentially feed back the common voltages to the common voltage feedback line 12 through the turned-on switch modules 112. As such, the common voltages at the N position points sequentially arranged along the power supply access end 2101 of the common electrode to the remote power supply end in the display panel 200 can be sequentially output through the common voltage feedback line 12, so that according to the common voltages at the N position points, gray-scale data of a frame to-be-displayed can be compensated or the common voltage can be accurately compensated, and uneven display brightness of the display panel 200 caused by attenuation of the common voltage when transmitted in the common electrode can be solved.
Further, the display panel 200 includes M×L sub-pixel units P arranged in M rows and L columns. As illustrated in
Further, the driving circuit 100 also includes a timing controller (TCON) 13 electrically connected to the common voltage feedback line 12 and the display panel 200 respectively. The timing controller 13 is used to obtain the N common voltages corresponding to the N common voltage collection points 2011 output from the common voltage feedback line 12, compensate gray-scale data of a frame to-be-displayed according to the N common voltages corresponding to the N common voltage collection points 2011, and output the compensated gray-scale data to the display panel 200 to drive the display panel 200 for display. As such, gray-scale loss caused by attenuation of the common voltage in the display panel 200 can be compensated and uneven display brightness of the display panel 200 can be solved.
In the driving circuit 100 provided in the disclosure, the timing controller 13 does not need to provide a signal input port for each common voltage collection point 2011, and the common voltages at the N common voltage collection points 2011 can be collected through one common voltage feedback line 12, so that ports of the timing controller 13 can be saved.
Optionally, the driving circuit 100 also includes an Analog-to-Digital Converter (ADC) 14 electrically connected between the timing controller 13 and the common voltage feedback line 12. The analog-to-digital converter 14 is used to convert the N common voltages sequentially output from the common voltage feedback line 12 into digital signals and then output them to the timing controller 13. In addition, in embodiments of the disclosure, the common voltages output from the common voltage feedback line 12 to the analog-to-digital converter 14 are serial signals. When the analog-to-digital converter 14 performs analog-to-digital conversion on the N common voltages, the analog-to-digital converter 14 can also convert the serial signals into parallel signals and then output them to the timing controller 13. In other embodiments the analog-to-digital converter 14 may also be integrated in the timing controller 13.
Optionally, the driving circuit 100 further includes multiple source drivers 16 electrically connected between the timing controller 13 and the display panel 200. The timing controller 13 outputs gray-scale data of frames to-be-displayed to the display panel 200 through the multiple source drivers 16.
Further, referring to
The first end of the energy storage module C is electrically connected to the second connection end of the trigger module T2 and the control end of the control signal output module T3 respectively, and the second end of the energy storage module C is electrically connected to the second connection end of the control signal output module T3.
The first connection end of the trigger module T2 is electrically connected to the control end of the trigger module T2, and the control end of the trigger module T2 is used to receive a trigger signal K1.
The first connection end of the control signal output module T3 is electrically connected to the timing controller 13, the first connection end of the control signal output module T3 is used to receive a clock signal CLK2 provided by the timing controller 13, the second connection end of the control signal output module T3 is electrically connected to the control end of the switch module 112 corresponding to its logic circuit 111, and the second connection end of the control signal output module T3 is used to output the corresponding control signal to the control end of the switch module 112 corresponding to its logic circuit 111.
The trigger module T2 is turned on in response to the trigger signal K1, to charge the energy storage module C, so that the potential of the control end of the control signal output module T3 changes to a first level. The control signal output module T3 is used to output the control signal to the corresponding switch module 112 through its second connection end when the potential of its control end and the clock signal CLK2 are both at the first level. The trigger signal Kl received by a first connection end of a trigger module T2 in a first logic circuit 111 is a feedback start signal CLK1 output by the timing controller 13, and a trigger signal K1 received by a first connection end of a trigger module T2 in a y-th logic circuit 111 of the N logic circuits 111 is a control signal G(y−1) output by a (y−1)-th logic circuit 111, where N≥y≥2. As shown in
Optionally, the driving circuit 100 further includes a Level Shifter (LS) 15 electrically connected between the logic circuits 111 and the timing controller 13, and the level shifter 15 is used for level shifting of the feedback start signal CLK1 and the clock signal CLK2 output by the timing controller 13, to improve the driving capability of the feedback start signal CLK1 and the clock signal CLK2.
Further as shown in
The first reset module T4 includes a first connection end, a second connection end, and a control end. The first connection end of the first reset module T4 is electrically connected to a control end of a control signal output module T3 in the (y−1)-th logic circuit 111. The second connection end of the first reset module T4 is used to receive a second level VSS. The control end of the first reset module T4 is electrically connected to a second connection end of a control signal output module T3 in the y-th logic circuit 111. The first reset module T4 is turned on when receiving a control signal G (y) output by the y-th logic circuit 111, to reset a potential of the control end of the control signal output module T3 in the (y−1)-th logic circuit 111 to the second level VSS, to turn off the control signal output module T3 in the (y−1)-th logic circuit 111.
The second reset module T5 includes a first connection end, a second connection end, and a control end. The first connection end of the second reset module T5 is electrically connected to the second connection end of the control signal output module T3 in the (y−1)-th logic circuit 111. The second connection end of the second reset module T5 is used to receive the second level VSS. The control end of the second reset module T5 is electrically connected to the second connection end of the control signal output module T3 in the y-th logic circuit 111. The second reset module T5 is turned on when receiving the control signal G (y) output by the y-th logic circuit 111, to reset a potential of the second connection end of the control signal output module T3 in the (y−1)-th logic circuit 111 to the second level VSS, so that the (y−1)-th logic circuit 111 stops outputting the control signal G(y−1).
Further, the y-th logic circuit 111 may adopt the circuit configuration shown in
Thus, arranging the first reset module T4 and the second reset module T5 in each logic circuit 111 can ensure that the N logic circuits 111 output only one control signal at any time to control one switch module 112 to be turned on, so that the common voltage feedback line 12 only feeds back the common voltage of one common voltage collection point 2011 to the timing controller 13 at any time, and the sampling accuracy can be improved.
The working principle of each common voltage detection unit 11 will be explained with reference to
The working process of the first logic circuit 111 is as follows. The trigger module T2 is turned on in response to the feedback start signal CLK1, to charge the energy storage module C, to pull up the potential of the control end (i.e., the Q node) of the control signal output module T3 to the first level, so that the control signal output module T3 is turned on. When the feedback start signal CLK1 ends, the energy storage module C can continuously discharge with the charging charge, so that the control signal output module T3 can continuously conduct. When a first pulse of the clock signal CLK2 arrives, the first connection end of the control signal output module T3 is at the first level, thereby outputting the first pulse of the clock signal CLK2 through the second connection end, i.e., outputting the control signal G1, thereby controlling the switch module 112 corresponding to the logic circuit 111 to be turned on, so that the first common voltage collection point 2011 feeds back the common voltage to the timing controller 13 through the turned-on switch module 112 and the common voltage feedback line 12. Thereafter, the first reset module T4 is turned on upon receiving the control signal G2 output from the second logic circuit 111 to reset the potential of the control end of the control signal output module T3 to the second level VSS, so that the control signal output module T3 is turned off. The second reset module T5 is turned on upon receiving the control signal G2 output by the second logic circuit 111, to reset the potential of the second connection end of the control signal output module T3 to the second level VSS, so that the logic circuit 111 stops outputting the control signal G1, thereby controlling the switch module 112 corresponding to the logic circuit 111 to be turned off, so that the first common voltage collection point 2011 stops feeding back the common voltage to the timing controller 13. At the same time, the energy storage module C can release residual charges through the conductive first reset module T4 and the second reset module T5.
The working process of the second to third logic circuits 111 is similar to that of the first logic circuit 111, except that the trigger module T2 in the second logic circuit 111 is turned on in response to the control signal G1 output from the first logic circuit 111, to charge the energy storage module C and the trigger module T2 in the third logic circuit 111 is turned on in response to the control signal G2 output from the second logic circuit 111, to charge the energy storage module C.
Thus, the N common voltage collection points can sequentially output the common voltages through the common voltage feedback line 12.
As an example, the switch module 112, the trigger module T2, the control signal output module T3, the first reset module T4, and the second reset module T5 may all employ Thin Film Transistors (TFTs). For example, an amorphous silicon thin film transistor (a-Si TFT), a low temperature polysilicon thin film transistor (LTPS TFT), or an oxide semiconductor thin film transistor (Oxide TFT) may be employed. In embodiments of the disclosure, the switch module 112, the trigger module T2, the control signal output module T3, the first reset module T4, and the second reset module T5 are all high-level conduction transistors, that is, the first level is high and the second level VSS is low. In other embodiments, the switch module 112, the trigger module T2, the control signal output module T3, the first reset module T4, and the second reset module T5 may also employ low-level conduction transistors, which are not limited herein.
In embodiments of the disclosure, a frequency at which the driving circuit 100 collects the common voltage is determined by the feedback start signal CLK1 and the clock signal CLK2. For example, the frequency at which the timing controller 13 outputs the feedback start signal CLK1 may be once per frame, or once per second, etc. The frequency of the clock signal CLK2 may be adjusted accordingly according to the frequency of the feedback start signal CLK1 and the number of the common voltage collection points 2011.
It can be understood that, the farther the distance between the sub-pixel unit P in the display panel 200 and the power supply access end 2101 of the common electrode, the greater the attenuation degree of the common voltage received by the sub-pixel unit P, and the attenuation degrees of the common voltages received by the sub-pixel units P in the same row are approximately the same. Therefore, the greater the number of the N common voltage collection points 2011, the more evenly distributed in the direction from the power supply access end 2101 of the common electrode to the remote power supply end, the higher the accuracy of the collected common voltage, and the higher the accuracy of compensation of the gray-scale data of the frame to-be-displayed. In embodiments of the disclosure, two adjacent common voltage collection points 2011 are separated by at least one row of sub-pixel units P. The N common voltage collection points 2011 are distributed in the display panel 200 at equal intervals, that is, distances between any two adjacent common voltage collection points 2011 in the direction from the power supply access end 2101 of the common electrode to the remote power supply end are approximately equal. Thus, the collected N common voltages are more representative, which is beneficial to improving the accuracy of voltage compensation, thereby further improving the brightness uniformity of the display panel 200. It should be noted that, in embodiments of the disclosure, N=3 is as an example, which is not regarded as limiting to the value of N. In other embodiments, N can be 2, 4, 8, 10, etc. Exemplarily, in one embodiment, M=1080, N=10, that is, the display panel 200 includes 1080 rows of sub-pixel units P and 1080 common voltage lines 201 electrically connected to the 1080 rows of sub-pixel units P in one-to-one correspondence, and 10 common voltage collection points 2011 evenly distributed are disposed on the 1080 common voltage lines 201.
Further, the timing controller 13 is used to determine the common voltage corresponding to each row of sub-pixel units P according to the N common voltages corresponding to the N common voltage collection points 2011, determine the compensation gray-scale value of each sub-pixel unit P according to the common voltage corresponding to each row of sub-pixel units P, and compensate the gray-scale data of the frame to-be-displayed according to the compensation gray-scale value of each sub-pixel unit P to obtain the compensated gray-scale data.
As an example, the timing controller 13 may determine the common voltage corresponding to each row of sub-pixel units P by using a linear interpolation method according to the N common voltages corresponding to the N common voltage collection points and the distribution of the N common voltage collection points 2011. For example, one common voltage collection point 2011 is disposed on the first and (x×108)-th common voltage lines 201, where 10≥x≥1. Then, the common voltages corresponding to the sub-pixel units P in the first row and the (x×108)-th row are the common voltage output from the first and (x×108)-th common voltage line 201, and the common voltages corresponding to the sub-pixel units P in other rows than the first row and the (x×108)-th row can be determined with linear interpolation based on the common voltages output from the first and (x×108)-th common voltage lines 201.
Further, in one embodiment, the timing controller 13 is used to determine the compensation gray-scale value of each sub-pixel unit P according to a first preset compensation gray-scale mapping table and a voltage difference between the common voltage corresponding to each row of sub-pixel units P and a target common voltage. The first preset compensation gray-scale mapping table records a mapping relationship between multiple voltage differences and multiple compensation gray-scale values. The first preset compensation gray-scale mapping table can be obtained experimentally before the display panel 200 leaves the factory. Exemplarily, the target common voltage is 6V. As shown in
In another embodiment, the timing controller 13 is used to determine the compensation gray-scale value of each sub-pixel unit P according to a second preset compensation gray-scale mapping table, the voltage difference between the common voltage corresponding to each row of sub-pixel units P and the target common voltage, and the gray-scale data of the frame to-be-displayed. The gray-scale data of the frame to-be-displayed includes a target gray-scale value corresponding to each sub-pixel unit P. The second preset compensation gray-scale mapping table records a mapping relationship between multiple voltage differences and multiple compensation gray-scale values under each target gray-scale value. The second preset compensation gray-scale mapping table can be obtained experimentally before the display panel 200 leaves the factory. Exemplarily, the target common voltage is 6V. As shown in
Referring again to
Referring to
At block 610, the N common voltages corresponding to the N common voltage collection points 2011 are obtained. The N common voltage collection points 2011 are the N position points sequentially arranged along the power supply access end 2101 of the common electrode to the remote power supply end, where 1<N≤M.
At block 620, a common voltage corresponding to each row of sub-pixel units P is determined according to the N common voltages corresponding to the N common voltage collection points 2011.
At block 630, a compensation gray-scale value of each sub-pixel unit P is determined according to the common voltage corresponding to each row of sub-pixel units P.
At block 640, gray-scale data of a frame to-be-displayed is compensated according to the compensation gray-scale value of each sub-pixel unit P, and the compensated gray-scale data is output to the display panel 200 to drive the display panel 200 to display.
Specifically, the compensation gray-scale value of each sub-pixel unit P is added to the target gray-scale value to obtain the compensated gray-scale data.
Further, the driving circuit 100 further includes the common voltage feedback line 12 and the N common voltage detection units 11 connected to the N common voltage collection points 2011 of the common electrode in one-to-one correspondence. Each common voltage detection unit 11 includes the switch module 112 and the logic circuit 111. The switch module 112 includes the first connection end, the second connection end, and the control end. The first connection end is electrically connected to the common voltage collection point 2011 corresponding to the common voltage detection unit 11, and the second connection end is electrically connected to the common voltage feedback line 12. The logic circuit 111 is electrically connected to the control end of the switch module 112.
In this embodiment, before performing the operation at block 610, the driving method further includes the following.
At block 601, the control signals are sequentially output to corresponding switch modules 112 through the N logic circuits 111 and the N switch modules 112 respectively included in the N common voltage detection units 11 are controlled to sequentially turn on, to make the N common voltage collection points 2011 sequentially feed back the common voltages to the common voltage feedback line 12 through the turned-on switch modules 112, to sequentially output the N common voltages corresponding to the N common voltage collection points 2011 through the common voltage feedback line 12.
As described above, the timing controller 13 outputs the feedback start signal CLK1 to the first logic circuit 111 and the clock signal CLK2 to each logic circuit 111, and can control the N logic circuits 111 to sequentially output the control signals to the corresponding switch modules 112. The working principle of the logic circuits 111 has been described in detail above and will not be described herein.
Further, the operation at block 610 includes: obtaining the N common voltages corresponding to the N common voltage collection points 2011 sequentially output from the common voltage feedback line 12.
Further, in one embodiment, the operation at block 630 includes: determining the compensation gray-scale value of each sub-pixel unit P according to a first preset compensation gray-scale mapping table and a voltage difference between the common voltage corresponding to each row of sub-pixel units P and a target common voltage. The first preset compensation gray-scale mapping table records a mapping relationship between multiple voltage differences and multiple compensation gray-scale values.
In another embodiment, the operation at block 630 includes: determining the compensation gray-scale value of each sub-pixel unit P according to a second preset compensation gray-scale mapping table, the voltage difference between the common voltage corresponding to each row of sub-pixel units P and the target common voltage, and the gray-scale data of the frame to-be-displayed. The gray-scale data of the frame to-be-displayed includes a target gray-scale value corresponding to each sub-pixel unit P. The second preset compensation gray-scale mapping table records a mapping relationship between multiple voltage differences and multiple compensation gray-scale values under each target gray-scale value.
It should be noted that all operations in the driving method described in any of the above embodiments may be executed by the timing controller 13.
For the driving method provided in the disclosure, the N common voltages corresponding to the N common voltage collection points are obtained, the common voltage corresponding to each row of sub-pixel units is determined according to the N common voltages corresponding to the N common voltage collection points, the compensation gray-scale value of each sub-pixel unit is determined according to the common voltage corresponding to each row of sub-pixel units, and the gray-scale data of the frame to-be-displayed is compensated according to the compensation gray-scale value of each sub-pixel unit, and the compensated gray-scale data is output to the display panel to drive the display panel to display. As such, the gray-scale data of the frame to-be-displayed can be accurately compensated according to the common voltages at the N position points, and uneven display brightness of the display panel 200 caused by attenuation of the common voltage when transmitted in the common electrode can be solved.
In conclusion, the disclosure provides a driving circuit for a display panel. The display panel includes a common electrode. The driving circuit includes a common voltage feedback line and N common voltage detection units. The N common voltage detection units are electrically connected to N common voltage collection points of the common electrode in one-to-one correspondence, where the N common voltage collection points are N position points sequentially arranged along a power supply access end of the common electrode to a remote power supply end, and N>1. Each common voltage detection unit includes a switch module and a logic circuit. The switch module includes a first connection end, a second connection end, and a control end, where the first connection end is electrically connected to a common voltage collection point corresponding to the common voltage detection unit, and the second connection end is electrically connected to the common voltage feedback line. The logic circuit is electrically connected to the control end of the switch module. The N logic circuits respectively included in the N common voltage detection units sequentially output control signals to corresponding switch modules, and control N switch modules respectively included in the N common voltage detection units to sequentially turn on, to make the N common voltage collection points sequentially feed back common voltages to the common voltage feedback line through the turned-on switch modules, to sequentially output N common voltages corresponding to the N common voltage collection points through the common voltage feedback line.
By arranging the N logic circuits, the N switch modules, and the common voltage feedback line electrically connected to all the N switch modules and sequentially outputting the control signals to the corresponding switch modules through the N logic circuits, the driving circuit provided in the disclosure can control the N switch modules to sequentially turn on, so that the N common voltage collection points sequentially feed back the common voltages to the common voltage feedback line through the turned-on switch modules. As such, the common voltages at the N position points sequentially arranged along the power supply access end of the common electrode to the remote power supply end in the display panel can be sequentially output through the common voltage feedback line, so that according to the common voltages at the N position points, gray-scale data of a frame to-be-displayed can be compensated or the common voltage can be accurately compensated, and uneven display brightness of the display panel caused by attenuation of the common voltage when transmitted in the common electrode can be solved.
Optionally, the driving circuit further includes a timing controller electrically connected to the common voltage feedback line and the display panel. The timing controller is used to obtain the N common voltages corresponding to the N common voltage collection points output from the common voltage feedback line, compensate gray-scale data of a frame to-be-displayed according to the N common voltages corresponding to the N common voltage collection points, and output the compensated gray-scale data to the display panel to drive the display panel to display.
Optionally, the N logic circuits are cascaded, and each logic circuit includes an energy storage module, a trigger module, and a control signal output module. The trigger module and the control signal output module each include a first connection end, a second connection end, and a control end, and the energy storage module includes a first end and a second end. The first end of the energy storage module is electrically connected to the second connection end of the trigger module and the control end of the control signal output module respectively, and the second end of the energy storage module is electrically connected to the second connection end of the control signal output module. The first connection end of the trigger module is electrically connected to the control end of the trigger module, and the control end of the trigger module is used to receive a trigger signal. The first connection end of the control signal output module is electrically connected to the timing controller, the first connection end of the control signal output module is used to receive a clock signal provided by the timing controller, and the second connection end of the control signal output module is electrically connected to the control end of the switch module corresponding to the logic circuit. The trigger module is turned on in response to the trigger signal, to charge the energy storage module, to change a potential of the control end of the control signal output module to a first level, the control signal output module is used to output the control signal to the corresponding switch module through the second connection end when the potential of the control end and the clock signal are both at the first level, a trigger signal received by a first connection end of a trigger module in a first logic circuit is a feedback start signal output by the timing controller, a trigger signal received by a first connection end of a trigger module in a y-th logic circuit of the N logic circuits is a control signal output by a (y−1)-th logic circuit, and N≥y≥2.
Optionally, the (y−1)-th logic circuit of the N logic circuits further includes a first reset module and a second reset module. The first reset module includes a first connection end, a second connection end, and a control end, where the first connection end of the first reset module is electrically connected to a control end of a control signal output module in the (y−1)-th logic circuit, the second connection end of the first reset module is used to receive a second level, and the control end of the first reset module is electrically connected to a second connection end of a control signal output module in the y-th logic circuit, and the first reset module is turned on when receiving a control signal output by the y-th logic circuit, to reset a potential of the control end of the control signal output module in the (y−1)-th logic circuit to the second level, to turn off the control signal output module in the (y−1)-th logic circuit. The second reset module includes a first connection end, a second connection end, and a control end, where the first connection end of the second reset module is electrically connected to a second connection end of the control signal output module in the (y−1)-th logic circuit, the second connection end of the second reset module is used to receive the second level, and the control end of the second reset module is electrically connected to the second connection end of the control signal output module in the y-th logic circuit, and the second reset module is turned on when receiving the control signal output by the y-th logic circuit, to reset a potential of the second connection end of the control signal output module in the (y−1)-th logic circuit to the second level, to stop the (y−1)-th logic circuit from outputting the control signal.
Optionally, the display panel further includes M rows of sub-pixel units, M>N, and two adjacent common voltage collection points are spaced apart by at least one row of sub-pixel units. The timing controller is used to determine a common voltage corresponding to each row of sub-pixel units according to the N common voltages corresponding to the N common voltage collection points, determine a compensation gray-scale value of each sub-pixel unit according to the common voltage corresponding to each row of sub-pixel units, and compensate the gray-scale data of the frame to-be-displayed according to the compensation gray-scale value of each sub-pixel unit, to obtain the compensated gray-scale data.
Optionally, the timing controller is used to determine the compensation gray-scale value of each sub-pixel unit according to a first preset compensation gray-scale mapping table and a voltage difference between the common voltage corresponding to each row of sub-pixel units and a target common voltage. The first preset compensation gray-scale mapping table records a mapping relationship between multiple voltage differences and multiple compensation gray-scale values.
Optionally, the timing controller is used to determine the compensation gray-scale value of each sub-pixel unit according to a second preset compensation gray-scale mapping table, a voltage difference between the common voltage corresponding to each row of sub-pixel units and a target common voltage, and the gray-scale data of the frame to-be-displayed, and the gray-scale data of the frame to-be-displayed includes a target gray-scale value corresponding to each sub-pixel unit. The second preset compensation gray-scale mapping table records a mapping relationship between multiple voltage differences and multiple compensation gray-scale values under each target gray-scale value.
The disclosure further provides a display device. The display device includes a housing, a power supply module, a display panel, and the driving circuit of the above. The driving circuit is electrically connected to the display panel and the power supply module, the power supply module is used to provide a working power supply for the driving circuit, the driving circuit is used to drive the display panel to display, and the housing is used to fix the power supply module, the display panel, and the driving circuit.
The disclosure further provides a driving method. The driving method is applied to the driving circuit for the display panel of the above. The display panel includes a common electrode and M rows of sub-pixel units, and the driving method includes: obtaining the N common voltages corresponding to the N common voltage collection points, where the N common voltage collection points are the N position points sequentially arranged along the power supply access end to the remote power supply end of the common electrode, and 1<N≤M; determining a common voltage corresponding to each row of sub-pixel units according to the N common voltages corresponding to the N common voltage collection points; determining a compensation gray-scale value of each sub-pixel unit according to the common voltage corresponding to each row of sub-pixel units; and compensating gray-scale data of a frame to-be-displayed according to the compensation gray-scale value of each sub-pixel unit, and outputting the compensated gray-scale data to the display panel to drive the display panel to display.
Optionally, the driving circuit includes the common voltage feedback line and the N common voltage detection units electrically connected to the N common voltage collection points of the common electrode in one-to-one correspondence. Each common voltage detection unit includes the switch module and the logic circuit, the switch module includes the first connection end, the second connection end, and the control end, the first connection end is electrically connected to the common voltage collection point corresponding to the common voltage detection unit, the second connection end is electrically connected to the common voltage feedback line, and the logic circuit is electrically connected to the control end of the switch module. Before obtaining the N common voltages corresponding to the N common voltage collection points, the driving method further includes: outputting the control signals to the corresponding switch modules sequentially through the N logic circuits, and controlling the N switch modules included in the N common voltage detection units to sequentially turn on, to make the N common voltage collection points sequentially feed back the common voltages to the common voltage feedback line through the turned-on switch modules, to sequentially output the N common voltages corresponding to the N common voltage collection points through the common voltage feedback line. Obtaining the N common voltages corresponding to the N common voltage collection points includes: obtaining the N common voltages corresponding to the N common voltage collection points sequentially output from the common voltage feedback line.
Optionally, determining the compensation gray-scale value of each sub-pixel unit according to the common voltage corresponding to each row of sub-pixel units includes: determining the compensation gray-scale value of each sub-pixel unit according to a first preset compensation gray-scale mapping table and a voltage difference between the common voltage corresponding to each row of sub-pixel units and a target common voltage, where the first preset compensation gray-scale mapping table records a mapping relationship between multiple voltage differences and multiple compensation gray-scale values.
Optionally, determining the compensation gray-scale value of each sub-pixel unit according to the common voltage corresponding to each row of sub-pixel units includes: determining the compensation gray-scale value of each sub-pixel unit according to a second preset compensation gray-scale mapping table, a voltage difference between the common voltage corresponding to each row of sub-pixel units and a target common voltage, and the gray-scale data of the frame to-be-displayed, and the gray-scale data of the frame to-be-displayed includes a target gray-scale value corresponding to each sub-pixel unit, where the second preset compensation gray-scale mapping table records a mapping relationship between multiple voltage differences and multiple compensation gray-scale values under each target gray-scale value.
Although embodiments of the disclosure have been shown and described, it will be understood by those of ordinary skill in the art that various changes, modifications, substitutions, and modifications may be made to these embodiments without departing from the principles and purposes of the disclosure, and the scope of the disclosure is defined by the claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202310463117.2 | Apr 2023 | CN | national |
