Patent Grant
7782291
The present invention relates to a driving circuit of a liquid crystal display (LCD), whereby accurate control of delay time periods of voltages output by the driving circuit can be attained.
An LCD has the advantages of portability, low power consumption, and low radiation, and has been widely used in various portable information products such as notebooks, personal digital assistants (PDAs), video cameras and the like. Furthermore, the LCD is considered by many to have the potential to completely replace CRT (cathode ray tube) monitors and televisions.
A typical LCD includes an LCD panel, a timing controller, a gate driver, and a data driver. The LCD panel includes a plurality of thin film transistors (TFTs), and a plurality of pixels, each of which is driven by a TFT. The gate driver drives the TFT by two different voltages, namely VGH and VGL. The data driver provides a plurality of gray-scale voltages to the pixels via the activated TFTs.
In order to avoid the gate driver being latched up by the two different voltages VGH and VGL, a delay circuit is needed to delay the voltages VGH and VGL for different predetermined time periods.
As shown in
In each of the first delay circuits 210, the first transistor 212 is a PNP (positive-negative-positive) type transistor. A base electrode “b” of the first transistor 210 is connected to ground via the second resistor R2. The first capacitor C1 and the first resistor R1 are connected in parallel, between an emitter electrode “e” and the base electrode “b” of the first transistor 212. The emitter electrode “e” of the first transistor 212 receives a first voltage signal from a first input terminal 211. A collector electrode “c” of the first transistor 212 provides the first voltage signal to a first output terminal 213. The first voltage signal can be a voltage VGH, or a voltage VDD. One of the first delay circuits 210 is used to delay the voltage VGH a first predetermined time period T1, and then send the voltage VGH to a gate driver of the LCD. The other first delay circuit 210 is used to delay the voltage VDD a second predetermined time period T2, and then send the voltage VDD to a data driver of the LCD.
The second transistor 222 is an n-channel metal oxide semiconductor field effect transistor (N-MOSFET). A gate electrode “G” of the second transistor 220 is connected to ground via the fourth resistor R4. The second capacitor C2 and the third resistor R3 are connected in parallel, between a source electrode “S” and the gate electrode “G” of the second transistor 222. The source electrode “S” of the second transistor 222 receives a second voltage signal from a second input terminal 221. A drain electrode “D” of the second transistor 222 provides the second voltage signal to a second output terminal 223. The second voltage signal can be a voltage VGL. The second delay circuit 220 is used to delay the voltage VGL a third predetermined time period T3, and then send the voltage VGL to the gate driver of the LCD.
The first and second delay circuits 210, 220 are analog circuits. The parameters of the elements of the first and second delay circuits 210, 220, such as the first and third resistors R1, R3 and the first and second capacitors C1, C2, vary in different environmental temperatures. Therefore the delay time periods T1, T2 and T3 vary with differing environmental temperatures. Thus, the delay time periods T1, T2, T3 cannot be accurately controlled.
What is needed, therefore, is a driving circuit of an LCD that can overcome the above-described deficiencies.
In a preferred embodiment, a driving circuit of a liquid crystal display includes a delay circuit, a first transistor, a second transistor, a first bias resistor, and a second bias resistor. The first transistor includes a source electrode for receiving a first voltage signal, a drain electrode for providing the first voltage signal to a first circuit of the liquid crystal display, and a gate electrode. The second transistor includes an emitter electrode for receiving a second voltage signal, a collector electrode for providing the second voltage signal to a second circuit of the liquid crystal display, and a base electrode. The first bias resistor is connected between the gate electrode and the source electrode of the first transistor. The second bias resistor is connected between the base electrode and the emitter electrode of the second transistor. The delay circuit includes a first control pin connected to the gate electrode of the first transistor, and a second control pin connected to the base electrode of the second transistor. The delay circuit is configured for delaying the first voltage signal for a first predetermined time period and the second voltage signal for a second predetermined time period.
Other advantages and novel features will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.
The delay circuit 130 includes a timing controller 131, a state machine 133, a fourth transistor 134, a fifth transistor 135, and a sixth transistor 136. The fourth transistor 134 is an n-channel metal oxide semiconductor field effect transistor. The fifth and sixth transistors 135, 136 are p-channel metal oxide semiconductor field effect transistors. The delay circuit 130 is an integrated circuit that can be manufactured by incorporating the state machine 133, the fourth transistor 134, the fifth transistor 135 and the sixth transistor 136 in the timing controller 131 in a semiconductor manufacturing process.
The timing controller 131 includes an oscillator (not shown) for providing an oscillatory signal such as a square pulse signal to the state machine 133. The state machine 133 is a digital circuit, and includes a counter (not shown) for generating time delays, and three control terminals (not labeled).
The fourth transistor 134 includes a gate electrode “G”, a source electrode “S”, and a drain electrode “D”. The gate electrode “G” is connected to a first one of the control terminals of the state machine 133. The source electrode “S” is connected to a power supply VCC. The drain electrode “D” is defined as a first control pin 137 of the delay circuit 130.
The fifth transistor 135 includes a gate electrode “G”, a source electrode “S”, and a drain electrode “D”. The gate electrode “G” is connected to a second one of the control terminals of the state machine 133. The source electrode “S” is connected to ground. The drain electrode “D” is defined as a second control pin 138 of the delay circuit 130.
The sixth transistor 136 includes a gate electrode “G”, a source electrode “S”, and a drain electrode “D”. The gate electrode “G” is connected to a third one of the control terminals of the state machine 133. The source electrode “S” is connected to ground. The drain electrode “D” is defined as a third control pin 139 of the delay circuit 130.
The first transistor 140 includes a gate electrode “G”, a source electrode “S”, and a drain electrode “D”. The first bias resistor R1 is connected between the gate electrode “G” and the source electrode “S”. The gate electrode “G” is connected to the first control pin 137 of the delay circuit 130. The source electrode “S” receives a first voltage signal from a first input terminal 151. The drain electrode “D” provides the first voltage signal to a gate driver (not shown) of the LCD via a first output terminal 150. The first voltage signal can be a voltage VGL that is approximately equal to −5 volts.
The second transistor 160 includes a base electrode “b”, an emitter electrode “e”, and a collector electrode “c”. The second bias resistor R2 is connected between the base electrode “b” and the emitter electrode “e”. The base electrode “b” is connected to the second control pin 138 of the delay circuit 130. The emitter electrode “e” receives a second voltage signal from a second input terminal 171. The collector electrode “c” provides the second voltage signal to the gate driver of the LCD via a second output terminal 170. The second voltage signal can be a voltage VGH that is approximately equal to 15 volts.
The third transistor 180 includes a base electrode “b”, an emitter electrode “e”, and a collector electrode “c”. The third bias resistor R3 is connected between the base electrode “b” and the emitter electrode “e”. The base electrode “b” is connected to the third control pin 139 of the delay circuit 130. The emitter electrode “e” receives a third voltage signal from a third input terminal 191. The collector electrode “c” provides the third voltage signal to a data driver of the LCD via a third output terminal 190. The third voltage signal can be a voltage VDD that is approximately equal to 9 volts.
Operation of the driving circuit 100 is as follows. When the LCD is turned on, the state machine 133 activates the second transistor 160 via the fifth transistor 135, and keeps the second transistor 160 in an activated state for a first predetermined time period T1. The second output terminal 170 provides the voltage VGH to the gate driver of the LCD when the second transistor 160 is activated. Then the voltage VGH activates a plurality of TFTs (not shown) of the LCD, and electric charges stored in a plurality of pixel capacitors of the LCD are discharged through the activated TFTs.
After the discharging has finished, the state machine 133 activates the third transistor 180 via the sixth transistor 136, and keeps the third transistor 180 in an activated state for a second predetermined time period T2. The third output terminal 190 provides the voltage VDD to the data driver of the LCD when the third transistor 180 is activated. The data driver accordingly provides a plurality of gray-scale voltages to a plurality of pixels of the LCD via the activated TFTs.
Then the state machine 133 activates the first transistor 140 via the fourth transistor 134, and keeps the first transistor 140 in an activated state for a third predetermined time period T3. The first output terminal 150 provides the voltage VGL to the gate driver of the LCD when the first transistor 140 is activated. Then the voltage VGL turns off the TFTs of the LCD.
In summary, the state machine 133 is used to delay the voltage signals VGH, VDD, VGL for the different predetermined time periods T1, T2, T3. Because the state machine 133 is a digital circuit, the delay time periods T1, T2, T3 can be accurately controlled and are not influenced by environmental temperatures.
It is to be understood, however, that even though numerous characteristics and advantages of the present embodiments have been set out in the foregoing description, together with details of the structures and functions of the embodiments, the disclosure is illustrative only, and changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.
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