The present disclosure relates generally to electronic displays and, more particularly, to electronic displays with reduced or eliminated mura artifacts.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Electronic displays may be found in a variety of devices, such as computer monitors, televisions, instrument panels, mobile phones, and clocks. One type of electronic display is known as a micro light-emitting diode (uLED) display, which includes pixels of LEDs for displaying image data. The uLED display may include micro drivers that may utilize p-type metal-oxide-semiconductor (PMOS) drivers used to drive the LED devices. For example, PMOS drivers may be used as part of the micro drivers in order to conserve physical area of the uLED display by avoiding level shifters that may be otherwise involved. However, utilizing PMOS drivers as part of the micro drivers may lead to image artifacts (e.g., flicker) becoming present on the uLED display.
A summary of certain embodiments disclosed herein is set forth below. It should be understood that these aspects are presented merely to provide the reader with a brief summary of these certain embodiments and that these aspects are not intended to limit the scope of this disclosure. Indeed, this disclosure may encompass a variety of aspects that may not be set forth below.
Various embodiments of the present disclosure relate to methods and devices useful in compensating for VDD and VTH variations in a micro light-emitting diode (micro-LED) display. By way of example, an LED driver includes a first transistor having a first source coupled to an upper voltage rail (VDD), a first gate, and a first drain. The LED driver includes a second transistor having a second source coupled to the first drain of the first transistor, a second gate, and a second drain coupled to the LED. The second transistor is configured to receive the drive current signal from the first transistor and supply the drive current signal to the LED. The LED driver includes compensation circuitry configured to adjust the drive current signal such that the drive current signal is independent of the upper voltage rail (VDD) and a threshold voltage (VTH) of the first transistor or the second transistor.
Various refinements of the features noted above may exist in relation to various aspects of the present disclosure. Further features may also be incorporated in these various aspects as well. These refinements and additional features may exist individually or in any combination. For example, various features discussed below in relation to one or more of the illustrated embodiments may be incorporated into any of the above-described aspects of the present disclosure alone or in any combination. The brief summary presented above is intended only to familiarize the reader with certain aspects and contexts of embodiments of the present disclosure without limitation to the claimed subject matter.
Various aspects of this disclosure may be better understood upon reading the following detailed description and upon reference to the drawings in which:
One or more specific embodiments will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.
When introducing elements of various embodiments of the present disclosure, the articles “a,” “an,” and “the” are intended to mean that there are one or more of the elements. The terms “comprising,” “including,” and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements. Additionally, it should be understood that references to “one embodiment” or “an embodiment” of the present disclosure are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features.
Embodiments of the present disclosure relate to upper voltage rail VDD and threshold voltage VTH compensation circuitry that may be used to compensate for the VDD and VTH variations that may be due to, for example, IR drop (e.g., voltage drops across the resistance R of the power supply between supply pins and one or more components drawing a current I) associated the high voltage potential rail (e.g., “VDD”) in micro light-emitting diode (uLED) displays. In certain embodiments, the micro drivers including p-type metal-oxide-semiconductor (PMOS) devices may be set to operate over one or more phases of the drive currents (e.g., “ILED”) of the LED devices to compensate for the VDD and VTH variations, and may generate a drive current for the LED devices independent of VDD and VTH. In another embodiment, the micro drivers including n-type metal-oxide-semiconductor (NMOS) devices may be set to operate over one or more phases of the drive currents (e.g., “ILED”) to compensate for the lower voltage rail VSS and threshold voltage VTH variations, and may generate a drive current for the LED devices independent of VSS and VTH In this way, any possible occurrence of image artifacts becoming apparent on the uLED display due to VDD, VSS, and VTH signal variations may be reduced or substantially eliminated.
A general description of suitable electronic devices that may include a micro-LED (μ-LED) display and corresponding circuitry of this disclosure are provided. One example of a suitable electronic device 10 may include, among other things, processor(s) such as a central processing unit (CPU) and/or graphics processing unit (GPU) 12, storage device(s) 14, communication interface(s) 16, a μ-LED display 18, input structures 20, and an energy supply 22. The blocks shown in
The CPU/GPU 12 of the electronic device 10 may perform various data processing operations, including generating and/or processing image data for display on the display 18, in combination with the storage device(s) 14. For example, instructions that can be executed by the CPU/GPU 12 may be stored on the storage device(s) 14. The storage device(s) 14 thus may represent any suitable tangible, computer-readable media. The storage device(s) 14 may be volatile and/or non-volatile. By way of example, the storage device(s) 14 may include random-access memory, read-only memory, flash memory, a hard drive, and so forth.
The electronic device 10 may use the communication interface(s) 16 to communicate with various other electronic devices or components. The communication interface(s) 16 may include input/output (I/O) interfaces and/or network interfaces. Such network interfaces may include those for a personal area network (PAN) such as Bluetooth, a local area network (LAN) or wireless local area network (WLAN) such as Wi-Fi, and/or for a wide area network (WAN) such as a long-term evolution (LTE) cellular network.
Using pixels containing an arrangement μ-LEDs, the display 18 may display images generated by the CPU/GPU 12. The display 18 may include touchscreen functionality to allow users to interact with a user interface appearing on the display 18. Input structures 20 may also allow a user to interact with the electronic device 10. For instance, the input structures 20 may represent hardware buttons. The energy supply 22 may include any suitable source of energy for the electronic device. This may include a battery within the electronic device 10 and/or a power conversion device to accept alternating current (AC) power from a power outlet.
As may be appreciated, the electronic device 10 may take a number of different forms. As shown in
The electronic device 10 may also take the form of a slate 40. Depending on the size of the slate 40, the slate 40 may serve as a handheld device such as a mobile phone. The slate 40 includes an enclosure 42 through which several input structures 20 may protrude. The enclosure 42 also holds the display 18. The input structures 20 may allow a user to interact with a GUI of the slate 40. For example, the input structures 20 may enable a user to make a telephone call. A speaker 44 may output a received audio signal and a microphone 46 may capture the voice of the user. The slate 40 may also include a communication interface 16 to allow the slate 40 to connect via a wired connection to another electronic device.
A notebook computer 50 represents another form that the electronic device 10 may take. It should be appreciated that the electronic device 10 may also take the form of any other computer, including a desktop computer. The notebook computer 50 shown in
A block diagram of the architecture of the μ-LED display 18 appears in
As noted above, the video TCON 66 may generate the data clock signal (DATA_CLK). An emission timing controller (TCON) 72 may generate an emission clock signal (EM_CLK). Collectively, these may be referred to as Row Scan Control signals, as illustrated in
In particular, the display panel 60 includes column drivers (CDs) 74, row drivers (RDs) 76, and micro-drivers (μDs or uDs) 78. Each uD 78 drives a number of pixels 80 having μ-LEDs as subpixels 82. Each pixel 80 includes at least one red μ-LED, at least one green μ-LED, and at least one blue μ-LED to represent the image data 64 in RGB format. Although the uDs 78 of
A power supply 84 may provide a reference voltage (VREF) 86 to drive the μ-LEDs, a digital power signal 88, and an analog power signal 90. In some cases, the power supply 84 may provide more than one reference voltage (VREF) 86 signal. Namely, subpixels 82 of different colors may be driven using different reference voltages. As such, the power supply 84 may provide more than one reference voltage (VREF) 86. Additionally or alternatively, other circuitry on the display panel 60 may step the reference voltage (VREF) 86 up or down to obtain different reference voltages to drive different colors of μ-LED.
To allow the μDs 78 to drive the μ-LED subpixels 82 of the pixels 80, the column drivers (CDs) 74 and the row drivers (RDs) 76 may operate in concert. Each column driver (CD) 74 may drive the respective image data 70 signal for that column in a digital form. Meanwhile, each RD 76 may provide the data clock signal (DATA_CLK) and the emission clock signal (EM_CLK) at an appropriate to activate the row of μDs 78 driven by the RD 76. A row of uDs 78 may be activated when the RD 76 that controls that row sends the data clock signal (DATA_CLK). This may cause the now-activated uDs 78 of that row to receive and store the digital image data 70 signal that is driven by the column drivers (CDs) 74. The uDs 78 of that row then may drive the pixels 80 based on the stored digital image data 70 signal based on the emission clock signal (EM_CLK).
A block diagram shown in
When the pixel data buffer(s) 100 has received and stored the image data 70, the RD 76 may provide the emission clock signal (EM_CLK). A counter 102 may receive the emission clock signal (EM_CLK) as an input. The pixel data buffer(s) 100 may output enough of the stored image data 70 to output a digital data signal 104 represent a desired gray level for a particular subpixel 82 that is to be driven by the μD 78. The counter 102 may also output a digital counter signal 106 indicative of the number of edges (only rising, only falling, or both rising and falling edges) of the emission clock signal (EM_CLK) 98. The signals 104 and 106 may enter a comparator 108 that outputs an emission control signal 110 in an “on” state when the signal 106 does not exceed the signal 104, and an “off” state otherwise. The emission control signal 110 may be routed to driving circuitry (not shown) for the subpixel 82 being driven, which may cause light emission 112 from the selected subpixel 82 to be on or off. The longer the selected subpixel 82 is driven “on” by the emission control signal 110, the greater the amount of light that will be perceived by the human eye as originating from the subpixel 82.
A timing diagram 120, shown in
It should be noted that the steps between gray levels are reflected by the steps between emission clock signal (EM_CLK) edges. That is, based on the way humans perceive light, to notice the difference between lower gray levels, the difference between the amount of light emitted between two lower gray levels may be relatively small. To notice the difference between higher gray levels, however, the difference between the amount of light emitted between two higher gray levels may be comparatively much greater. The emission clock signal (EM_CLK) therefore may use relatively short time intervals between clock edges at first. To account for the increase in the difference between light emitted as gray levels increase, the differences between edges (e.g., periods) of the emission clock signal (EM_CLK) may gradually lengthen. The particular pattern of the emission clock signal (EM_CLK), as generated by the emission TCON 72, may have increasingly longer differences between edges (e.g., periods) so as to provide a gamma encoding of the gray level of the subpixel 82 being driven.
Various components of the electronic device 10 may be used to control the current signal supplied to drive LED devices 102 of the uLED display 18. For example, as will be further appreciated, the uDs 78 may include a p-type metal-oxide-semiconductor (PMOS) device, an n-type metal-oxide-semiconductor (NMOS) device, or some combination of PMOS and NMOS devices.
In certain embodiments, the number of LED devices 208A may each be coupled to a high voltage potential rail (e.g., “VDD”) and a low voltage potential rail or ground (e.g., “VSS” or “GND”). For example, the high voltage potential rail (e.g., “VDD”) may be set to a voltage of 1.2V, 1.5V, 1.8V, 2.5V, 3.3V, 5V, or other similar voltage that may be used to supply power to the Subpixels 82 for operation. Similarly, the low voltage potential rail or ground (e.g., “VSS” or “GND”) 212A may be generally set to a ground voltage (e.g., 0 V or approximately 0 V).
In some embodiments, the uDs 78 may each include a PMOS driver used to drive the Subpixels 82. For example, PMOS drivers may be used as part of the uDs 78 in order to conserve physical area of the uLED display 18 by avoiding level shifters that may be otherwise involved. However, in some embodiments, utilizing PMOS drivers as part of the uDs 78 may lead to image artifacts (e.g., flicker) becoming present on the uLED display 18, as the PMOS drivers may be sensitive to variations of the high voltage potential rail (e.g., “VDD”) 210A. The variations of the high voltage potential rail (e.g., “VDD”) 210A may be caused by IR drop (e.g., voltage drops across the resistance R of the power supply 198A between supply pins and one or more components drawing a current I). For example,
Indeed, the VDD variations may vary depending on the incoming image data and the image pattern, as the luminance of the uLED display 18 and the characteristics of the subpixels 82 may also be variable. Furthermore, variations in the threshold voltage (e.g., “VTH”) of the subpixels 82 may also adversely impact the drive currents (e.g., “ILED”) of the subpixels 82. As may be further appreciated, the VDD and VTH variations may be exacerbated for larger area uLED displays 18. Thus, as will be further appreciated with respect to
Turning now to
For example, in an initial phase (e.g., “Phase 1”), the voltage VB may be low (e.g., approximately “GND” or 0 V). Thus, a PMOS transistor 224A (e.g., “M1”) coupled (e.g., in series) between a PMOS transistor 226A (e.g., “M2”) and the high voltage potential rail (e.g., “VDD”) 210A coupled directly to the high voltage potential rail (e.g., “VDD”) 210A may be “ON” (e.g., activated). The PMOS transistor 226A (e.g., “M2”) may also be “ON,” as the voltage EM may also be low (e.g., approximately “GND” or 0 V) in the initial phase (e.g., “Phase 1”). Accordingly, a drive current may be allowed to flow from the high voltage potential rail (e.g., “VDD”) 210A to the LED device 208A. In some embodiments, the PMOS transistor 224A (e.g., “M1”) may be susceptible to VDD voltage variations, while the PMOS transistor 226A (e.g., “M2”) may be susceptible to VTH voltage variations.
In certain embodiments, in a reset phase 229 (e.g., “Phase 2”), the voltage EM may be low (e.g., approximately “GND” or 0 V), while the voltages VA and VB may be expressed as:
Specifically, in equation (1), VRef may be the reference supply voltage for the LED device 208A that may be controlled by the PMOS 228A. In equation (2), VDD_CL may be an additional high voltage potential rail (e.g., “VDD_CL”) 217A (e.g., independent of the high voltage potential rail (“VDD_CL”) 210A). Thus, in the reset phase (e.g., “Phase 2”), when VA=VRef and VB=VDD_CL VTH, the following condition may exist:
VB=VDD_CL−VTH,for VB<VTH_LED equation (3).
In this case, the LED device 208A may not turn “ON.” Furthermore, in the reset phase (e.g., “Phase 2”), the voltage VC (e.g., voltage across a compensation capacitance 230A) may be expressed as:
VC=VRef−VDD_CL−VTH equation (4).
As may be appreciated from equation (4), the voltage VC may be a voltage across a compensation capacitance 230A that may, in some embodiments, be the difference between the reference voltage VRef and the voltage VB.
In certain embodiments, in another reset phase 231 (e.g., “Phase 3”), the voltages VA and VB may be then expressed as:
Expanding equations (5) and (6) based on equations (1), (2), and (4), the voltage VB may be then expressed as:
VB=VDD−VRef+VDD_CL−VTH equation (7).
Thus, when VB<VDD−VTH and VTH<VDD_CL<VRef, the PMOS transistor 216A (e.g., “M1”), the PMOS transistor 224A (e.g., “M5”), and the PMOS transistor 228A (e.g., “M6”) may each be “ON” (e.g., conductive or in the saturation mode). Indeed, further, when VRef<VTH<VTH Diode, the LED device 208A drive current ILED may be expressed as:
ILED=K(VGS−VTH)2=K(VDD−VB−VTH)2 equation (8).
Expanding equation (8) based on equation (7), the LED device 208A drive current ILED may be then expressed as:
ILED=K(VDD−(VDD−VRef+VDD_CL−VTH)−VTH)2 equation (9).
Lastly, simplifying equation (9), the LED device 208A drive current ILED may be expressed as:
ILED=K(VRef+VDD_CL)2 equation (10).
Accordingly, equation (10) illustrates that LED device 208A drive current ILED may be independent of the high voltage potential rail (e.g., VDD) and the threshold voltage (e.g., VTH), and may thus compensate for VDD and VTH variations that may otherwise adversely affect drive current ILED (e.g., due to IR drop). Indeed, instead of being a function of VDD and VTH (e.g., as expressed by equation (8)) and, by extension, being susceptible to VDD and VTH variations (e.g., due to IR drop), the LED device 208A drive current ILED may be function of the uDs 78 reference voltage VRef and the compensation voltage potential rail VDD_CL. In this way, any possible occurrence of image artifacts becoming apparent on the uLED display 18 may be reduced or substantially eliminated.
As a further example of the presently disclosed embodiments,
Turning now to
Turning now to
As a further example,
The specific embodiments described above have been shown by way of example, and it should be understood that these embodiments may be susceptible to various modifications and alternative forms. It should be further understood that the claims are not intended to be limited to the particular forms disclosed, but rather to cover all modifications, equivalents, and alternatives falling within the spirit and scope of this disclosure.
Number | Name | Date | Kind |
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20090109150 | Han | Apr 2009 | A1 |
20130141412 | Kang | Jun 2013 | A1 |
20140299837 | Bibl | Oct 2014 | A1 |
20160148564 | Kim | May 2016 | A1 |
Number | Date | Country | |
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62232918 | Sep 2015 | US |