The present invention will be described in detail below with reference to the drawings showing embodiments thereof.
A first embodiment of the present invention will be described with reference to
In this embodiment, a description will be given regarding an example where the driving device according to the present invention is constructed as a switching amplifier (class D amplifier) having inductive load such as a dynamic speaker as load.
The driving device 1 includes a driving circuit 10 outputting an output signal Vp-n1, an arithmetic circuit 18 detecting an inclination of a first error suppression signal Vout1 to generate an inclination signal, an error suppression circuit 11 by which, when the inclination signal of first error suppression signal Vout1 is fed back, a second error suppression signal Vout2 can be further generated, a pulse width modulation circuit (PWM) 12 as a pulse modulation means outputting pulse modulation signals Vp1 and Vp2, a gate driver 13 outputting switching control signals Vp1p, Vp1n, Vp2p and Vp2n to respective switching elements 101, 102, 103 and 104 of the driving circuit 10, and low pass filters (LPF1, LPF2) 14 and 15 as a first feedback means. Here, the error suppression circuit 11 is constructed as an integrator.
The driving circuit 10 has a switching circuit 100 including a plurality of the switching elements 101, 102, 103 and 104; inductive load L1 as the load is connected at terminals between connection points OUTP and OUTN of the driving circuit 10.
Here, in order to evaluate input reproducibility of the switching amplifier, low pass filters (LPF3, LPF4) 16 and 17 are connected to the output terminals 50 and 51 of the driving circuit 10, for the sake of convenience, whereby an output signal Vp-n10 is extracted from output terminals 52 and 53 of the low pass filters (LPF3, LPF4) 16 and 17. In this case, these low pass filters (LPF3, LPF4) 16 and 17 are not necessitated structure elements in the driving device 1, and are no relationship with the operation as a switching amplifier.
The configuration of each portion will now be described.
The arithmetic circuit 18 is connected between the error suppression circuit 11 and the pulse width modulation circuit (PWM) 12. Connection lines 19a and 19b on the input side is connected to an output line in which first error suppression signal Vout1 is outputted from the error suppression circuit 11. Connection lines 30a and 30b on the output side thereof are connected to resistors RF3 and RF4 of the error suppression circuit 11.
The arithmetic circuit 18 is a circuit for detecting a signal inclination such as a differentiation circuit but the configuration is not limited to this circuit. As another example, the arithmetic circuit 18 may be constituted of a high-pass filter having a frequency component higher than a predetermined set cutoff frequency, or a band pass filter having a limited pass-band.
After the arithmetic circuit 18 detects a inclination of first error suppression signal Vout1 outputted from the error suppression circuit 11, a detection signal Vfb2 containing the detected inclination is inputted to the error suppression circuit 11 together with fed back output signals V1a and V1b.
Then, in the error suppression circuit 11, output signals V1a and V1b containing the inclination of detection signal Vfb2 are compared with the inclination of input signal Vin. A second error suppression signal Vout2 is produced so that the inclination error between signals is suppressed.
Here, this input signal Vin may be a differential signal, or a single end that the input terminal 8a or 8b is connected to a reference signal level. Further, the error suppression circuit 11 may be a single end configuration. In this case, OUTP and OUTN as differential output are changed to a single end and the output from the single end terminal may be fed back to the error suppression circuit 11.
Also, the driving circuit 10 may have a full-bridge configuration or a half-bridge configuration. In a half-bridge configuration, one terminal of the inductive load L1 is connected to the ground. In this case, the driving circuit 10 is comprised of two switching elements 101 and 102 (or 103 and 104).
First an outline of operation of the driving device 1 shown in
In step S1, an output signal Vp-n1 at the output terminals 50 and 51 of the connection points between the terminals of the inductive load L1 and the first terminal 40 of the switching elements 101, 102, 103 and 104 is fed back as output signals V1a and V1b to the input terminals 9a and 9b via the low pass filters (LPF1, LPF2) 14 and 15. The voltage values of the fed back output signals V1a and V1b are accumulated across capacitors C2 and C3 of the differential amplifier circuit 111.
In step S2, the magnitude (amplitude) of the fed back output signals V1a and V1b is compared with the magnitude (amplitude) of input signal Vin to detect an error of magnitude (amplitude) between signals, and a first error suppression signal Vout1 is produced such that the detected error of amplitude between the signals is suppressed.
In step S3, detection signal Vfb2 containing a inclination component of first error suppression signal Vout1 detected by the arithmetic circuit 18 constituting the second feedback means is inputted via the resistors RF3 and RF4 to the error suppression circuit 11. A second error suppression signal Vout2 is produced such that the error of the inclination component of input signal Vin is suppressed.
In step S4, the pulse width modulation circuit (PWM) 12 produce pulse modulation signals Vp1 and Vp2 having modulated pulse width based on the generated second error suppression signal Vout2. The produced pulse modulation signals Vp1 and Vp2 are inputted to the third terminal 42 of the switching elements 101, 102, 103 and 104 via the gate driver 13. Thus, the switching elements 101, 102, 103 and 104 perform on/off behavior to control supplying of a current I to the inductive load L1.
The word “inclination” means a magnitude of the voltage amplitude variation contrast to time variation of continuous signal.
For example, detection signal Vfb2 is a signal produced by differentiating first error suppression signal Vout1 outputted from the arithmetic circuit 18. This output differentiation signal Vfb2 represents a variation of inclination of the first error suppression signal Vout1. As to the output, a steeper inclination becomes a larger variation.
The operation of second error suppression signal Vout2 will now be described.
(A) to (C) of
In the above described driving device 1 of
This produced first error suppression signal Vout1 varies the duty ratio of switching control signals Vp1 and VP2 as pulse modulation signals, but a waveform error component which cannot be suppressed enough by the error suppression circuit 11 still remains. This error component contained in first error suppression signal Vout1 can be regarded as a difference between the inclination of output signal waveform and the inclination of input signal waveform.
Thus, according to the present embodiment, first error suppression signal Vout1 containing that difference of inclination component is sent to the arithmetic circuit 18 constituted of a differentiation circuit. Then, an output differentiation signal Vfb2 as the inclination component is inputted via the feedback resistors RF3 and RF4 to the error suppression circuit 11.
When the arithmetic circuit 18 is a differentiation circuit, detection signal Vfb2 is a reverse signal by inverting a differential signal obtained by differentiating first error suppression signal Vout1. For example, as shown in (A) of
The error suppression circuit 11 calculates a variation component of detection signal Vfb2 to output second error suppression signal Vout2. When first error suppression signal Vout1 is a waveform without distortion, second error suppression signal Vout2 becomes a waveform having a phase lead corresponding to the magnitude of variation of detection signal Vfb2 produced by first error suppression signal Vout1, and thus there is no variation in the waveform quality.
When first error suppression signal Vout1 is distorted, as shown in (B) of
When this detection signal Vfb2′ is inputted to the error suppression circuit 11, the addition amount is large only at points where the inclination of signal waveform is steep. Thus, the inclination becomes a smooth curve only at the points where the inclination of signal waveform is steep. Then, second error suppression signal Vout2 is produced, as shown in (B) of
Here, a description will be given using formulas. When first error suppression signal Vout1 is expressed as a×sin(ωt), detection signal Vfb2′ is expressed as b×cos(ωt), and second error suppression signal Vout2 being the corrected signal is expressed as r×sin(ωt+a), r=√(a2+b2), α=tan−1(b/a). Accordingly, when there is no harmonic distortion, the input signal is faithfully reproduced (only the amplitude and phase being slightly varied). While only when there is harmonic distortion, the addition amount of the portion in which the inclination is steeper than the input signal as the distortion factor is larger than when there is no distortion. Thus, a correction is made so that the inclination becomes a smooth curve, thus reducing the distortion component.
As means for verifying the improvement effect, in order to evaluate input reproducibility, output signal Vp-n10 from the low pass filters 16 and 17 connected to the output terminals 50 and 51 of the driving circuit 10 of
That is, second error suppression signal Vout2 is produced by the arithmetic circuit 18 as the second feedback means, thus correcting the waveform distortion at the inductive load L1 to improve the input reproducibility.
As described above, in the switching amplifier of
In contrast, in the switching amplifier of
In view of the frequency domain, distortion components are lowered totally in even-order and odd-order, thus improving THD up to about 80 dB. In comparison with THD of the switching amplifier of
As the size of IC chip, in order to cope with stereo systems used in recent years, a size of about 2 mm×2 mm may be set in case that two channels are incorporated in switching amplifiers.
A second embodiment of the present invention will be described with reference to
In this example, the driving device according to the present invention is an example of a switching amplifier (class D amplifier) having capacitive load such as a piezoelectric speaker. The same reference numerals are applied to the parts corresponding to those of the first example described above and an explanation thereof is omitted.
The driving circuit 10 has a switching circuit 100 including a plurality of switching elements 101, 102, 103 and 104. Capacitive load C1 as load is connected at terminals between connection points OUTP and OUTN of the driving circuit 10.
Only load is different from that of the first embodiment shown in
The basic circuit operation of the driving device 1 will now be described with reference to the flowchart of
In step S1, an output signal Vp-n1 is produced at the output terminals 50 and 51 between the terminal of capacitive load C1 and the first terminal 40 of the switching elements 101, 102, 103 and 104. The produced output signal Vp-n1 is fed back as output signals V1a and V1b to the input side terminals 9a and 9b via the low pass filters (LPF1, LPF2) 14 and 15. The voltage values of output signals V1a and V1b are produced at capacitors C2 and C3 of the differential amplifier circuit 111.
In step S2, the magnitude (amplitude) of the fed back output signals V1a and V1b is compared with the magnitude (amplitude) of input signal Vin to detect an error of magnitude (amplitude) between signals. A first error suppression signal Vout1 is produced such that the detected error of amplitude between the signals is suppressed.
In step S3, detection signal Vfb2 containing a inclination component of first error suppression signal Vout1, detected by the arithmetic circuit 18 as the second feedback means, is inputted via the resistors RF3 and RF4 to the error suppression circuit 11. Thus, a second error suppression signal Vout2 is produced such that the error due to the inclination component of input signal Vin is suppressed.
In step S4, the pulse width modulation circuit (PWM) 12 produces pulse modulation signals Vp1 and Vp2 having modulated pulse width based on the generated second error suppression signal Vout2. The produced pulse modulation signals Vp1 and Vp2 are inputted to the gate driver 13 to produce switching control signals Vp1p, Vp1n, Vp2p and Vp2n.
The switching control signals Vp1p, Vp1n, Vp2p and Vp2n outputted from the gate driver 13 are inputted to the third terminal 42 of the switching elements 101, 102, 103 and 104. Thus, the switching elements 101, 102, 103 and 104 perform on/off behavior respectively to control supplying of a current I to the capacitive load C1.
Accordingly, when the signal correction processing is performed based on second error suppression signal Vout2 produced from the arithmetic circuit 18 as the second feedback means, waveform distortion appearing at the capacitive load C1 is corrected, thus improving input reproducibility.
A third embodiment of the present invention will be described with reference to
This example shows information apparatus including the above described driving device 1 of
The personal digital assistant 200 includes; a speaker 201 such as a dynamic speaker or a piezoelectric speaker as load (i.e. inductive load, capacitive load), the driving device 1 of
As described above, since the driving device 1 or driving device 2 is incorporated in the information apparatus 200 to control supplying of electric power to the load, sound quality of speaker can be dramatically improved, for example.
While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.
Number | Date | Country | Kind |
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2006-135596 | May 2006 | JP | national |
2007-042485 | Feb 2007 | JP | national |