The present application claims foreign priority to Chinese Patent Application No. CN201910086148.4, titled “DRIVING METHOD, DRIVING MODULE, AND DISPLAY DEVICE”, filed on Jan. 29, 2019 in the National Intellectual Property Administration, PRC, and the entire contents of which is hereby incorporated by reference.
The present disclosure relates to a field of display technology, and in particular to a driving method, a driving circuit, and a display device.
The statements herein only provide background information related to the present disclosure, and do not necessarily constitute prior art.
There are three main types of television standards worldwide, which include Phase Alteration Line (PAL) standard, National Television Standards Committee (NTSC) standard, and Sequentiel Couleur A Memoire (SECAM) standard. Commonly used standards are the PAL standard and the NTSC standard. A data signal of the PAL standard, such as format of a TV signal, is 25 frames per second. After a system on a vhip (SOC) decodes and multiplies the frequency, it is output as a data frame of 50 frames per second to a display panel, which has a refresh frequency of 50 Hz. In the NTSC standard, the TV signal includes 30 frames per second, which is processed by the SOC and output as a data frame of 60 frames per second to the display panel. In the situation, the image is restored at a refresh frequency of 60 Hz.
When the PAL standard is switched to the NTSC standard, or the NTSC standard is switched to the PAL standard, since the refresh frequency output by the SOC is different, the refresh frequency received by the display panel has a large change, and screen flickering is likely to occur at this time.
An object of the present disclosure is to provide a driving method, a driving circuit, and a display device.
The present disclosure provides a driving method. The driving method includes steps:
receiving a data signal of a first standard, generating a first data frame, and driving a display panel at a refresh frequency of the first data frame;
receiving a data signal of a second standard, calculating and generating at least one transition frame according to the data signal of the first standard and the data signal of the second standard, and driving the display panel at a refresh frequency corresponding to the at least one transition frame; and
continuing to receive the data signal of the second standard, generating a second data frame, and driving the display panel at a refresh frequency of the second data frame;
a length of one frame time of the first data frame is different from a length of one frame time of the second data frames. A length of one frame time of the at least one transition frame is between the length of one frame time of the first data frame and the length of one frame time of the second data frame.
The present disclosure further provide a driving circuit. The driving circuit includes: a receiving circuit receiving a data signal, a data frame generating circuit receiving and switching the data signal to generate a corresponding data frame, a transition frame generating circuit generating transition frames according to the received data signal, and a standard switching detecting circuit detecting the data signal received by the receiving circuit, controlling the data frame generating circuit to generate the data frame, and controlling the transition frame generating circuit to generate the transition frames;
when the standard switching detecting circuit detects that the received data signal is a data signal of a first standard, it controls the data frame generating circuit to generate a first date frame. The first date frame is corresponding to the data signal of the first standard. The first date frame drives a display panel. When the standard switching detecting circuit detects that the received data signal is switched from the data signal of the first standard to a data signal of a second standard, it controls the transition frame generating circuit to generate the transition frames to drive the display panel. Then the standard switching detecting circuit controls a second data frame generated by the data frame generating circuit to drive the display panel. The second data frame is corresponding to the data signal of the second standard.
The present disclosure further provides a display device that includes a display and the driving circuit mentioned above.
Compared with a solution of directly switching between data signals of two different standards, the present disclosure calculates and generates the at least one transition frame according to the received data signals of two different standards when switching between different standards. The present disclosure provides the transition frames when switching between two different standards. The length of one frame time of the transition frames is between the length of one frame time of the first data frame and the length of one frame time of the second data frame Frequencies of the transition frames are controlled by the length of one frame time of the transition frames, so as to ensure that the frequency of each transition frames is between the frequencies of the two switched different standards. Thus, a difference of refresh frequencies between two adjacent transition frames is reduced, which prevents a large frequency difference when switching. Further, the screen would not flicker due to the large difference in refresh frequencies, and a display effect of the display panel is excellent.
The drawings are included to provide a further understanding of embodiments of the present disclosure, which form portions of the specification and are used to illustrate implementation manners of the present disclosure and are intended to illustrate operating principles of the present disclosure together with the description. Apparently, the drawings in the following description are merely some of the embodiments of the present disclosure, and those skilled in the art are able to obtain other drawings according to the drawings without contributing any inventive labor. In the drawing:
It should be understood that specific structure and function details disclosed herein are only representative and are used for the purpose of describing exemplary embodiments of the present disclosure. However, the present disclosure may be achieved in many alternative forms and shall not be interpreted to be only limited to the embodiments described herein.
It should be understood in the description of the present disclosure that terms such as “first” and “second” are only used for the purpose of description, rather than being understood to indicate or imply relative importance or hint the number of indicated technical features. Thus, the feature limited by “first” and “second” can explicitly or impliedly include one or more features. In the description of the present disclosure, the meaning of “a plurality of” is two or more unless otherwise specified. The term “include” and any variant are intended to cover non-exclusive inclusion, which may exist or add one or more other features, integers, steps, operations, units, components, and/or combinations thereof.
In addition, terms such as “central”, “horizontal”, “upper”, “lower”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inner”, “outer”, etc. indicate direction or position relationships shown based on the drawings, and are only intended to facilitate the description of the present disclosure and the simplification of the description rather than to indicate or imply that the indicated device or element must have a specific direction or constructed and operated in a specific direction, and therefore, shall not be understood as a limitation to the present disclosure.
In addition, It should be noted in the description of the present disclosure that, unless otherwise regulated and defined, terms such as “installation,” “bonded,” and “bonding” shall be understood in broad sense, and for example, may refer to fixed bonding or detachable bonding or integral bonding; may refer to mechanical bonding or electrical bonding; and may refer to direct bonding or indirect bonding through an intermediate medium or inner communication of two elements. For those of ordinary skill in the art, the meanings of the above terms in the present disclosure may be understood according to concrete conditions.
The present disclosure will be further described in detail below in combination with the drawings and optional embodiments.
As shown in
S1: receiving a data signal of a first standard, generating a first data frame, and driving a display panel at a refresh frequency of the first data frame;
S2: receiving a data signal of a second standard, calculating and generating at least one transition frame according to the data signal of the first standard and a data signal of the second standard, and driving the display panel at a refresh frequency corresponding to the at least one transition frame; and
S3: continuing to receive the data signal of the second standard, generating a second data frame, and driving the display panel at a refresh frequency of the second data frame.
A length of one frame time of the first data frame is different from a length of one frame time of the second data frames. A length of one frame time of the at least one transition frame is between the length of one frame time of the first data frame and the length of one frame time of the second data frame.
The transition frame generating circuit 123 is directly connected to the receiving circuit 121. The data frame generating circuit 122 is directly connected to the receiving circuit 121. The standard switching detecting circuit 124 detects the data signal received by the receiving circuit, and selectively controls the data frame generating circuit 122 to generate data frames or controls the transition frame generating circuit 123 to generate the transition frames to drive the display panel.
When the standard switching detecting circuit detects that the received data signal is a data signal of a first standard, it controls a first data frame generated by the data frame generating circuit corresponding to the data signal of the first standard to drive the display panel. When the standard switching detecting circuit detects that the received data signal is switched from the data signal of the first standard to the data signal of the second standard, it controls the transition frame generating circuit to generate the transition frames to drive the display panel. Then the standard switching detecting circuit controls the second data frame generated by the data frame generating circuit corresponding to the data signal of the second standard to drive the display panel.
The driving circuit 120 further includes a system chip 125 and a timing control circuit 126. The receiving circuit 121, the data frame generating circuit 122, the transition frame generating circuit 123, and the standard switching detecting circuit 124 are integrated on the system chip 125. The data frame generated by the data frame generating circuit 122 and the transition frames generated by the transition frame generating circuit 123 are sent to the timing control circuit 126 to drive the display panel 110.
When the data signal is switched from the first standard to the second standard, the standard of the TV signal is still taken as an example, such as the PAL standard and the NTSC standard, the refresh frequencies of the data frames driving the display panel generated by the data frame generating circuit of the display panel are different. If the refresh frequencies of the data frames generated by the two standards differs greatly, a difference between two adjacent frames is too large when the two standards are switched from one to the other, which causes the screen to flicker, brings a bad sensory experience to a user, affects a display effect.
In order to avoid the difference between the two refresh frequencies when the two standards are switched from one to the other, when the data signals of the two standards are switched, at least one transition frame is calculated and generated according to the received data signals of the two standards. Because the two standards are different, the length of one frame time of the first data frame is different from the length of one frame time of the second data frames, and the length of one frame time of the at least one transition frame is between the length of one frame time of the first data frame and the length of one frame time of the second data frame. The refresh frequency of the first data frame corresponding to the data signal of the first standard is switched to the refresh frequencies of the transition frames first, and then the refresh frequencies of the transition frames are switched to the refresh frequency of the second data frame corresponding to the data signal of the second standard, so that the difference in refresh frequencies between two adjacent frames is reduced, and the screen would not flicker due to the excessive difference in refresh frequencies, and the display effect of the display panel is good.
In addition, in some embodiment, the driving circuit of the display panel includes a frequency locking circuit for protection. When fluctuation of a signal frequency of the data signal exceeds a predetermined threshold, the frequency locking circuit triggers a frequency lock function, determines that an input data signal is abnormal, and interrupts the input data signal to protect the display panel. Therefore, for a frequency-locked display panel, when the standards of the input data signals are switched, the generated transition frames are inserted, and the frequency difference between two adjacent frames is reduced. Thus, even if the frequency difference between the two standards is large, it would not cause false triggering of the frequency locking circuit and avoid affecting normal display of the display panel.
Of course, the first standard is the PAL standard, the NTSC standard or other standards, and the second standard is PAL standard, the NTSC standard or other standards. The data frame generating circuit decodes and multiplies the data signal received by the receiving circuit to generate a data frame. The data frame uses different formats for inputting to display panels of different resolutions, For the display panel with High Definition (HD) resolution or Full High Definition (FHD) resolution, the data frame is input by Low-Voltage Differential Signaling (LVDS) signal format. For the display panel with Ultra High-Definition (UHD) resolution or even higher resolutions, the data frame is input to the display panel by a video by one (VBO) signal format.
In one embodiment, for one data frame, whether it is the first data frame, the second data frame, or the transition frame, a length of each frame time includes a line scanning time (HActive) and a line idle time (HBlank). The line scanning time is a working time of an actual number of lines that the scanning lines on the display panel are sequentially turned on. The number of the scanning lines of the horizontal lines of the current frame is recorded as Vactive. The line idle time is a virtual time which is the time when there is no scanning line working. During the line idle time, the scanning lines do not work. The number of idle lines in the horizontal lines of the current frame is recorded as Vblank. The number of the idle lines of the horizontal lines of the current frame, Vblank, is the number of virtual lines.
Specifically, in the step S2, the number of frames of the generated at least one transition frame is optionally set from 2 to 5 frames, and the refresh frequency of each transition frame is calculated according to the number of frames set in the transition frames. A difference between refreshed frequencies of any two adjacent frames in a last frame of the first data frame, the transition frames, and a first frame of the second data frame is equal.
Specifically, the line idle time is adjusted to change the length of each transition frame. In step S2: the number of the generated transition frames is optionally set to be no less than 3 frames. As shown in
In one embodiment, the line scanning time of the transition frames is equal to the line scanning time of the first data frame or the line scanning time of the second data frame. In the first data frame and the second data frame, a data frame with a shorter length of one frame time is a first reference data frame. As shown in
Each transition frame includes parameter information of the number of scanning lines of horizontal lines corresponding to the line scanning time, and parameter information of the number of horizontal idle lines corresponding to the line idle time. The first reference data frame includes parameter information of the number of the scanning lines of horizontal lines corresponding to the line scanning time and the parameter information of the number of horizontal idle lines corresponding to the line idle time. The number of horizontal idle lines of each transition frame is greater than the number of horizontal idle lines of the first reference data frame. The number of scanning lines of horizontal lines of each transition frame is equal to the number of scanning lines of horizontal lines of the first data frame and the second data frame. Since the opening time of each scanning line is relatively determined, the line scanning time and the line idle time are determined according to the number of the scanning lines of horizontal lines and the number of the horizontal idle lines.
Of course, in the first data frame and the second data frame, as a reference, a data frame with a longer length of one frame time is a second reference data frame. As shown in
The length of the line idle time of each transition frame is greater than the length of a shorter line idle time in the first data frame and the second data frame, so that the two standards are switched through the transition frames to reduce the frequency difference when switching between the two frames with two different standards. Specific analysis and calculation of a frame frequency refer to following formulas:
F=DCLK/(Htotal*Vtotal);
Vtotal=Vactive+Vblank;
Htotal=Hactive+Hblank.
F is a frequency of a current frame. DCLK is a signal transmission frequency of the current frame. Vtotal is a total number of horizontal lines of the current frame; Htotal is a total number of vertical lines of the current frame. Vactive is the number of scanning lines of horizontal lines in the current frame. Vblank is the number of horizontal idle lines in the current frame. Hactive is the number of vertical scanning lines in the current frame. Hblank is the number of vertical idle lines in the current frame.
In addition, in the step S2, the number of frames of the generated transition frames is optionally set from 2 to 5 frames, and the refresh frequency of each transition frame is calculated according to the number of frames set in the transition frames. A difference between refreshed frequencies of any two adjacent frames in a last frame of the first data frame, the transition frames, and a first frame of the second data frame is equal.
It should be noted that the difference between the refreshed frequencies of adjacent transition frames is a fixed value. In the last frame of the first data frame, the transition frames, and the first frame of the second data frame, the frequency of any two adjacent frames increases or decreases in sequence with the fixed value. If the refresh frequency of the first standard is greater than the refresh frequency of the second standard, when the first standard is switched to the second standard, the refreshed frequencies of the transition frames are sequentially increased. When the second standard is switched to the first standard, the refreshed frequencies of the transition frames are sequentially decreased. Or, the difference between the refreshed frequencies of adjacent transition frames is a variable value, and the variable value may increase or decrease sequentially.
The number of transition frames may be 2, 3, 4, or 5 frames. The selection of the number of transition frames mainly refers to the difference between the refresh frequency of the first data frame corresponding to the data signal of the first standard and the refresh frequency of the second data frame corresponding to the data signal of the second standard. As shown in
Of course, the difference of the refresh frequencies between two adjacent transition frames may be predetermined. A specific number of frames is calculated according to the difference between the refresh frequency of the first data frame corresponding to the data signal of the first standard and the refresh frequency of the second data frame corresponding to the data signal of the second standard. For example, the difference between refreshed frequencies of any two adjacent frames in the last frame of the first data frame, the transition frames, and the first frame of the second data frame is a fixed value. The fixed value is set in a range of 1-4 Hz to generate refreshed frequencies of the frames. For different differences, the number of transition frames is also different. Of course, if the display panel can adapt to the switching of the refresh frequencies of frames with a large difference, then the fixed value is able to be greater than 4 Hz.
In one embodiment, the present disclosure take the switch between the PAL standard and NTSC standard as an example, if the refresh frequency of the PAL standard driving the display panel is 60 Hz, and the refresh frequency of the NTSC standard driving the display panel is 50 Hz, then a recommended fixed value is 2 Hz. The refresh frequency of each transition frame is increased or decreased by 2 Hz, and the difference of the refresh frequencies of two adjacent transition frames is generally set as 2 Hz. When the NTSC standard is switched to the PAL standard, the switching is completed in 5 frames, and the refresh frequency of each frame is 50 Hz, 52 Hz, 54 Hz, 56 Hz, 58 Hz, 60 Hz. When the PAL standard is switched to the NTSC standard, the switching is completed in 5 frames, and the refresh frequency is 60 Hz, 58 Hz, 56 Hz, 54 Hz, 52 Hz, 50 Hz. Therefore, the difference of the refresh frequencies of the frames is small when switching, and the signal is output smoothly without affecting the display effect.
As shown in
At the HD resolution (1366*768): Vactive=768, Vblank=38, then Vtotal=806; Hactive=1366, Hblank=194, then Htotal=Vactive+Vtotal=1560.
At the FHD resolution (1920*1080): Vactive=1080, Vblank=45, then Vtotal=Vactive+Vtotal=1125; Hactive=960, Hblank=140, then Htotal=1100.
When at UHD resolution (3840*2160), that is, 4K resolution: which is equivalent to 4 times the data volume of FHD resolution.
When at 8K resolution (7680*4320): the data volume is equivalent to 4 times the data volume of UHD resolution. In the present disclosure, only transmission methods of the HD and FHD resolutions are listed herein.
Specifically, the value of Vtotal is changed 5 times, and the frequency of each frame is 50 Hz→452 Hz→54 Hz→56 Hz→58 Hz→60 Hz in sequence, so that the refresh frequency is switched from 50 Hz to 60 Hz. During a switching process, calculating processes of values of the horizontal lines of the transition frames is as follows:
Frame 1 (the last frame of the PAL standard):
At HD resolution: Vtotal=75441600/50/1560=967.2.
The Vtotal is rounded down to a nearest integer 967, then Vblank=967−768=199.
At FHD resolution: Vtotal=74250000/50/1100=1350, then Vblank=1350−1080=270.
Frame 2 (the first frame of the transition frame):
At HD resolution: Vtotal=75441600/52/1560=930, then Vblank=930−768=162.
At FHD resolution: Vtotal=74250000/52/1100=1298.07. The Vtotal is rounded down to a nearest integer 1298, then Vblank=1298−1080=218.
Frame 3 (the second frame of the transition frame):
At HD resolution: Vtotal=75441600/54/1560=895.56,
The Vtotal is rounded up to a nearest integer 896, then Vblank=896−768=128.
At FHD resolution: Vtotal=74250000/54/1100=1250, then Vblank=1250−1080=170.
Frame 4 (the third frame of the transition frame):
At HD resolution: Vtotal=75441600/56/1560=863.57.
The Vtotal is rounded up to a nearest integer 864, then Vblank=864−768=97.
At FHD resolution: Vtotal=74250000/56/1100=1205.36;
The Vtotal is rounded down to a nearest integer 1205, then Vblank=1205−1080=125.
Frame 5 (the fourth frame of the transition frame):
At FHD resolution: Vtotal=75441600/58/1560=833.79.
The Vtotal is rounded up to a nearest integer 834, then Vblank=834−768=66.
At FHD resolution: Vtotal=74250000/58/1100=1163.79;
The Vtotal is rounded up to a nearest integer 1164, then Vblank=1164−1080=84.
Frame 6 (the last frame of the NSTC system):
At HD resolution: Vtotal=75441600/60/156806, then Vblank=806−768=38.
At FHD resolution: Vtotal=4250000/60/1101125, then Vblank=1125−1080=45.
Of course, in the present disclosure, it is also possible that the length of the line scanning time of each transition frame is not equal to the length of the line scanning time of the data frame of the first standard or the length of the line scanning time of the data frame of the second standard. As shown in
In step S2, transition frames including an enable signal (DE) and an image data signal (Data) are also generated. As shown
Above embodiments shows driving steps for switching from the PAL standard to the NTSC standard. If the NTSC standard is switched to the PAL standard, the above steps are reversed.
The transition frame generating circuit 123 is directly connected to the receiving circuit 121 to obtain the data signal. Of course, as another embodiment of the present disclosure, the present disclosure further provides a driving circuit applying the above driving method. As shown in
When the standard switching detecting circuit 124 detects that the received data signal is the data signal of the first standard, it controls the data frame signal generated by the data frame generating circuit 122 corresponding to first date frame to drive the display panel. When the standard switching detecting circuit 124 detects that the received data signal is switched from the data signal of the first standard to the data signal of the second standard, it controls and starts the transition frame generating circuit 123. The transition frame generating circuit 123 receives the data signal of the data frame generated by the data frame generation circuit 122, generates the transition frames to drive the display panel. Then the standard switching detecting circuit 124 controls the second data frame generated by the data frame generating circuit corresponding to the data signal of the second standard is applied to drive the display panel.
It should be noted that technical solutions of the present disclosure are able to be combined and applied on a premise of not conflicting with each other. The limitations of the steps involved in the embodiments are not considered as limiting the order of the steps without affecting the implementation of the specific embodiments. The steps written before is able to be executed first, executed later, or even executed simultaneously. As long as the embodiments can be implemented, it should be regarded as falling within the protection scope of the present disclosure.
The technical solutions of the present disclosure are able to be widely used in various display panels, such as Twisted Nematic (TN) display panels, In-Plane Switching (IPS) display panels, Vertical Alignment (VA) display panels. display panels, and Multi-Domain Vertical Alignment (MVA) display panels. Of course, the present disclosure are able to be widely used in other types of display panels, such as Organic Light-Emitting Diode (OLED) display panels, which is also able to be applies to the above embodiments.
The above content is a further detailed description of the present disclosure in conjunction with specific optional embodiments, and is not considered that the specific embodiments of the present disclosure are limited to these descriptions. For those of ordinary skill in the field to which the present disclosure belongs, a number of simple deductions or substitutions can be made without departing from the concept of the present disclosure, which should all be regarded as falling within the protection scope of the present disclosure.
Number | Date | Country | Kind |
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201910086148.4 | Jan 2019 | CN | national |
Filing Document | Filing Date | Country | Kind |
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PCT/CN2019/130289 | 12/31/2019 | WO |
Publishing Document | Publishing Date | Country | Kind |
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WO2020/156007 | 8/6/2020 | WO | A |
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