Patent Application
20070152913
1. Field of the Invention
The present disclosure relates to plasma displays, and more particularly, to a technique of generating voltages for electrodes of a pixel in a plasma display in a manner that significantly reduces the address time by improving the wall voltage establishment in both sustain gap and plate gap while retaining low level of background glow.
2. Description of the Related Art
Most commercial plasma display panels (PDP's) are of the surface discharge type. The constitution of a plasma display panel of the prior art is described below with reference to the accompanying drawing.
Back plate assembly 106 includes a glass back plate 115 upon which plural column address electrodes 116, i.e., data electrodes, are located. Data electrodes 116 are covered by a dielectric layer 117. Barrier 118 separates front plate assembly 103 and back plate assembly 106. Red phosphor layer 120, green phosphor layer 121, and blue phosphor layer 122 are located on top of the dielectric layer 117 and along the sidewalls created by barriers 118. Each pixel of PDP 100 is defined as a region proximate to an intersection of (i) a row including sustain electrode 111 and scan electrode 112, and (ii) three column address electrodes 116, one for each of red phosphor layer 120, green phosphor layer 121, and blue phosphor layer 122.
Barrier ribs 118 separate color channels formed by barrier ribs 118, front plate assembly 103 and back plate assembly 106. Sub-pixels 140 are formed as an area bounded by the sides of barrier ribs 118 and the area defined by sustain electrodes 111. A gas discharge 145 is generated by a voltage applied between sustain electrode 111 and scan electrode 112, which creates vacuum ultraviolet (VUV) light that excites the red, green, and blue phosphor layers, respectively to emit visible light. For example, green phosphor 121, as shown in
The operating sustain voltage of PDP 100 is determined by a geometry of a sustain gap 130, dielectric layer 113, the particular gas mixture used, and a secondary electron emission coefficient of the protective MgO layer 114 on front plate 110. The visible light generated in the sustain discharges is responsible for the brightness of a color PDP. Initiation of sustain discharges is achieved by an addressing discharge through a plate gap 131 prior to sustain discharges, which is further described below. A full color image is generated by appropriately controlling the driving voltage on sustain electrodes 111, scan electrodes 112, and addressing electrodes 116.
In operation, as shown in
The setup period resets any ON pixels to an OFF state, and provides priming to the gas and to the surface of protective layer 114 to allow for subsequent addressing. In the setup period, it is desirable that each interior surface of the pixel's electrodes is placed at a voltage very close to a firing voltage of the gas.
During the addressing period, the sustain electrodes are driven with a common potential, while scan electrodes are driven such that a row of pixels is selected so that pixels in that row can be addressed via an addressing discharge triggered by an application of a data voltage on a vertical column electrode. Thus, during the addressing period, each row is sequentially addressed to place desired pixels in the ON state.
During the sustain period, a common sustain pulse is applied to all scan electrodes to repetitively generate plasma discharges at each sub-pixel addressed during the addressing period. That is, if a sub-pixel is turned ON during the address period, the pixel is repetitively discharged in the sustain period to produce a desired brightness.
In order to exhibit a full color image on a plasma display panel (PDP) from a video source, a proper driving scheme is needed to achieve sufficient gray scale and minimize motion picture distortion. In AC plasma display panels, a widely used driving scheme to accomplish gray scale in pixels is the so called ADS (address display separated) suggested by Shinoda (Yoshikawa K, Kanazawa Y, Wakitani W, Shinoda T and Ohtsuka A, 1992 Japan. Display 92, 605).
Referring to
As shown in
More sub-fields and higher resolution PDP TV sets requires a shorter total scanning time to leave enough time for the sustain periods which determine the brightness of the display. In order to achieve shorter total scanning time, faster addressing in each sub-pixel is needed. In order to achieve a fast and reliable addressing, the delay time before the start of the address discharge should be kept as short as possible and the jitter of the discharge should also be kept as low as possible.
The delay time of the start of the discharge, also called the formative delay, is determined by the electric field across the gas in the plate gap 131. The stronger the field across the gas the shorter the formative delay of the discharge. The jitter of the discharge, also defined as statistical delay, is mainly due to the quantity of priming particles, such as UV photons, electrons, ions, and metastable atoms, present in the gas volume 125 during the address period. An increase in the quantity of priming particles left at the address time lowers the jitter occurring during addressing, i.e., results in a shorter statistical delay.
The wall charge is defined as charge accumulation on the dielectric surfaces, including the surface of protective layer 114 and the surfaces of phosphor layers 120, 121 and 22, due to gas discharge. The wall charge on each surface has its own charge distribution caused by the gas discharge. The wall charge provides extra voltage, defined as wall voltage, across the gas. Wall voltage may be measured as plate gap wall voltage or sustain gap wall voltage. The total voltage across the gas is the difference between wall voltage and an external voltage applied to the electrodes.
The addressing time is determined by how fast the addressing discharge occurs. The addressing discharge is initiated or triggered by a plate gap discharge which determines the formative delay of the addressing discharge. The stronger the electric field across plate gap 131, the shorter the formative delay. Higher wall voltage establishment in the plate gap helps to provide the highest possible electric field across the plate gap at addressing time, which leads to the fastest formative delay. Also because of the higher electric field across the plate gap, priming particles (such as electrons) can be easily released from protective layer 114 on the front plate to significantly reduce the statistical delay. As a result, a faster address discharge can be achieved.
To reduce the cost of data driving circuits, the address voltage applied on the address electrodes is kept below about 80V. There is therefore a need to provide a stronger field in the plate gap to reduce addressing time, without increasing the address voltage. There is also a need to provide a better priming condition at the time of addressing. Furthermore, there is a need to reduce the addressing time of plasma display panels.
There is provided a method for controlling a pixel in a plasma display. The method includes applying a first voltage to a first electrode, a second voltage to a second electrode, and a third voltage to a third electrode to generate a first plasma discharge of a dischargeable gas in the pixel. The method also includes applying a forth voltage to the first electrode, a fifth voltage to the second electrode, and a sixth voltage to the third electrode to generate a second plasma discharge of the dischargeable gas in the pixel. The first plasma discharge establishes a first wall potential between the first electrode and the third electrode. The second plasma discharge establishes a second wall potential between the first electrode and the third electrode. The second wall potential is offset from the first wall potential. There is also provided a plasma display and a controller that employ the method.
The present invention provides waveform techniques for activating a strong plate gap discharge before an addressing period, and before or during a ramp setup period. The waveforms of the present invention result in a greater wall voltage across the plate gap and better distribution of wall voltage (or potential) across the plate gap by introducing a plate gap discharge prior to, or during, the ramp setup period. A well built-up wall voltage across the plate gap can trigger a faster addressing discharge, thus allowing for a significant reduction of the addressing time.
In one embodiment, there is provided a method for controlling a pixel in a plasma display. The method includes applying a first voltage to a first electrode, a second voltage to a second electrode, and a third voltage to a third electrode to generate a first plasma discharge of a dischargeable gas in the pixel. The method also includes applying a forth voltage to the first electrode, a fifth voltage to the second electrode, and a sixth voltage to the third electrode to generate a second plasma discharge of the dischargeable gas in the pixel. The first plasma discharge establishes a first wall potential between the first electrode and the third electrode. The second plasma discharge establishes a second wall potential between the first electrode and the third electrode. The second wall potential is offset from the first wall potential. There is also provided a plasma display and a controller that employ the method.
There is also provided a controller for a plasma display that includes a module that applies a first voltage to a first electrode, a second voltage to a second electrode, and a third voltage to a third electrode to generate a first plasma discharge of a dischargeable gas in the pixel. The module also applies a forth voltage to the first electrode, a fifth voltage to the second electrode, and a sixth voltage to the third electrode to generate a second plasma discharge of said dischargeable gas in said pixel. The module applies voltages to the electrodes in a manner described in the method provided herein. There is further provided a plasma display including a first electrode, a second electrode, and a third electrode, and a controller that applies voltages to the electrodes in a manner described in the method provided herein.
In one embodiment, the waveform technique creates an offset of voltages applied to the scan and sustain electrodes sufficient to cause a discharge which results in wall charge being applied to the data electrode. In another embodiment, the waveform technique creates an offset of voltages applied to the scan and data electrodes, which also results in wall charge being applied to the data electrode. This accumulation of wall charge at the data electrode contributes to both a plate gap and sustain gap wall voltage that is very close to the breakdown voltage, for example, on the order of a few volts below the breakdown voltage, by the end of the setup period. As a result, a faster addressing can be accomplished.
In one embodiment, the waveform technique activates a strong plate gap discharge during the ramp setup period. A better wall charge build-up in the plate gap is created by the new waveform, which helps to trigger the address discharge faster. As a result, a significant reduction of addressing time is achieved. The waveform increases the voltage between front electrodes and back electrodes during the ramp setup period. Increasing the voltage on both scan electrodes and sustain electrodes at front plates relative to data electrodes at back plates during the ramp rise period can increase more wall charge built-up on data electrodes.
The methods disclosed below, corresponding to
Referring again to
At time t3, during the setup period and prior to ramping down the voltage on scan electrode 112, the voltage on sustain electrode 111 is quickly reduced to a voltage Vfb. This creates a large voltage difference between scan electrode 112 and sustain electrode 111. In one embodiment, the voltage drop on sustain electrode 111 is preferably in the range of about 50V to about 350V, depending on the pixel cell structure. This reduction of voltage occurs prior to a ramp-down period that occurs between times t4 and t5.
At time t4, the voltage is gradually decreased, i.e., ramped down, on scan electrode 112. During the ramp-down period between times t4 and t5, the scan electrode produces a very slight background glow as result of a small positive resistance discharge in plate gap 131 and sustain gap 130. At time t6, the beginning of the addressing period, the voltage on scan electrode 112 is increased to voltage Vscan. The step voltage Vscan at time t6 is used for preventing wall charge leakage and row isolation during addressing.
At time t7, the sub-pixel corresponding to electrodes 111, 112 and 116 is addressed. Data electrode 116 experiences an increase of voltage to voltage Vx. The voltage is lowered on scan electrode 112 at time t7 to negative voltage Vo in order to increase the voltage across the sustain gap and plate gap. As a result, a lower voltage Vx can be applied to the data electrode to achieve the desired voltage at time t7, as compared to the instance where the voltage applied to the scan electrode is zero. Voltage Vo is typically less than 10 volts for the purpose of reducing data voltage Vx. During the first sustain period, a first sustain pulse is applied to scan electrode 112 at voltage Vset, which is usually higher in magnitude and wider in time compared to the remaining pulses in the sustain pulse train.
As is discussed below, the waveforms of
Referring again to
Referring again to
A slow ramping down of voltage on scan electrode 112 from time t4 to t5 produces very little background glow as result of a small positive resistance discharge in plate gap 131 and sustain gap 130. Referring to
Referring again to
Referring again to
Referring again to
Another strong negative resistance discharge in sustain gap 130 is expected at time t4. Weak positive resistance discharges occur in both sustain gap 130 and plate gap 131 during voltage ramping down period (from t4 to t5).
Thus, the plate gap wall voltage Wad(A) is significantly increased from Vwall3 to Vwall4 due to strong sustain gap discharge at time t3 as a result in the drop of voltage applied to sustain electrode 111. This is desirable because increased plate gap wall voltages Wad(A) before the ramp down period beginning at time t4 result in a more positive resistance discharge during the ramp down period, which in turn results in the establishment of a more stable plate gap wall voltage Wad(A) that is close to the breakdown voltage at time t5. As a result, a faster addressing can be accomplished. The above waveform results in a reduction of address time of approximately 50%.
Referring to
In this embodiment, the waveforms of
In this case, by applying a negative voltage Vfx in the ramp setup period, a strong discharge takes place across plate gap at time t81 if the previous sub-field is addressed. A strong build up of plate gap wall voltage Wad(A), similar to Vwall4 in
Referring to
In this embodiment, the waveforms of
In this embodiment, the setup period begins at time t93. Prior to the setup period, at time t90 through time t92, a sustain voltage pulse Vs is applied to scan electrode 112. A sustain voltage pulse Vs is also applied to sustain electrode 111 and reduced to zero at time t91. Between times t90 and t92, a negative voltage Vfx is applied to data electrode 116. A strong plate gap discharge occurs between scan electrode 112 and data electrode 116 at time t90 and a sustain gap discharge between scan electrode 112 and sustain electrode 111 at t91. A strong discharge across both plate gap and sustain gap occurs at t92. Discharge occurring at t90 and t92 increases the wall charges in plate gap 131 prior to the ramping up of voltage at time t93. The ramp in the time period of t93 to t95 helps to establish wall voltage both in the plate gap and the sustain gap close to breakdown voltage. The increased wall charge built up in the plate gap, as a result of the negative voltage applied to data electrode 116 also improves the priming condition of address discharge. As a result, a significant reduction of address time is achieved by this waveform.
Referring to
In this embodiment, the waveforms of
In this embodiment, a positive voltage Vfx is applied to data electrode 116 during a sustain pulse period immediately preceding the setup period. Positive voltage Vfx is applied to data electrode 116 between times tX0 and tX1. At time tX0, a sustain pulse applied during the preceding sustain period ends, and voltage Vfx is applied at time tX0 until time tX1, when the setup period begins.
Strong plate gap discharges and weak sustain gap discharges occur between time tX0 and tX1, as a result of the voltage increase on data electrode 116, before the ramping up period between times tX1 and tX4. These strong plate gap discharges help to establish wall charges in plate gap 131. The ramp setup period from tX0 to tX5, in conjunction with the voltage offset between scan electrode 112 and data electrode 116 between time tX0 and tX1, provides good wall voltages close to the breakdown voltage of both plate gap 131 and sustain gap 130. Thus, similar to previous embodiment, this embodiment of the waveform of the present invention can also achieve a very fast addressing discharge.
The present invention significantly reduces the address time by improving wall voltage establishment in both sustain gap and plate gap while retaining a low level of background glow. Wall voltage is induced by accumulation of wall charges induced in a sub-pixel. A fast address time has numerous benefits, including allowing for more time for more sub-fields which results in higher resolution, and allowing more time for sustain periods which increases brightness. As a result, higher brightness and higher resolution display can be achieved with the voltage levels equal to or less than those currently employed in the art to drive PDP's.
The present invention has been described with particular reference to the preferred embodiments. It should be understood that the foregoing descriptions and examples are only illustrative of the invention. Various alternatives and modifications thereof can be devised by those skilled in the art without departing from the spirit and scope of the present invention. Accordingly, the present invention is intended to embrace all such alternatives, modifications, and variations that fall within the scope of the appended claims.
