Patent Application
20240087532
This application claims priority to Chinese Patent Application No. 202310990777.6 filed with the China National Intellectual Property Administration (CNIPA) on Aug. 8, 2023, the disclosure of which is incorporated herein by reference in its entirety.
The present disclosure relates to the field of display technology, for example, a driving method of a display panel and a display device.
With the widespread use of electronic devices (such as mobile phones and tablet computers), the electronic devices can support more and more applications, and the functions become more and more powerful. The electronic devices are developed in a diversified and personalized direction and become indispensable electronic supplies in the life of users.
In the current display devices, panels or devices including electroluminescent devices such as organic light-emitting diodes and mini diodes can generally be driven according to different drive frequencies. That is, a display panel may display an image according to different refresh frequencies. When high-speed driving is required, a pixel is driven by increasing a refresh frequency. When power consumption must be reduced, or low-speed driving is required, a pixel is driven by reducing a refresh frequency.
In the related art, when a screen is applied to a frequency-convertible scenario, the working frequency range of the screen may be changed. However, based on the consideration of a display effect, frequency switching is often limited, that is, selectable frequencies are limited.
The present disclosure provides a driving method of a display panel and a display device.
The present disclosure provides a driving method of a display panel. The display panel to which the driving method is applied includes a fundamental frequency display frame and a low frequency display frame. The display panel also includes a light emission control signal and a bias adjustment signal. In the fundamental frequency display frame, the light emission control signal includes a light emission control period. The bias adjustment signal includes a bias adjustment period. The bias adjustment period is M times greater than the light emission control period. M is a positive integer. The fundamental frequency display frame includes a fundamental frequency scan stage. The time of the fundamental frequency scan stage is N times greater than the light emission control period. N is a positive integer greater than or equal to 2. The low frequency display frame includes a fundamental frequency scan stage and a blank stage. The blank stage includes at least a non-bias stage. The time of the non-bias stage is L times greater than the light emission control period. L is not an integer multiple of M.
The present disclosure also provides a display device. A display panel included in the display device is driven by the preceding driving method.
The drawings, which are incorporated in and constitute a part of the description, illustrate embodiments of the present disclosure.
Various example embodiments of the present disclosure are described in detail with reference to the drawings. It should be noted that relative arrangements of components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless otherwise specified.
The following description of at least one example embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure and the present application or usages thereof.
Techniques, methods, and devices known to those of ordinary skill in the related art may not be discussed, but where appropriate, such techniques, methods, and devices should be considered part of the specification.
In all examples shown and discussed herein, any values should be construed as merely exemplary and not as limiting. Therefore, other examples of the example embodiments may have different values.
It is apparent for those skilled in the art that various modifications and changes in the present disclosure may be made without departing from the spirit or scope of the present disclosure. Accordingly, the present disclosure is intended to cover modifications and variations of the present disclosure that fall within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It is to be noted that embodiments of the present disclosure, if not in collision, may be combined with each other.
It should be noted that similar reference numerals and letters indicate similar items in the drawings below, and therefore, once a particular item is defined in a drawing, the item need not to be further discussed in following drawings.
Referring to
The display panel 000 also includes a light emission control signal EM and a bias adjustment signal SP1. In the fundamental frequency display frame, the light emission control signal EM includes a light emission control period T-EM, and the bias adjustment signal SP1 includes a bias adjustment period T-SP1. The bias adjustment period T-SP1 is M times greater than the light emission control period T-EM. M is a positive integer.
The fundamental frequency display frame includes a fundamental frequency scan stage J0. The time of the fundamental frequency scan stage J0 is N times greater than the light emission control period T-EM. N is a positive integer greater than or equal to 2.
The low frequency display frame includes a fundamental frequency scan stage J0 and a blank stage J1. The blank stage J1 includes at least a non-bias stage J11. The time of the non-bias stage J11 is L times greater than the light emission control period T-EM. L is not an integer multiple of M.
The driving method provided by this embodiment may be applied to a display panel including an electroluminescent device such as an organic light-emitting diode display panel or a micro light-emitting diode display panel. For example, when the display panel 000 is an organic light-emitting diode display panel, the display panel 000 may include multiple sub-pixels P. For example, the multiple sub-pixels P may include multiple different colors (illustrated and distinguished by different filling patterns in
As shown in
In this embodiment, the display panel 000 also includes a light emission control signal EM and a bias adjustment signal SP1. A control terminal of the light emission control module 101 (a control terminal of the first light emission control module 1011 and a control terminal of the second light emission control module 1012 may be connected and both used as the control terminal of the light emission control module 101) is electrically connected to the light emission control signal EM. Under the control of the light emission control signal EM, whether or not a first terminal and a second terminal of the light emission control module 101 are conductive is implemented. The first light emission control module 1011 and the second light emission control module 1012 may be turned on at the same time. During the driving process of the display panel 000, in the light emission stage of the pixel circuit 10, the light emission control signal EM controls the first terminal and the second terminal of the first light emission control module 1011 to be conductive and controls the first terminal and the second terminal of the second light emission control module 1012 to be conductive. The on path of the first light emission control module 1011, the drive transistor DT, the second light emission control module 1012, and the light-emitting element 20 is formed between the first power signal Vpvdd and the second power signal Vpvee. The drive current drives the light-emitting element 20 to emit light. A control terminal of the bias adjustment module 102 is electrically connected to the bias adjustment signal SP1. Under the control of the bias adjustment signal SP1, whether or not the first terminal and second terminal of the bias adjustment module 102 are conductive is implemented. During the driving process of the display panel 000, in the bias voltage adjustment stage of the pixel circuit 10, the bias adjustment signal SP1 controls the first terminal and the second terminal of the bias adjustment module 102 to be conductive. The bias voltage signal VD is transmitted to the first pole of the drive transistor DT. The bias state of the drive transistor DT is adjusted, so that the drive transistor DT is reverse biased. The first pole and the second pole of the drive transistor DT are inverted. In this manner, the degree of polarization of ions inside the drive transistor DT is weakened, and the threshold voltage of the drive transistor DT is reduced. Thus, the forward bias state of the drive transistor DT is compensated, so that the threshold voltage drift is caused by the hysteresis effect of the drive transistor DT, and the impact of the hysteresis effect of the drive transistor DT on the display effect in the display panel 000 is alleviated, thereby improving the display effect.
It is to be understood that in this embodiment,
In the related art, during the driving process of a frequency-convertible display panel 000, if frequency reduction is performed on the fundamental frequency display frame to the low frequency display frame, the frequency reduction method may generally adopt two forms, namely frame skip and long-V. Frame skip refers to frequency reduction through frame insertion. For example, a frequency is reduced from 60 Hz to 30 Hz, and then the frequency may be composed of two frames of 60 Hz. The first frame is a data write frame, and the second frame is a data maintenance frame. Long_V refers to frequency reduction through the insertion of the pulse period of the light emission control signal EM, that is, the insertion of an EM pulse. For example, the frequency of the fundamental frequency display frame is 60 Hz, including 4 EM pulses. If the frequency is reduced to 30 Hz, the frequency is composed of 2 frames of 60 Hz, that is, 8 EM pulses. If the frequency is reduced to 40 Hz, 2 EM pulses may be inserted for implementation. At this time, one frame (4 EM pulses) is a data write time period, and 2 EM pulses are data maintenance time periods.
In the related art, the bias adjustment module 102 may reuse a module originally included in the pixel circuit 10 structure, for example, the data write module is reused. However, for a circuit in which the bias adjustment module 102 and the data write module are reused with each other, the frequency of data writing (that is, the frequency of bias adjustment) limits the frequency that can be reduced to, and the time of a data maintenance stage during frequency reduction is an integer multiple of a bias adjustment signal period. The frequency that does not satisfy the integer multiple relationship cannot be implemented. For example, frequency reduction is performed in the form of long V. Although the frequency can be reduced from 60 to 40 Hz, the bias adjustment signal SP1 constituting periodicity cannot be controlled to control the bias voltage signal VD to be written at a frequency that is an integer multiple of the periodicity. As a result, the adjustment of the bias state of the drive transistor DT is affected, and the display quality of the display panel is easily affected.
In the related art, the bias adjustment module 102 may also not reuse a module originally included in the pixel circuit 10 structure. That is, an additional bias adjustment module 102 is configured. However, for the pixel circuit 10 in which the additional bias adjustment module 102 is configured, the frequency of bias adjustment also limits the frequency that can be reduced to. The bias adjustment signal SP1 is used to control the bias voltage signal VD for bias adjustment. The time of the data maintenance stage during frequency reduction is an integer multiple of the bias adjustment signal period. The frequency that does not satisfy the integer multiple relationship cannot be implemented. For example, frequency reduction is performed in the form of long_V. Although the frequency can be reduced from 60 to 40 Hz, the bias adjustment signal SP1 constituting periodicity cannot be controlled to control the bias voltage signal VD to be written at a frequency that is an integer multiple of the periodicity. It cannot be ensured that a complete frame is inserted to ensure that the bias voltage signal VD can be completely written. Further, the adjustment of the bias state of the drive transistor DT may also be affected, and the display quality is still easily affected.
When the display panel is at a high refresh frequency (that is, high-frequency driving), and when the frequency of bias adjustment is too high, apparent changes in brightness are caused, resulting in poor display at high-frequency driving. This is because the effect of bias adjustment may be equal to the product of the action of the bias voltage signal VD and the time (or the number of times) of bias adjustment. When the value of the bias voltage signal VD does not change, the increase in the number of times of bias adjustment may result in the increase in the effect of bias adjustment. When the effect of bias adjustment is greater than a preset required value, an abnormal change in brightness is prone to occur. For example, commonly, if the number of times of bias adjustment increases, the negative drift of the drive transistor DT may exceed expectation, and the brightness is abnormal.
In the related art, during frequency reduction of the panel, to ensure that a complete frame is inserted to ensure that the voltage of the bias voltage signal is completely written to ensure the display quality, for example, when the refresh frequency of the fundamental frequency display frame is 120 Hz, generally, frequency reduction is performed only in the form of frame skip. For this reason, the frequency can only be reduced to 120 Hz/Q (Q is a positive integer other than 1). Thus, the switching of the current design frequency is limited, and requirements for different high and low frequencies cannot be applied.
In the driving method provided by this embodiment, the display panel 000 to which the driving method is applied includes a fundamental frequency display frame and a low frequency display frame. The fundamental frequency display frame may be understood as a display frame under a fundamental refresh frequency before the display panel 000 performs a frequency reduction operation. The low frequency display frame may be understood as a display frame under a low refresh frequency after the display panel 000 performs the frequency reduction operation. The refresh frequency of the fundamental frequency display frame and the refresh frequency of the low frequency display frame are not limited in this embodiment. It is only required that the refresh frequency of the fundamental frequency display frame is greater than the refresh frequency of the low frequency display frame, and the low frequency display frame refers to a display frame after the display panel 000 performs the frequency reduction operation.
As shown in
As shown in
As shown in
It is to be understood that in this embodiment, description is given with reference to
Thus, if the refresh frequency of the fundamental frequency display frame illustrated in
Alternatively, if the refresh frequency of the fundamental frequency display frame illustrated in
It is to be noted that in this embodiment, the structure of the display panel 000 includes, but is not limited to, the preceding structure. For example, the display panel 000 may include other structures that can implement display functions, and the details are not repeated in this embodiment. For details, reference may be made to the structure of an organic light-emitting diode display panel in the related art for understanding.
In some embodiments, referring to
This embodiment illustrates that the display panel 000 to which the driving method is applied includes a fundamental frequency display frame and a low frequency display frame. The fundamental frequency display frame may be understood as a display frame under a fundamental refresh frequency before the display panel 000 performs the frequency reduction operation. The low frequency display frame may be understood as a display frame under a low refresh frequency after the display panel 000 performs the frequency reduction operation. As shown in
It is to be understood that in this embodiment, description is given with reference to
In some embodiments, further referring to
This embodiment illustrates that when the frequency of the fundamental frequency display frame is the first frequency, and the refresh frequency of the low frequency display frame after frequency reduction is required to be greater than or equal to half of the first frequency, the blank stage J1 of the low frequency display frame may be configured to include only the non-bias stage J11, that is, the low frequency display frame does not need bias voltage adjustment. Even if frequency reduction is performed (the refresh frequency of the low frequency display frame is less than the refresh frequency of the fundamental frequency display frame, that is, the refresh frequency of the low frequency display frame is less than the first frequency of the fundamental frequency display frame), the refresh frequency of the low frequency display frame after frequency reduction is still greater than or equal to half of the first frequency. It is to be understood that even if frequency reduction is performed, the frequency of the low frequency display frame is still in a relatively high-frequency situation (the reduction is relatively small). In this high-frequency situation, even if the brightness changes, it is relatively difficult to be detected since the changed frequency is high. In another aspect, the pulse period of the light emission control signal EM is inserted, that is, the EM pulse is inserted, so that low-frequency driving of the low frequency display frame is implemented. When the drive transistor DT is compensated in a data maintenance stage, the hysteresis of the drive transistor DT is not serious, and the caused brightness difference is smaller than the brightness difference in a low-frequency situation. Thus, bias voltage adjustment may not be performed, that is, the bias voltage signal VD is not written. The display difference perceived by a user is relatively small. It is to be understood that the display quality of the display panel 000 can still be ensured. The pulse period of the light emission control signal EM may be inserted, that is, the EM pulse may be inserted, so that the controllability of the refresh frequency of the low frequency display frame after frequency reduction may be more flexible. Thus, the display panel 000 has more switchable frequency options for frequency reduction, and various switching requirements of different high and low frequencies can be satisfied.
In some embodiments, further referring to
This embodiment illustrates that during the drive period of the display panel 000, after frequency reduction is performed on the fundamental frequency display frame to the low frequency display frame, in the K low frequency display frames included in the drive period of the display panel 000, in first K−1 low frequency display frames, that is, from the first low frequency display frame to the (K−1)th low frequency display frame, the blank stage J1 of each low frequency display frame may be configured to include only the non-bias stage J11. That is, in the K low frequency display frames included in the drive period of the display panel 000, the blank stages J1 of the first K−1 low frequency display frames include only non-bias stages J11. The first K−1 low frequency display frames do not need bias voltage adjustment. Although frequency reduction is performed, the frequency of the low frequency display frame after frequency reduction is still relatively high. For example, the frequency is greater than half of the first frequency of the fundamental frequency display frame. Even if the brightness changes, it is relatively difficult to be detected since the changed frequency is high. Thus, bias voltage adjustment may not be performed. However, after continuous multi-frame high-frequency low frequency display frames (such as K−1 low frequency display frames), the blank stage J1 of the Kth low frequency display frame may be configured to include the bias stage J12. Thus, bias voltage adjustment is performed on the last frame of the K low-frequency display frames to compensate for the display deviation caused by the absence of bias voltage adjustment in the previous frames. For example, when K is 10, the blank stages J1 of the first low frequency display frame to the ninth low frequency display frame include only non-bias stages J11, and the blank stage J1 of the tenth low frequency display frame includes the bias stage J12. Alternatively, when K is 3 (not shown in the drawings), the blank stages J1 of the first low frequency display frame to the second low frequency display frame include only non-bias stages J11, and the blank stage J1 of the third low frequency display frame includes the bias stage J12. In this manner, the display situation caused by the absence of bias voltage adjustment of more low frequency display frames is avoided. Thus, the controllability of the refresh frequency of the low frequency display frame after frequency reduction may be more flexible, and at the same time, the display quality can be ensured by performing the bias stage J12 once among multiple non-bias stages J11.
In some embodiments, as shown in
It is to be understood that
In some embodiments, referring to
This embodiment illustrates that when the frequency of the fundamental frequency display frame is the first frequency, and the refresh frequency of the low frequency display frame after frequency reduction is required to be less than half of the first frequency, the blank stage J1 of the low frequency display frame may be configured to include the bias stage J12. That is, the low frequency display frame needs bias adjustment. Frequency reduction is performed (the refresh frequency of the low frequency display frame is less than the refresh frequency of the fundamental frequency display frame, that is, the refresh frequency of the low frequency display frame is less than the first frequency of the fundamental frequency display frame), but the refresh frequency of the low frequency display frame after frequency reduction is still less than half of the first frequency. For this reason, it is to be understood that after frequency reduction is performed, the refresh frequency of the low frequency display frame is still in a relatively low-frequency situation (the reduction is relatively great). In this low-frequency situation, if the brightness changes, it is relatively easy to be detected since the changed frequency is relatively low (in a high-frequency situation, even if the brightness changes, it is relatively difficult to be detected since the changed frequency is high). Thus, the blank stage J1 needs to be configured to include the bias stage J12 for bias adjustment to alleviate the display impact caused by the brightness difference. That is, a frequency reduction operation is performed through a frame insertion method. In the bias stage J12 of the low frequency display frame, the bias voltage signal VD is written. Bias voltage adjustment is performed on the drive transistor DT. In this manner, the drive transistor DT is reverse biased. The first pole and the second pole of the drive transistor DT are inverted. Then, the degree of polarization of ions inside the drive transistor DT is weakened, and the threshold voltage of the drive transistor DT is reduced. Moreover, the impact of the hysteresis effect of the drive transistor DT on the display effect in the display panel 000 can be alleviated, thereby improving the display effect. Since the time of the inserted bias stage J12 is an integer multiple of the bias adjustment period T-SP1, the frequency of bias adjustment also does not limit the frequency that can be reduced to. Alternatively, as shown in
It is to be understood that in this embodiment, description is given with reference to
In some embodiments, referring to
The pixel circuit 10 includes at least a drive module, that is, a drive transistor DT, a data write module 103, and a light emission control module 101. The drive module, that is, the drive transistor DT, is configured to generate a drive current. The data write module 103 is configured to provide a data voltage signal Vdata for the drive module, that is, the drive transistor DT. The drive module, that is, the drive transistor DT, is electrically connected to the light emission control module 101.
A control terminal of the data write module 103 is connected to a data write control signal SP0. A first terminal of the data write module 103 is connected to the drive module, that is, the drive transistor DT. A second terminal of the data write module 103 is connected to the data voltage signal Vdata.
A control terminal of the light emission control module 101 is connected to a light emission control signal EM.
For example, the data write module 103 is reused as a bias adjustment module 102. The data write control signal SP0 is reused as a bias adjustment signal SP1.
As shown in
A second pole of the drive transistor DT is connected to a first pole of the sixth transistor T6. A second pole of the sixth transistor T6 is connected to the anode of the light-emitting element 20. The cathode of the light-emitting element 20 is connected to a second power signal Vpvee. A gate of the sixth transistor T6 is also connected to the light emission control signal EM. That is, when the gate of the first transistor T1 and the gate of the sixth transistor T6 jointly respond to the light emission control signal EM, the first transistor T1 and the sixth transistor T6 are in an on state.
A first pole of the seventh transistor T7 is connected to a second reset signal Vref2. A second pole of the seventh transistor T7 is connected to the anode of the light-emitting element 20. A gate of the seventh transistor T7 is connected to the first scan signal Scan1. That is, when the gate of the fifth transistor T5 and the gate of the seventh transistor T7 jointly respond to the first scan signal Scan1, the fifth transistor T5 and the seventh transistor T7 are in an on state. For example, the second reset signal Vref2 and the first reset signal Vref1 may be different reset voltage signals or may be the same reset voltage signal. In this embodiment, description is given with reference to the figure by using an example in which the second reset signal Vref2 and the first reset signal Vref1 are different reset voltage signals and provided by different signal lines.
A first pole of the fourth transistor T4 is connected to the gate of the drive transistor DT. A second pole of the fourth transistor T4 is connected to the second pole of the drive transistor DT. A gate of the fourth transistor T4 is connected to the data write control signal SP0, that is, the bias adjustment signal SP1. That is, when the gate of the fourth transistor T4 and the gate of the second transistor T2 may jointly respond to the data write control signal SP0, that is, the bias adjustment signal SP1, the fourth transistor T4 and the second transistor T2 are in an on state.
One end of the storage capacitor Cst is connected to the first power signal Vpvdd, and the other end of the storage capacitor Cst is connected to the gate of the drive transistor DT. The storage capacitor Cst is configured to stabilize the potential of the gate of the drive transistor DT, so that the drive transistor DT is kept turned on.
This embodiment illustrates the circuit connection structure that the pixel circuit 10 in the display panel 000 may include. The pixel circuit 10 includes multiple transistors and a storage capacitor Cst. One transistor is the drive transistor DT, and the remaining transistors are switch transistors. In this embodiment, the structure in which the pixel circuit 10 and the light-emitting element 20 are electrically connected as shown in
In an initial reset stage, the fifth transistor T5 and the seventh transistor T7 are turned on, and the remaining transistors are cut off. The potential of the first node N1 is the first reset signal Vref1. The potential of the fourth node N4 is the second reset signal Vref2. In this manner, the gate of the drive transistor DT and the anode of the light-emitting element 20 are reset.
In a data write stage and a threshold capture stage, the second transistor T2, the fourth transistor T4, and the drive transistor DT are turned on, and the remaining transistors are cut off. The potential of the second node N2 is the data voltage signal Vdata. The potential difference of the first node N1 and the third node N3 is Vdata−|Vth|. Vth is the threshold voltage of the drive transistor DT.
In a light emission stage, the first transistor T1, the sixth transistor T6, and the drive transistor DT are turned on, and the remaining transistors are cut off. The first power signal Vpvdd is transmitted to the drive transistor DT. The drive transistor DT generates a drive current to drive the light-emitting element 20 to emit light. The potential of the second node N2 is the first power signal Vpvdd. The potential of the first node N1 is Vdata−|Vth|. The potential of the third node N3 is Vpvee+Voled. Voled is the corresponding voltage on the light-emitting element 20, and the light emission current Id=k (Vgs−|Vth|)2=k (Vpvdd−Vdata−|Vth|)2. The constant k is related to the performance of the drive transistor DT.
This embodiment illustrates that the data write module 103 in the pixel circuit 10 may be reused as the bias adjustment module 102. That is, in the data write stage, the data write control signal SP0 is reused as the bias adjustment signal SP1. When the bias adjustment signal SP1 controls the first terminal and the second terminal of the bias adjustment module 102 to be conductive, the data voltage signal Vdata may be used to perform bias voltage adjustment on the drive transistor DT. Under the control of the data write control signal SP0, that is, the bias adjustment signal SP1, the data voltage signal Vdata, that is, the bias voltage signal VD, is provided to the first pole of the drive transistor DT to adjust the bias state of the drive transistor DT. In this manner, the drive transistor DT is reverse biased. The first pole and the second pole of the drive transistor DT are inverted. Then, the degree of polarization of ions inside the drive transistor DT is weakened, and the threshold voltage of the drive transistor DT is reduced. Moreover, the impact of the hysteresis effect of the drive transistor DT on the display effect in the display panel 000 can be alleviated, thereby improving the display effect. Since the data write module 103 is reused as the bias adjustment module 102, it is beneficial to reduce the number of transistors in the pixel circuit 10, and further, it is beneficial to increase the aperture ratio of the sub-pixel P in the panel, thereby saving the layout space of the panel.
In this embodiment, the bias adjustment module 102 reuses the data write module 103. The blank stage J1 of the low-frequency display frame includes the non-bias stage J11 and the bias stage J12. Even if the frequency of data writing (that is, the frequency of bias adjustment) limits the frequency that can be reduced to, the blank stage J1 may still be configured to include the bias stage J12, and the time of the bias stage J12 is an integer multiple of the bias adjustment period T-SP1. In this manner, the bias adjustment signal SP1 constituting periodicity controls the bias voltage signal VD to be written at a frequency that is an integer multiple of the periodicity. Then, the bias state of the drive transistor DT is adjusted. Thus, it is beneficial to make the frequency that can be reduced to diverse and flexible, and the display quality of the display panel can also be ensured.
Alternatively, as shown in
In some embodiments, referring to
The pixel circuit 10 includes at least a drive module, that is, a drive transistor DT, a data write module 103, a bias adjustment module 102, and a light emission control module 101. The drive module, that is, the drive transistor DT, is configured to generate a drive current. The data write module 103 is configured to provide a data voltage signal Vdata for the drive module, that is, the drive transistor DT. The drive module, that is, the drive transistor DT, is electrically connected to the light emission control module 101.
A control terminal of the bias adjustment module 102 is connected to a bias adjustment signal SP1. A first terminal of the bias adjustment module 102 is connected to the drive module, that is, the drive transistor DT. A second terminal of the bias adjustment module 102 is connected to a bias voltage signal VD. The bias adjustment signal SP1 controls the bias voltage signal VD to write into the bias adjustment module 102.
A control terminal of the data write module 103 is connected to a data write control signal SP0. A first terminal of the data write module 103 is connected to the drive module, that is, the drive transistor DT. A second terminal of the data write module 103 is connected to the data voltage signal Vdata.
A control terminal of the light emission control module 101 is connected to a light emission control signal EM.
As shown in
A gate of the drive transistor DT is connected to a first pole of the fifth transistor T5. A second pole of the fifth transistor T5 is connected to a first reset signal Vref1. A gate of the fifth transistor T5 is connected to a second scan signal S1N1. A first pole of the drive transistor DT is connected to a first pole of the first transistor T1. A second pole of the first transistor T1 is connected to a first power signal Vpvdd. A gate of the first transistor T1 is connected to the light emission control signal EM. The first pole of the drive transistor DT is also connected to a first pole of the second transistor T2. A second pole of the second transistor T2 is connected to the data voltage signal Vdata. A gate of the second transistor T2 is connected to the data write control signal SP0. The first pole of the drive transistor DT is also connected to a first pole of the eighth transistor T8. A second pole of the eighth transistor T8 is connected to the bias voltage signal VD. A gate of the eighth transistor T8 is connected to the bias adjustment signal SP1.
A second pole of the drive transistor DT is connected to a first pole of the sixth transistor T6. A second pole of the sixth transistor T6 is connected to the anode of the light-emitting element 20. The cathode of the light-emitting element 20 is connected to a second power signal Vpvee. A gate of the sixth transistor T6 is also connected to the light emission control signal EM. That is, when the gate of the first transistor T1 and the gate of the sixth transistor T6 jointly respond to the light emission control signal EM, the first transistor T1 and the sixth transistor T6 are in an on state.
A first pole of the seventh transistor T7 is connected to a second reset signal Vref2. A second pole of the seventh transistor T7 is connected to the anode of the light-emitting element 20. A gate of the seventh transistor T7 is connected to a first scan signal Scan1. That is, when the gate of the seventh transistor T7 responds to the first scan signal Scan1, the seventh transistor T7 is in an on state. For example, the second reset signal Vref2 and the first reset signal Vref1 may be different reset voltage signals or may be the same reset voltage signal. In this embodiment, description is given with reference to the figure by using an example in which the second reset signal Vref2 and the first reset signal Vref1 are different reset voltage signals and provided by different signal lines.
A first pole of the fourth transistor T4 is connected to the gate of the drive transistor DT. A second pole of the fourth transistor T4 is connected to the second pole of the drive transistor DT. A gate of the fourth transistor T4 is connected to a third scan signal S2N1. That is, when the gate of the fourth transistor T4 responds to the third scan signal S2N1, the fourth transistor T4 is in an on state.
One end of the storage capacitor Cst is connected to the first power signal Vpvdd, and the other end of the storage capacitor Cst is connected to the gate of the drive transistor DT. The storage capacitor Cst is configured to stabilize the potential of the gate of the drive transistor DT, so that the drive transistor DT is kept turned on.
This embodiment illustrates another circuit connection structure that the pixel circuit 10 in the display panel 000 may include. The data write module 103 and the bias adjustment module 102 in the pixel circuit 10 may be independently configured. That is, in the data write stage, when the data write control signal SP0 controls the first terminal and the second terminal of the data write module 103 to be conductive, the data voltage signal Vdata is written into the pixel circuit 10. When the bias adjustment signal SP1 controls the first terminal and the second terminal of the bias adjustment module 102 to be conductive, the bias voltage signal VD is written into the pixel circuit 10 to perform bias voltage adjustment on the drive transistor DT. In this manner, the drive transistor DT is reverse biased. The first pole and the second pole of the drive transistor DT are inverted. Then, the degree of polarization of ions inside the drive transistor DT is weakened, and the threshold voltage of the drive transistor DT is reduced. Moreover, the impact of the hysteresis effect of the drive transistor DT on the display effect in the display panel 000 can be alleviated, thereby improving the display effect. In this embodiment, when the bias adjustment module 102 and the data write module 103 are not reused with each other, the frequency of bias adjustment also does not limit the frequency that can be reduced to. The blank stage J1 may still be configured to include the non-bias stage J11 and the bias stage J12, and the time of the bias stage J12 is an integer multiple of the bias adjustment period T-SP1. The bias adjustment signal SP1 constituting periodicity controls the bias voltage signal VD to be written at a frequency that is an integer multiple of the periodicity. Then, the bias state of the drive transistor DT is adjusted. In this manner, the display quality of the display panel is ensured, and at the same time, the frequency that can be reduced to may be diverse and flexible.
As shown in
In
In
In
It is to be understood that in some other embodiments, the blank stage J1 illustrated in
In some embodiments, as shown in
The refresh frequency of the fundamental frequency display frame includes A Hz. The period of the fundamental frequency display frame is 1/A seconds. A is a positive integer. The time of the fundamental frequency scan stage J0 included in the low frequency display frame is 1/A seconds. The time of the fundamental frequency scan stage J0 is N times greater than the light emission control period T-EM. The time of the light emission control period T-EM is 1/NA seconds. The time of the non-bias stage J11 included in the low frequency display frame is L times greater than the light emission control period T-EM. L is not an integer multiple of M. The time of the non-bias stage J11 included in the low frequency display frame is L/NA seconds. It can be seen that the period of the low frequency display frame is the sum of the time of the fundamental frequency scan stage J0 and the time of the non-bias stage J11 of the blank stage J1, that is, 1/A seconds+L/NA seconds. The period of the low frequency display frame is calculated to be
seconds. The refresh frequency of the low frequency display frame is
In some embodiments, if the refresh frequency of the fundamental frequency display frame is 120 Hz, the period of the fundamental frequency display frame is 1/120 seconds. As shown in
The time of the non-bias stage J11 included in the low frequency display frame is the light emission control period T-EM multiplied by 1, that is, L is 1. The time of the non-bias stage J11 included in the low frequency display frame is 1/480 seconds. It can be seen that the period of the low frequency display frame is the sum of the time ( 1/120 seconds) of the fundamental frequency scan stage J0 and the time ( 1/480 seconds) of the non-bias stage J11 of the blank stage J1, that is, 1/120 seconds+ 1/480 seconds, that is, 1/96 seconds. The refresh frequency of the low frequency display frame is 96 Hz.
In this embodiment, the blank stage J1 of the low frequency display frame is configured to include the non-bias stage J11, so that the refresh frequency of the display panel 000 can be reduced from 120 Hz of the fundamental frequency display frame to 96 Hz of the low frequency display frame. Then, the quotient of the refresh frequency (120 Hz) of the fundamental frequency display frame and the refresh frequency (96 Hz) of the low frequency display frame is not a positive integer other than 1. That is, the refresh frequency of the fundamental frequency display frame is not an integer multiple of the refresh frequency of the low frequency display frame. Thus, the display panel 000 has more switchable frequency options for frequency reduction, and various switching requirements of different high and low frequencies can be satisfied.
In some embodiments, if the refresh frequency of the fundamental frequency display frame is 120 Hz, the period of the fundamental frequency display frame is 1/120 seconds. As shown in
The time of the non-bias stage J11 included in the low frequency display frame is 2 times greater than the light emission control period T-EM, that is, L is 2. The time of the non-bias stage J11 included in the low frequency display frame is 2/720 seconds. It can be seen that the period of the low frequency display frame is the sum of the time ( 1/120 seconds) of the fundamental frequency scan stage J0 and the time ( 2/720 seconds) of the non-bias stage J11 of the blank stage J1, that is, 1/120 seconds+ 2/720 seconds, that is, 1/90 seconds. The refresh frequency of the low frequency display frame is 90 Hz.
In this embodiment, the blank stage J1 of the low frequency display frame is configured to include the non-bias stage J11, so that the refresh frequency of the display panel 000 can be reduced from 120 Hz of the fundamental frequency display frame to 90 Hz of the low frequency display frame. Then, the quotient of the refresh frequency (120 Hz) of the fundamental frequency display frame and the refresh frequency (90 Hz) of the low frequency display frame is not a positive integer other than 1. That is, the refresh frequency of the fundamental frequency display frame is not an integer multiple of the refresh frequency of the low frequency display frame. Thus, the display panel 000 has more switchable frequency options for frequency reduction, and various switching requirements of different high and low frequencies can be satisfied.
In some embodiments, if the refresh frequency of the fundamental frequency display frame is 120 Hz, the period of the fundamental frequency display frame is 1/120 seconds. As shown in
The time of the non-bias stage J11 included in the low frequency display frame is the light emission control period T-EM multiplied by 1, that is, L is 1. The time of the non-bias stage J11 included in the low frequency display frame is 1/720 seconds. It can be seen that the period of the low frequency display frame is the sum of the time ( 1/120 seconds) of the fundamental frequency scan stage J0 and the time ( 1/720 seconds) of the non-bias stage J11 of the blank stage J1, that is, 1/120 seconds+ 1/720 seconds, that is, 1/102.86 seconds. The refresh frequency of the low frequency display frame is 102.86 Hz.
In this embodiment, the blank stage J1 of the low frequency display frame is configured to include the non-bias stage J11, so that the refresh frequency of the display panel 000 can be reduced from 120 Hz of the fundamental frequency display frame to 102.86 Hz of the low frequency display frame. Then, the quotient of the refresh frequency (120 Hz) of the fundamental frequency display frame and the refresh frequency (102.86 Hz) of the low frequency display frame is not a positive integer other than 1. That is, the refresh frequency of the fundamental frequency display frame is not an integer multiple of the refresh frequency of the low frequency display frame. Thus, the display panel 000 has more switchable frequency options for frequency reduction, and various switching requirements of different high and low frequencies can be satisfied.
It is to be understood that
In some embodiments, if the refresh frequency of the fundamental frequency display frame is 120 Hz, the period of the fundamental frequency display frame is 1/120 seconds. For example, if 32 light emission control periods T-EM are included in the period of the fundamental frequency display frame, the light emission control period T-EM is one thirty-second multiplied by 1/120 seconds, that is, 1/3840 seconds. The time of the fundamental frequency scan stage J0 is 32 times greater than the light emission control period T-EM, that is, N is 32. The time of the fundamental frequency scan stage J0 included in the low frequency display frame is 32 times greater than 1/3840 seconds, that is, 1/120 seconds.
The time of the non-bias stage J11 included in the low frequency display frame is 2 times greater than the light emission control period T-EM, that is, L is 2. The time of the non-bias stage J11 included in the low frequency display frame is 2/3840 seconds. It can be seen that the period of the low frequency display frame is the sum of the time ( 1/120 seconds) of the fundamental frequency scan stage J0 and the time ( 2/3840 seconds) of the non-bias stage J11 of the blank stage J1, that is, 1/120 seconds+ 2/3840 seconds, that is, 1/112.94 seconds. The refresh frequency of the low frequency display frame is 112.94 Hz.
Alternatively, the time of the non-bias stage J11 included in the low frequency display frame is 4 times greater than the light emission control period T-EM, that is, L is 4. The time of the non-bias stage J11 included in the low frequency display frame is 4/3840 seconds. It can be seen that the period of the low frequency display frame is the sum of the time ( 1/120 seconds) of the fundamental frequency scan stage J0 and the time ( 4/3840 seconds) of the non-bias stage J11 of the blank stage J1, that is, 1/120 seconds+ 4/3840 seconds, that is, 1/106.67 seconds. The refresh frequency of the low frequency display frame is 106.67 Hz.
Alternatively, the time of the non-bias stage J11 included in the low frequency display frame is 8 times greater than the light emission control period T-EM, that is, L is 8. The time of the non-bias stage J11 included in the low frequency display frame is 8/3840 seconds. It can be seen that the period of the low frequency display frame is the sum of the time ( 1/120 seconds) of the fundamental frequency scan stage J0 and the time ( 8/3840 seconds) of the non-bias stage J11 of the blank stage J1, that is, 1/120 seconds+ 8/3840 seconds, that is, 1/96 seconds. The refresh frequency of the low frequency display frame is 96 Hz.
This embodiment illustrates that the blank stage J1 of the low frequency display frame is configured to include the non-bias stage J11, so that another method in which the refresh frequency of the display panel 000 can be reduced from 120 Hz of the fundamental frequency display frame to 96 Hz of the low frequency display frame, 106.67 Hz of the low frequency display frame, or 112.94 Hz of the low frequency display frame is implemented. Then, the quotient of the refresh frequency of the fundamental frequency display frame and the refresh frequency of the low frequency display frame is not a positive integer other than 1. That is, the refresh frequency of the fundamental frequency display frame is not an integer multiple of the refresh frequency of the low frequency display frame. Thus, the display panel 000 has more switchable frequency options for frequency reduction, and various switching requirements of different high and low frequencies can be satisfied. Moreover, in this embodiment, L is set to 2, 4, 6, or 8, so that the refresh frequency of the fundamental frequency display frame is reduced to relatively high refresh frequencies of more low frequency display frames. In this manner, more relatively high refresh frequencies in the low frequency display frame are implemented. Under the relatively high refresh frequency of a low frequency display frame, frequency reduction requirements are satisfied, and at the same time, the requirement for bias adjustment is reduced.
In some embodiments, referring to
In some embodiments, further referring to
In this embodiment, the fundamental frequency display frame of the display panel 000 is configured to include at least two different types of refresh frequency. For example, the fundamental frequency display frame of the display panel 000 includes at least a first fundamental frequency display frame and a second fundamental frequency display frame. The refresh frequency of the first fundamental frequency display frame is different from the refresh frequency of the second fundamental frequency display frame. Thus, in fundamental frequency display frames of different refresh frequencies, the blank stage J1 is configured, so that the display panel 000 has more switchable frequency options after frequency reduction, and more switching requirements of different high and low frequencies can be satisfied.
For example, it is assumed that the refresh frequency of the first fundamental frequency display frame is 120 Hz, and the refresh frequency of the second fundamental frequency display frame is 144 Hz.
The display panel 000 is under the refresh frequency of the first fundamental frequency display frame, that is, under 120 Hz, and the frequency reduction method in the preceding embodiments may be adopted to implement refresh frequencies of multiple low frequency display frames. As shown in the preceding embodiments, the refresh frequency of the first fundamental frequency display frame before frequency reduction is 120 Hz, and the refresh frequency of the low frequency display frame after frequency reduction may include 80 Hz, 90 Hz, 96 Hz, and 102.86 Hz. The display panel 000 is under the refresh frequency of the second fundamental frequency display frame, that is, under 144 Hz, and the frequency reduction method that is the same as the method in the embodiment of
In the display panel 000 of this embodiment, when the fundamental frequency display frame includes a first fundamental frequency display frame and a second fundamental frequency display frame having different refresh frequencies, frequency reduction may be performed multiple times by using stepping in which N is 6, and L is 2. For example, for the display panel 000, the refresh frequency of the first fundamental frequency display frame is 120 Hz, N may be 6, and L may be 2; and then the refresh frequency of the first low frequency display frame after frequency reduction is 90 Hz. N may be 6, and L may be 4; and then the refresh frequency of the second low frequency display frame after frequency reduction is 72 Hz. N may be 6, and L may be 6; and then the refresh frequency of the third low frequency display frame after frequency reduction is 60 Hz. For the display panel 000, the refresh frequency of the second fundamental frequency display frame is 144 Hz, N may be 6, and L may be 2; and then the refresh frequency of the first low frequency display frame after frequency reduction is 108 Hz. N may be 6, and L may be 4; and then the refresh frequency of the second low frequency display frame after frequency reduction is 86.4 Hz. N may be 6, and L may be 6; and then the refresh frequency of the third low frequency display frame after frequency reduction is 72 Hz.
It can be seen from the preceding frequency reduction process that in the first fundamental frequency display frame (for example, when the refresh frequency is 120 Hz), the refresh frequency of the low frequency display frame of the display panel 000 includes a second frequency (for example, 72 Hz). In the second fundamental frequency display frame (for example, when the refresh frequency is 144 Hz), the refresh frequency of the low frequency display frame of the display panel 000 also includes the second frequency (for example, 72 Hz). When the display panel is at the first fundamental frequency display frame, if the refresh frequency of the low frequency display frame is required to be the second frequency (for example, 72 Hz), the fundamental frequency display frame of the display panel 000 maintains as the first fundamental frequency display frame. That is, the second frequency of the low frequency display frame after frequency reduction may be implemented by frequency reduction in the first fundamental frequency display frame or by frequency reduction in the second fundamental frequency display frame, but if the display panel 000 is in the first fundamental frequency display frame at this time, the display panel 000 does not switch the fundamental frequency display frame. The previous frame is the first fundamental frequency display frame, the next fundamental frequency display frame that needs frequency reduction still maintains the first fundamental frequency display frame, and frequency reduction is performed on the next fundamental frequency display frame to the low frequency display frame of the second frequency. For example, the low frequency display frame of this frame needs to implement 72 Hz, and which 72 Hz to use is selected according to the fundamental frequency of the previous frame. If the previous frame is the first fundamental frequency display frame of 120 Hz, in the first fundamental frequency display frame, the frequency is directly reduced to 72 Hz. If the previous frame is the first fundamental frequency display frame of 144 Hz, in the first fundamental frequency display frame, the frequency is directly reduced to 72 Hz. No fundamental frequency switching is required. In this manner, the fundamental frequency switching of the display panel can be avoided, and it is beneficial to reduce the power consumption of the panel.
In this embodiment, when the fundamental frequency display frame of the display panel 000 includes a first fundamental frequency display frame and a second fundamental frequency display frame having different refresh frequencies, in the first fundamental frequency display frame, the refresh frequency of the low frequency display frame of the display panel 000 includes a third frequency. In the second fundamental frequency display frame, the refresh frequency of the low frequency display frame of the display panel 000 also includes the third frequency. The difference value between the third frequency and the refresh frequency of the first fundamental frequency display frame is less than the difference value between the third frequency and the refresh frequency of the second fundamental frequency display frame. When the display panel 000 is switched to the first fundamental frequency display frame, the refresh frequency of the low frequency display frame is set to be the third frequency. For example, the low frequency display frame after the first frequency reduction needs to implement 72 Hz, and the fundamental frequency display frame having a small difference value from the 72 Hz may be selected. For example, the refresh frequency of the first fundamental frequency display frame is 120 Hz, and the refresh frequency of the second fundamental frequency display frame is 144 Hz. The difference value between 120 Hz and 72 Hz is smaller than the difference value between 144 Hz and 72 Hz. After the display panel 000 is switched to the first fundamental frequency display frame, the frequency is reduced to the low frequency display frame of 72 Hz. In this manner, the power consumption during the frequency reduction process can be reduced, and the waste of the power consumption of the panel caused by excessive frequency reduction can be avoided.
In some embodiments, referring to
As can be seen from the preceding embodiments, the driving method of a display panel and the display device provided by the present disclosure at least implement the beneficial effects below.
The driving method provided by the present disclosure may be applied to a display panel including an electroluminescent device such as an organic light-emitting diode display panel or a micro light-emitting diode display panel. A sub-pixel of the display panel includes a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit is configured to transmit a light-emitting drive current to the light-emitting element under the action of the signal of a drive signal line on the display panel to provide the drive current to the light-emitting element to enable the light-emitting element to emit light. In the driving method provided by the present disclosure, the display panel to which the driving method is applied includes a fundamental frequency display frame and a low frequency display frame. The fundamental frequency display frame may be understood as a display frame under a fundamental refresh frequency before the display panel performs the frequency reduction operation. The low frequency display frame may be understood as a display frame under a low refresh frequency after the display panel performs the frequency reduction operation. The refresh frequency of the fundamental frequency display frame is greater than the refresh frequency of the low frequency display frame. In the fundamental frequency display frame, the light emission control signal includes the light emission control period. The light emission control period may be understood as the time occupied by one pulse period of the light emission control signal. The bias adjustment signal includes the bias adjustment period. The bias adjustment period may be understood as the time occupied by one pulse period of the bias adjustment signal. The bias adjustment period is M times greater than the light emission control period. The fundamental frequency display frame includes the fundamental frequency scan stage. The time of the fundamental frequency scan stage is N times greater than the light emission control period. The time of the fundamental frequency scan stage may be understood as the time of scanning from the first row of sub-pixels to the last row of sub-pixels in the driving process of the display panel. After the frequency reduction operation is performed on the display panel, the low frequency display frame may include a fundamental frequency scan stage and a blank stage. The blank stage includes at least the non-bias stage. The time of the non-bias stage is L times greater than the light emission control period. L is not an integer multiple of M. That is, under low-frequency driving after frequency reduction, bias voltage adjustment is not performed on the inserted blank stage. The bias adjustment signal is not a valid pulse signal. The bias adjustment signal controls the first terminal and the second terminal of a bias adjustment module not to be conductive. The bias voltage signal is not written. The bias adjustment module does not perform bias adjustment on the drive transistor in the pixel circuit. In this manner, the frequency of bias adjustment may be prevented from limiting the frequency that can be reduced to, thereby making the refresh frequency of the low frequency display frame more flexible. When the display panel of the present disclosure is in the low frequency display frame, the blank stage includes the non-bias stage. Bias voltage adjustment is not performed on the non-bias stage. The pulse period of the light emission control signal is inserted, that is, the EM pulse is inserted, so that low-frequency driving of the low frequency display frame is implemented. Then, the quotient of the refresh frequency of the fundamental frequency display frame and the refresh frequency of the low frequency display frame is not a positive integer other than 1. That is, the refresh frequency of the fundamental frequency display frame is not an integer multiple of the refresh frequency of the low frequency display frame. Thus, the display panel has more switchable frequency options for frequency reduction, and various switching requirements of different high and low frequencies can be satisfied.
While some embodiments of the present disclosure has been described in detail through examples, it should be understood by those skilled in the art that the preceding examples are for illustration only and are not intended to limit the scope of the present disclosure. It should be understood by those skilled in the art that modifications may be made to the preceding embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202310990777.6 | Aug 2023 | CN | national |
