Driving method of plasma display panel

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates to a driving method of a matrix display system plasma display panel.

[0003] 2. Description of Related Art

[0004] An AC (alternating current discharge) type plasma display is known as one of display panels of a matrix display scheme.

[0005] Such a plasma display panel includes a plurality of row electrodes each bearing a role of a display line, and a plurality of column electrodes so arranged respectively as to intersect the row electrodes. These row and column electrodes are arranged in such a way as to oppose one another while interposing therebetween a discharge space filled with a discharge gas. Discharge cells serving as pixels are formed at the points of intersection between a row electrode pair and the column electrodes inclusive of the discharge space. Since the discharge cell emits light by utilizing a discharge phenomenon, it can assume only two states, that is, a “light emission” state and a “light non-emission” state. In other words, this plasma display device can express luminance of only two gradations, i.e., the lowest luminance (light non-emission state) and the highest luminance (light emission state). Therefore, gradation driving using a sub-field method is executed in order to accomplish luminance display of an intermediate tone corresponding to input image signals for the plasma display panel comprising such discharge cells.

[0006] In the driving system using the sub-field method, a display period of one field (frame) is constituted by a plurality of sub-fields. In each sub-field, each of discharge cells is set to either a “light emission cell” state or a “light non-emission cell” state in accordance with pixel data for each pixel on the basis of an input image signal. Only the discharge cell under the “light emission cell” state is allowed to discharge (with light emission) a number of times (for a time) corresponding to weighting of its sub-field, for each sub-field. In this instance, various intermediate luminance can be visually sensed stepwise in accordance with the sum of the number of light emissions made inside the one-field (frame) display period.

[0007] In recent years, display apparatus having the plasma display panel mounted thereto have contemplated to increase the number of gradations by combining gradation driving using the sub-field method described above with a multi-gradation processing such as a dither processing.

[0008] In such a dither processing, four discharge cells, for example, that are adjacent to one another among the discharge cells arranged in a matrix form are grasped as one discharge cell block. Sequentially, four dither coeffients having different values each are allotted to each of the four discharge cells inside the discharge cell block. Here, a dither coefficient allotted as described above is added to each pixel data corresponding to each discharge cell inside the discharge cell block. Only the high-order bit of the addition result is grasped as new pixel data, and gradation driving described above is executed. According to such a dither processing, new intermediate luminance can be visually sensed depending on the combination of the light emission (or light non-emission) state of the four discharge cells inside the discharge cell block, and the number of gradations can be virtually increased.

[0009] According to the multi-gradation method described above, however, a process for adding the dither coefficient to the pixel data is necessary. Therefore, a luminance difference between the adjacent discharge cells greatly fluctuates depending on the value of original pixel data with the result that display quality is likely to drop, too.

SUMMARY OF THE INVENTION

[0010] In view of the problems described above, the present invention aims at providing a driving method of a plasma display panel capable of executing a dither processing without lowering display quality.

[0011] In a driving method of a plasma display panel for driving gradation-wise a plasma display panel having a plurality of discharge cells each arranged in matrix and bearing a role of a pixel by constituting one field of input image signals by a plurality of sub-fields, a driving method of a plasma display panel according to the present invention is characterized in that when each of the discharge cells is set to a light emission cell state or a light non-emission cell state in accordance with the input image signal in each of the sub-fields and only the discharge cell under the light emission cell state is caused to emit light the number of light emissions allotted in accordance with weighting of the sub-field, while the number of light emissions to be allotted in accordance with weighting of the sub-field is rendered different for each of the discharge cells inside a discharge cell block consisting of a plurality of discharge cells adjacent to one another.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012]
FIG. 1 is a schematic diagram showing the construction of a plasma display device for driving a plasma display panel based on an intermediate gradation display method according to the present invention;

[0013]
FIG. 2 is a diagram showing an internal construction of a data conversion circuit 30;

[0014]
FIG. 3 is a diagram showing an internal construction of a first data conversion circuit 32 in the data conversion circuit 30;

[0015]
FIGS. 4A through 4D are diagrams showing first to fourth conversion tables by data converters 321 to 324, respectively;

[0016]
FIG. 5 is a data conversion table by a second data conversion circuit 34 and a light emission driving pattern inside one-field display period;

[0017]
FIG. 6 is a diagram showing an example of a light emission driving format on the basis of a driving method according to the present invention;

[0018]
FIG. 7 shows various driving pulses applied to PDP 10 and their application timing when a selective erase address method is employed;

[0019]
FIG. 8 shows light emission driving formats A to D allocated to discharge cells inside a discharge cell block;

[0020]
FIG. 9 shows correspondence between a discharge cell block and a light emission driving format allocated to each discharge cell inside the discharge cell block;

[0021]
FIGS. 10A through 10D are diagrams showing light emission luminance acquired for pixel data PD for each light emission driving format A to D;

[0022]
FIG. 11 a diagram showing pixel data PD corresponding to each luminance level “0” to “11” and light emission luminance of each discharge cell inside a discharge cell block;

[0023]
FIG. 12 is a diagram showing the correspondence between pixel data PD and a light emission luminance level visually sensed in a discharge cell block unit;

[0024]
FIG. 13 is a diagram showing an operation example when allotment of a light emission driving format A to D for each discharge cell is changed in each one-field display period;

[0025]
FIG. 14 is a diagram showing various driving pulses applied to PDP 10 and their application timing when a selective write address method is employed; and

[0026]
FIG. 15 is a data conversion table used in a second data conversion circuit 34 and a light emission driving pattern in one-field display period when a selective write address method is employed.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] Hereinafter, preferred embodiments of the present invention will be explained with reference to the drawings.

[0028]
FIG. 1 shows a schematic construction of a plasma display device for driving gradation-wise a plasma display panel in accordance with a driving method of the present invention.

[0029] Referring to FIG. 1, a PDP 10 as a plasma display panel is shown equipped with m column electrodes D1 to Dm, and n row electrodes X1 to Xn and n row electrodes Y1, to Yn, so arranged as to cross the column electrodes, respectively. These row electrodes X1 to Xn and Y1 to Yn bear first to nth display lines of the PDP 10 in the form of pairs of row electrodes Xi(1≦i≦n) and Yi(1≦i≦n)1 respectively. A discharge space filled with a discharge gas is defined between the column electrode D and the row electrodes X and Y. A discharge cell as a pixel is formed at each intersection between each row electrode pair and each column electrode inclusive of this discharge space. In other words, (n×m) discharge cells corresponding to the first row/first column to nth row/mth column are formed in the PDP 10.

[0030] An A/D converter 1 samples an input analog image signal, converts the signal to 4-bit pixel data PD, for example, corresponding to each pixel and supplies this pixel data to a data conversion circuit 30.

[0031]
FIG. 2 shows an internal construction of such a data conversion circuit 30.

[0032] Referring to FIG. 2, a first data conversion circuit 32 converts the above-mentioned pixel data PD capable of expressing a luminance range of “0” to “15” by four bits to luminance suppression pixel data PDL in which luminance is suppressed to a luminance range of “0” to “4” by three bits.

[0033]
FIG. 3 shows an internal construction of the first data conversion circuit 32 described above.

[0034] Referring to FIG. 3, a data converter 321 converts the four-bit pixel data PD described above to three-bit converted pixel data Da in accordance with a first conversion table shown in FIG. 4A, and supplies this pixel data Da to a selector 320. A data converter 322 converts the four-bit pixel data PD described above to three-bit converted pixel data Db in accordance with a second conversion table shown in FIG. 4B, and supplies the pixel data Db to the selector 320. A data converter 323 converts the four-bit pixel data PD described above to three-bit converted pixel data Dc in accordance with a third conversion table shown in FIG. 4C, and supplies the pixel data Dc to the selector 320. A data converter 324 converts the four-bit pixel data PD described above to three-bit converted pixel data Dd in accordance with a fourth conversion table shown in FIG. 4D, and supplies the pixel data Dd to the selector 320. The selector 320 alternatively selects one of the converted pixel data Da to Dd designated by a conversion table designation signal SS and outputs the selected data as the luminance suppression pixel data PDL. Incidentally, the conversion table designation signal SS is supplied from a driving control circuit 2. The driving control circuit 2 supplies to the selector 320 the conversion table designation signal SS, that is to selectively output the converted pixel data Da obtained by the first conversion table as the luminance suppression pixel data PDL for the pixel data PD corresponding to the discharge cell belonging to an odd-numbered row/odd-numbered column. The driving control circuit 2 supplies to the selector 320 the conversion table designation signal SS, that is to selectively output the converted pixel data Db obtained by the second conversion table as the luminance suppression pixel data PDL, for the pixel data PD corresponding to the discharge cell belonging to an odd-numbered row/even-numbered column. The driving control circuit 2 supplies to the selector 320 the conversion table designation signal SS, that is to selectively output the converted pixel data Dc obtained by the third conversion table as the luminance suppression pixel data PDL, for the pixel data PD corresponding to the discharge cell belonging to an even-numbered row/odd-numbered column. The driving control circuit 2 supplies to the selector 320 the conversion table designation signal SS, that is to selectively output the converted pixel data Dd obtained by the fourth conversion table as the luminance suppression pixel data PDL, for the pixel data PD corresponding to the discharge cell belonging to an even-numbered row/even-numbered column.

[0035] In other words, when the pixel data PD corresponds to the discharge cell arranged in the odd-numbered row/odd-numbered column, the first data conversion circuit 32 converts this pixel data PD to three-bit luminance suppression pixel data PDL in accordance with the first conversion table shown in FIG. 4A. When the pixel data PD corresponds to the discharge cell arranged in the odd-numbered row/even-numbered column, the first data conversion circuit 32 converts this pixel data PD to three-bit luminance suppression pixel data PDL in accordance with the second conversion table shown in FIG. 4B. When the pixel data PD corresponds to the discharge cell arranged in the even-numbered row/odd-numbered column, the first data conversion circuit 32 converts this pixel data PD to three-bit luminance suppression pixel data PDL in accordance with the third conversion table shown in FIG. 4C. When the pixel data PD corresponds to the discharge cell arranged in the even-numbered row/even-numbered column, the first data conversion circuit 32 converts this pixel data PD to three-bit luminance suppression pixel data PDL in accordance with the fourth conversion table shown in FIG. 4C.

[0036] A second data conversion circuit 34 shown in FIG. 2 converts the luminance suppression data PDL to four-bit pixel driving data GD in accordance with a conversion table shown in FIG. 5, and supplies the data GD to a memory 4.

[0037] The memory 4 serially writes the pixel driving data GD described above in accordance with a write signal supplied from the driving control circuit 2. The memory 4 executes the following read operation whenever the write operation of (n×m) data of one display screen, that is, the data from the pixel driving data GD11 corresponding to the first row/first column to the pixel driving data GDnm corresponding to the nth row/mth column, is completed.

[0038] First, the memory 4 grasps the first bit as the lowermost bit of each pixel driving data GD11 to GDnm as the pixel driving data bit DB111 to DB1nm, reads the pixel driving data bits for one display line and supplies them to an address driver 6. Next, the memory 4 grasps the second bit as the bit of each pixel driving data GD11 to GDnm as the pixel driving data bit DB211 to DB2nm, reads the pixel driving data bits for one display line and supplies them to the address driver 6. The memory 4 then grasps the third bit of each pixel driving data GD11 to GDnm as the pixel driving data bit DB311 to DB3nm, reads the pixel driving data bits for one display line and supplies them to the address driver 6. Further, the memory 4 grasps the fourth bit of each pixel driving data GD11 to GDnm as the pixel driving data bit DB411 to DB4nm, reads the pixel driving data bits for one display line and supplies them to the address driver 6.

[0039] Incidentally, the memory 4 executes the read operation of each pixel driving data bit DB1 to DB4 described above in such a fashion as to correspond to each sub-field SF1 to SF4 of a light emission driving format (to be described later) shown in FIG. 6. The memory 4 executes the read operation of the pixel driving data bit DB1 in the sub-field SF1, the pixel driving data bit DB2 in SF2, the pixel driving data bit DB3 in SF3 and the pixel driving data bit DB4 in SF4.

[0040] The driving control circuit 2 generates various timing signals for driving gradation-wise PDP 10 in accordance with a light emission driving format shown in FIG. 6, and supplies these signals to each of the address driver 6, the first sustain driver 7 and the second sustain driver 8.

[0041] Incidentally, in the light emission driving format shown in FIG. 6, a display period of one field (frame) comprises four sub-fields SF1 to SF4 as described above. Inside each sub-field, a simultaneous reset step R, a pixel data write step W, first to fourth light emission sustain steps I1 to I4, first to third selective simultaneous erase steps S1 to S3 and a second erase step E are executed respectively.

[0042]
FIG. 7 shows various driving pulses that the address driver 6, the first sustain driver 7 and the second sustain driver 8 apply to the PDP 10 in accordance with various timing signals supplied from the driving control circuit 2, and their application timing.

[0043] Referring to FIG. 7, in the simultaneous reset step R to be executed at the leading part of each sub-field, the first sustain driver 7 generates a reset pulse RPx of a negative polarity and applies the reset pulse to the row electrodes X1 to Xn. The second sustain driver 8 generates a reset pulse RPy of a positive polarity and applies the reset pulse to the row electrodes Y1 to Yn simultaneously with the application of the reset pulse RPx. Reset discharge is induced inside all the discharge cells of the PDP 10 in response to the simultaneous application of these reset pulses RPx and RPy, and a wall charge is formed inside each discharge cell. In consequence, all the discharge cells are initialized to a state of “light emission cell”.

[0044] After such a simultaneous reset step R is completed, the pixel data write step W is executed.

[0045] In the pixel data write step W, the address driver 6 generates a pixel data pulse having a pulse voltage corresponding to the pixel driving data bit DB supplied from the memory 4. Since the pixel driving data bit DB1 is supplied from the memory 4 in the sub-field SF1, for example, the address driver 6 generates the pixel data pulse having a pulse voltage corresponding to a logic level of the pixel driving data bit DB1. Since the pixel driving data bit DB2 is supplied from the memory 4 in the sub-field SF2, the address driver 6 generates the pixel data pulse having a pulse voltage corresponding to a logic level of the pixel driving data bit-DB2. Incidentally, the address driver 6 generates the pixel data pulse of a high voltage when the logic level of the pixel driving data bit DB is “1” and a pixel data pulse of a low voltage (0 V) when the logic level is “0”. The address driver 6 serially applies the pixel data pulses generated in this way to the column electrodes D1 to Dm as pixel data pulse group DP1 to DPn that is grouped for each display line, as shown in FIG. 7.

[0046] In the pixel data write step W, the second sustain driver 8 generates a scan pulse SP of a negative polarity at the application timing of the pixel data pulse group DP1 to DPn, and serially applies the scan pulse SP to the row electrodes Y1 to Yn as shown in FIG. 7. Here, discharge (selective erase discharge) occurs in only the discharge cell at the intersection between the display line to which the scan pulse SP is applied and the “column” to which the pixel data pulse of a high voltage is applied. Such selective erase discharge extinguishes the wall charge formed inside the discharge cell, and the discharge cell shifts to the state of “light non-emission cell”. On the other hand, the selective erase discharge does not occur in the discharge cells to which the scan pulse SP described above is applied but to which the pixel data pulse of a low voltage is applied. In consequence, these discharge cells maintain the state in which they are initialized by the simultaneous reset step R, that is, the “light emission cell” state. In other words, the pixel data write step W sets each discharge cell either to the “light emission cell” state or the “light non-emission cell” state in accordance with the pixel data based on the input image signal.

[0047] After the pixel data write step W is completed, the first light emission sustain step I1 is executed as shown in FIG. 7.

[0048] In the first light emission sustain step I1, the first sustain driver 7 and the second sustain driver 8 alternately apply the sustain pulses IPx and IPy of the positive polarity to the row electrodes X1 to Xn and Y1 to Yn, respectively, as shown in FIG. 7. In this instance, the number of times (or the period) of the application of the sustain pulse IP repeatedly applied in each first light emission sustain step I1 of each sub-field SF1 to SF4 is given as follows when the number of times in the first light emission sustain step I1 of the sub-field SF1 is 4:

[0049] SF1: 4

[0050] SF2: 36

[0051] SF3: 68

[0052] SF4: 100

[0053] As a result of the operation described above, only the discharge cells in which the wall charge remains, that is, only the discharge cells which are under the “light emission cell” state, execute sustain discharge whenever the sustain pulses IPx and IPy described above are applied, and sustain the light emission state by the sustain discharge the number of times listed above.

[0054] After the first light emission sustain step I1 described above is completed, the first selective simultaneous erase step S1 is executed as shown in FIG. 7.

[0055] In this first selective simultaneous erase step S1, the address driver 6 applies an even-numbered address pulse APEV of a positive polarity shown in FIG. 7 to each of the even-numbered column electrodes D2, D4, D6, D8, . . . , Dm among the column electrodes D1 to Dm. The second sustain driver 8 applies the erase pulse EP of a negative polarity shown in FIG. 7 to each of the even-numbered row electrodes Y2, Y4, Y6, Y8, . . . , Yn among the row electrodes Y1 to Yn at the same timing as the application timing of the even-numbered address pulse APEV. The simultaneous application of these even-numbered address pulse APEV and erase pulse EP generate simultaneous erase discharge in all the discharge cells at the intersections between the even-numbered “column electrodes” and the even-numbered “row electrode pairs”, so that the wall charge formed inside the discharge cells extinguishes.

[0056] In other words, when the first selective simultaneous erase step S1 is executed, all the discharge cells arranged in the even-numbered rows/even-numbered columns are compulsively brought into the “light non-emission” state.

[0057] After this first selective simultaneous erase step S1 is completed, the second light emission sustain step I2 is executed as shown in FIG. 7.

[0058] In the second light emission sustain step I2, the first sustain driver 7 and the second sustain driver 8 alternatively apply the sustain pulses IPx and IPy of a positive polarity shown in FIG. 7 to the row electrodes X1 to Xn and Y1 to Yn. In this case, the number of times (or the period) of the application of the sustain pulse IP to be applied repeatedly inside the second light emission sustain step I2 of each sub-field SF1 to SF4 is 8. As a result of such an operation, only the discharge cells in which the wall charge remains, that is, only the discharge cells under the “light emission cell” state, execute sustain discharge whenever the sustain pulses IPx and IPy are applied, and sustain only eight times the light emission state accompanied with the sustain discharge.

[0059] After the second light emission sustain step I2 is completed, the second selective simultaneous erase step S2 is executed as shown in FIG. 7.

[0060] In this second selective simultaneous erase step S2, the address driver 6 applies an odd-numbered address pulse APOD of a positive polarity shown in FIG. 7 to each of the odd-numbered column electrodes D1, D3, D5, D7 . . . , Dm−1 among the column electrodes D1 to Dm The second sustain driver 8 applies the erase pulse EP of a negative polarity shown in FIG. 7 to each of the even-numbered row electrodes Y2, Y4, Y6, Y8, . . . , Yn among the row electrodes Y1 to Yn at the same timing as the application timing of the odd-numbered address pulse APOD. The simultaneous application of these odd-numbered address pulse APOD and erase pulse EP generate simultaneous erase discharge in all the discharge cells at the intersections between the odd-numbered “column electrodes” and the even-numbered “row electrode pairs”, so that the wall charge formed inside the discharge cells extinguishes.

[0061] In other words, when the second selective simultaneous erase step S2 is executed, all the discharge cells arranged in the even-numbered rows/odd-numbered columns are compulsively brought into the “light non-emission cell” state.

[0062] After this second selective simultaneous erase step S2 is completed, the third light emission sustain step I3 is executed as shown in FIG. 7.

[0063] In the third light emission sustain step I3, the first sustain driver 7 and the second sustain driver 8 alternatively apply the sustain pulses IPx and IPy of a positive polarity shown in FIG. 7 to the row electrodes X1 to Xn and Y1 to Yn . In this case, the number of times (or the period) of the application of the sustain pulse IP to be applied repeatedly inside the third light emission sustain step I3 of each sub-field SF1 to SF4 is 8. As a result of such an operation, only the discharge cells in which the wall charge remains, that is, only the discharge cells under the “light emission cell” state, execute sustain discharge whenever the sustain pulses IPx and IPy are applied, and sustain only eight times the light emission state accompanied with the sustain discharge.

[0064] After the third light emission sustain step I3 is completed, the third selective simultaneous erase step S3 is executed as shown in FIG. 7.

[0065] In this third selective simultaneous erase step S3, the address driver 6 applies an odd-numbered address pulse APOD of a positive polarity shown in FIG. 7 to each of the odd-numbered column electrodes D1, D3, D5, D7, . . , Dm−1 among the column electrodes D1 to Dm. The second sustain driver 8 applies the erase pulse EP of a negative polarity shown in FIG. 7 to each of the odd-numbered row electrodes Y1, Y3, Y5, Y7, . . . , Yn−1 among the row electrodes Y1 to Yn at the same timing as the application timing of the odd-numbered address pulse APOD. The simultaneous application of these odd-numbered address pulse APOD and the erase pulse EP generate simultaneous erase discharge in all the discharge cells at the intersections between the odd-numbered “column electrodes” and the odd-numbered “row electrode pairs”, so that the wall charge formed inside the discharge cells extinguishes.

[0066] In other words, when the third selection/simultaneous erase step S3 is executed, all the discharge cells arranged in the odd-numbered rows/odd-numbered columns are compulsively brought into the “light non-emission cell” state.

[0067] After this third selective simultaneous erase step S3 is completed, the fourth light emission sustain step I4 is executed as shown in FIG. 7.

[0068] In the fourth light emission sustain step I4, the first sustain driver 7 and the second sustain driver 8 alternatively apply the sustain pulses IPx, and IPy of a positive polarity shown in FIG. 7 to the row electrodes X1 to Xn and Y1 to Yn. In this case, the number of times (or the period) of the application of the sustain pulse IP to be applied repeatedly inside the fourth light emission sustain step I4 of each sub-field SF1 to SF4 is 8. As a result of such an operation, only the discharge cells in which the wall charge remains, that is, only the discharge cells under the “light emission cell” state, execute sustain discharge whenever the sustain pulses IPx and IPy are applied, and sustain only eight times the light emission state accompanied with the sustain discharge.

[0069] After the fourth light emission sustain step 14 is completed, the erase step E is executed as shown in FIG. 7.

[0070] In the erase step E, the second sustain driver 8 applies the erase pulse EP of a negative polarity shown in FIG. 7 to all the row electrodes Y1 to Yn. Erase discharge is generated inside one screen in response to such an application operation, and all the discharge cells enter the “light non-emission cell” state.

[0071] According to the driving method shown in FIG. 7, only the discharge cells set to the “light emission cell” state in the pixel data write step W keep the light emission state resulting from sustain discharge generated in each of the first to fourth light emission sustain step I1 to I4 in the sum of the number of times corresponding to the number of times of sustain discharge. In the sub-field SF1, for example, sustain discharge is effected 4 times in the first light emission sustain step I1 eight times in the second light emission sustain step I2, 8 times in the third light emission sustain step I3 and 8 times in the fourth light emission sustain step I4, that is, 28 times in all, as shown in FIG. 6. In other words, the number of times of execution of sustain discharge is allotted to each of the sub-fields SF1 to SF4 as listed below:

[0072] SF1: 28

[0073] SF2: 60

[0074] SF3: 92

[0075] SF4: 124

[0076] In this instance, intermediate luminance corresponding to the sum of the number of times of sustain discharge induced inside each sub-field SF1 to SF4 can be acquired on the screen of the PDP 10.

[0077] In the driving method shown in FIGS. 6 and 7, the first selective simultaneous erase step S1 is executed immediately after completion of the first light emission sustain step I1 to compulsively bring all the discharge cells arranged in the even-numbered row/even-numbered column into the “light non-emission cell” state. Further, the second selective simultaneous erase step S2 is executed immediately after completion of the second light emission sustain step I2 to compulsively bring all the discharge cells arranged in the even-numbered row/odd-numbered column into the “light non-emission cell” state. The third selective simultaneous erase step S3 is executed immediately after completion of the third light emission sustain step I3 to compulsively bring all the discharge cells arranged in the odd-numbered row/odd-numbered column into the “light non-emission cell” state.

[0078] Therefore, the discharge cells arranged in the odd-numbered row/odd-numbered column do not execute sustain discharge in the fourth light emission sustain step I4 even when they are under the “light emission cell” state. In other words, gradation driving is substantially conducted in the discharge cells belonging to the odd-numbered row/odd-numbered column in accordance with the light emission driving format A shown in FIG. 8. In consequence, sustain discharge is effected the number of times in each sub-field SF1 to SF4 as listed below:

[0079] SF1: 20

[0080] SF2: 52

[0081] SF3: 84

[0082] SF4: 116

[0083] On the other hand, the discharge cells arranged in the odd-numbered row/even-numbered column are not affected by the first selective simultaneous erase step S1 to the third selective simultaneous erase step S3. Therefore, gradation driving is substantially conducted in these discharge cells in accordance with the light emission driving format B shown in FIG. 8. In consequence, sustain discharge is effected the number of times in each sub-field SF1 to SF4 as listed below:

[0084] SF1: 28

[0085] SF2: 60

[0086] SF3: 92

[0087] SF4: 124

[0088] The discharge cells arranged in the even-numbered row/odd-numbered column are, however, compulsively brought into the “light non-emission cell” state at the stage of the second selective simultaneous erase step S2. Therefore, these discharge cells do not execute sustain discharge in the third light emission sustain step I3 and the fourth light emission sustain step I4. In other words, gradation driving is substantially executed in the discharge cells arranged in the even-numbered row/odd-numbered column in accordance with the light emission driving format C shown in FIG. 8. In consequence, sustain discharge is effected the number of times in each sub-field SF1 to SF4 as listed below:

[0089] SF1: 12

[0090] SF2: 44

[0091] SF3: 76

[0092] SF4: 108

[0093] Further, the discharge cells arranged in the even-numbered row/even-numbered column are compulsively brought into the “light non-emission cell” state at the stage of the first selective simultaneous erase step S1. Therefore, they do not execute the sustain discharge in each of the second light emission sustain step I2 to the fourth light emission sustain step I4. In other words, gradation driving is substantially executed in the discharge cells arranged in the even-numbered row/even-numbered column in accordance with the light emission driving format D shown in FIG. 8. In consequence, sustain discharge is effected the number of times in each sub-field SF1 to SF4 as listed below:

[0094] SF1: 4

[0095] SF2: 36

[0096] SF3: 68

[0097] SF4: 100

[0098] Whether each discharge cell is brought into the “light emission cell” state or the “light non-emission cell” state inside each sub-field depends on the pixel driving data GD consisting of four bits and five patterns shown in FIG. 5. In other words, when the bits of the pixel driving data GD are at the logic level “1”, selective erase discharge is induced in the sub-field corresponding to the bit digit as represented by the black circles in FIG. 5, and the discharge cells are brought into the “light non-emission cell” state. On the other hand, when the bits of the pixel driving data GD are at the logic level “0”, selective erase discharge is not generated. Therefore, the discharge cells are brought into the “light emission cell” state, and sustain discharge is induced in the sub-field corresponding to the bit digit as represented by the white circles.

[0099] Therefore, light emission of five gradations having respectively the following luminance levels is executed by the driving operation in the discharge cells arranged in the odd-numbered row/odd-numbered column among the discharge cells arranged in matrix as shown in FIG. 9 on the basis of the light emission driving format A using the pixel driving data GD described above:

[0100] [0, 20, 72, 156, 2721]

[0101] In the discharge cells arranged in the odd-numbered/even-numbered column, light emission of four gradations having respectively the following luminance levels is executed by the driving operation on the basis of the light emission driving format B using the pixel driving data GD (with the proviso that GD “0000” does not exist because luminance suppression is made by the second conversion table shown in FIG. 4B):

[0102] [0, 28, 88, 180]

[0103] In the discharge cells arranged in the even-numbered row/odd-numbered column, light emission of five gradations having respectively the following luminance levels is executed by the driving operation on the basis of the light emission driving format C:

[0104] [0, 12, 56, 132, 240]

[0105] In the discharge cells arranged in the even-numbered row/even-numbered column, light emission of five gradations having respectively the following luminance levels is executed on the basis of the light emission driving format D:

[0106] [0, 4, 40, 108, 208]

[0107] As a result, in the discharge cells arranged in the odd-numbered row/odd-numbered column, light emission of the luminance level shown in FIG. 10A is executed in accordance with the pixel data PD. In the discharge cells arranged in the odd-numbered row/even-numbered column, light emission of the luminance level shown in FIG. 10B is executed in accordance with the pixel data PD. In the discharge cells arranged in the even-numbered row/odd-numbered column, light emission of the luminance level shown in FIG. 10C is executed in accordance with the pixel data PD. Further, in the discharge cells arranged in the even-numbered row/even-numbered column, light emission of the luminance level shown in FIG. 10D is executed in accordance with the pixel data PD.

[0108] In other words, the number of light emissions (the number of times of sustain discharge) to be executed in each sub-field is executed as mutually different light emission driving formats A to D are allotted respectively thereto for each of the four discharge cells inside the discharge cell blocks encompassed by thick lines in FIG. 9.

[0109] Therefore, when the same pixel data is supplied to each of the four discharge cells inside the discharge cell block, the light emission luminance level inside this discharge cell block becomes such as the state shown in FIG. 11.

[0110] When the pixel data PD representative of the luminance level “4” is supplied, for example, the discharge cell G(j, k) arranged in the odd-numbered row/odd-numbered column emits light of the luminance level “20” as shown in FIG. 11. In this case, the discharge cell G(j, k+1) arranged in the odd-numbered row/even-numbered column emits light of the luminance level “28”. The discharge cell G(j+1, k) arranged in the even-numbered row/odd-numbered column emits light of the luminance level 12. Further, the discharge cell G(j+1, k+1) arranged in the even-numbered row/even-numbered column emits light of the luminance level “4”. In consequence, the mean luminance level of each discharge cell is “16”, and this is the light emission luminance level that is visually sensed in the discharge cell block unit consisting of the four discharge cells.

[0111] When the pixel data PD representative of the luminance level “10” is supplied, for example, the discharge cell G(j, k) arranged in the odd-numbered row/odd-numbered column emits light of the luminance level “72” as shown in FIG. 11. In this case, the discharge cell G(j, k+1) arranged in the odd-numbered row/even-numbered column emits light of the luminance level “88”. The discharge cell G(j+1, k) arranged in the even-numbered row/odd-numbered column emits light of the luminance level “132”. Further, the discharge cell G(j+1, k+1) arranged in the even-numbered row/even-numbered column emits light of the luminance level “108”. In consequence, the mean luminance level of each discharge cell is “100”, and this is the light emission luminance level that is visually sensed in the discharge cell block unit consisting of the four discharge cells.

[0112]
FIG. 12 is a graph showing the relation between the pixel data PD corresponding to the input image signal and the light emission luminance level visually sensed in the discharge cell block unit consisting of the four discharge cells.

[0113] Even though the number of gradations during driving for one discharge cell is five gradations as shown in FIG. 5, intermediate luminance of sixteen gradations can be visually sensed as shown in FIG. 12 when the adjacent four discharge cells are grasped as one display unit. In other words, the driving method described above executes a multi-gradation processing analogous to a dither processing without adding a dither coefficient to the original pixel data.

[0114] Therefore, the present invention can keep the luminance difference among the discharge cells inside all the discharge cell blocks constant, and can accomplish multi-gradation having high display quality.

[0115] Incidentally, in the embodiment given above, driving is executed by allotting the light emission driving format to each of the four discharge cells in the following way as shown in FIG. 9:

[0116] Discharge cells arranged in odd-numbered row/odd-numbered column: light emission driving format A

[0117] Discharge cells arranged in odd-numbered row/even-numbered discharge cells: light emission driving format B

[0118] Discharge cells arranged in even-numbered row/odd-numbered column: light emission driving format C

[0119] Discharge cells arranged in even-numbered row/even-numbered column: light emission driving format D

[0120] However, allotment of the light emission driving format to each discharge cell is not limited to the allotment described above.

[0121] The allotment of each light emission driving format A to D to each of the four discharge cells may be changed in each one-field display period as shown in FIG. 13.

[0122] In the first field, the allotment is as follows:

[0123] Discharge cell G(j,k) arranged in odd-numbered row/odd-numbered column: Light emission driving format A

[0124] Discharge cell G(j,k+1) arranged in odd-numbered row/even-numbered column: Light emission driving format B

[0125] Discharge cell G(j+1,k) arranged in even-numbered row/odd-numbered column: Light emission driving format C

[0126] Discharge cell G(j+1,k+1) arranged in even-numbered row/even-numbered column: Light emission driving format D

[0127] In the second field:

[0128] Discharge cell G(j,k) arranged in odd-numbered row/odd-numbered column: Light emission driving format B

[0129] Discharge cell G(j,k+1) arranged in odd-numbered row/even-numbered column: Light emission driving format A

[0130] Discharge cell G(j+1, k) arranged in even-numbered row/odd-numbered column: Light emission driving format D

[0131] Discharge cell G(j+1,k+1) arranged in even-numbered row/even-numbered column: Light emission driving format C

[0132] In the next third field:

[0133] Discharge cell G(j, k) arranged in odd-numbered row/odd-numbered column: Light emission driving format D

[0134] Discharge cell G(j,k+1) arranged in odd-numbered row/even-numbered column: Light emission driving format C

[0135] Discharge cell G(j+1, k) arranged in even-numbered row/odd-numbered column: Light emission driving format B

[0136] Discharge cell G(j+1,k+1) arranged in even-numbered row/even-numbered column: Light emission driving format A

[0137] In the fourth field:

[0138] Discharge cell G(j, k) arranged in odd-numbered row/odd-numbered column: Light emission driving format C

[0139] Discharge cell G(j,k+1) arranged in odd-numbered row/even-numbered column: Light emission driving format D

[0140] Discharge cell G(j+1, k) arranged in even-numbered row/odd-numbered column: Light emission driving format A

[0141] Discharge cell G(j+1,k+1) arranged in even-numbered row/even-numbered column: Light emission driving format B

[0142] The operation in each of the first to fourth fields described above is repeatedly executed.

[0143] The embodiment given above employs a so-called “selective erase address method” that the discharge cells are selectively discharged (selective erase discharge) in accordance with the pixel data and the wall charge is extinguished to write the pixel data, as the write method of the pixel data. However, the present invention can be similarly applied to a so-called “selective write address method” that the discharge cells are selectively discharged (selective write discharge) in accordance with the pixel data and the wall charge is generated inside the discharge cells, as the write method of the pixel data.

[0144]
FIG. 14 shows the driving pulses that the address driver 6, the first sustain driver 7 and the second sustain driver 8 apply to the PDP 10 and their application timing when the selective write address method is employed.

[0145] Incidentally, the operation contents of all the steps other than the simultaneous reset step R′ and the pixel data write step W′, that is, the first light emission sustain step I1 to the fourth light emission sustain step I4, the first selective simultaneous erase step S1 to the third selective simultaneous erase step S3 and the erase step E in FIG. 14 are the same as those shown in FIG. 7. Therefore, their explanation will be omitted.

[0146] In the simultaneous reset step R′ executed at the leading part of each sub-field shown in FIG. 14, the first sustain driver 7 applies simultaneously the reset pulse RPx of a positive polarity to all the row electrodes X1 to Xn of the PDP 10. At the same time, the second sustain driver 8 applies the reset pulse RPy of a negative polarity to all the row electrodes Y1 to Yn. All the discharge cells inside the PDP 10 are subjected to the reset discharge in response to the application of these reset pulses RPx and RPy and a wall charge of a predetermined amount is generated uniformly in each discharge cell. Immediately thereafter, the first sustain driver 7 generates the erase pulse EP of a negative polarity as shown in FIG. 14 and applies the erase pulse EP all at once to the row electrodes X1 to Xn. The application of such an erase pulse EP generates the erase discharge, and the wall charge that has been formed inside all the discharge cells extinguishes. In other words, according to the simultaneous reset step R′ in the selective write address method, all the discharge cells in the PDP 10 are initialized to the “light non-emission cell” state.

[0147] In the next pixel data write step W′, the address driver 6 generates the pixel data pulse having a pulse voltage corresponding to the pixel driving data bit DB supplied from the memory 4. In the sub-field SF1, for example, the memory 4 supplies the pixel driving data bit DB1. Therefore, the address driver 6 generates a pixel data pulse having a pulse voltage corresponding to the logic level of this pixel driving data bit DB1. In the sub-field SF2, the memory 4 supplies the pixel driving data bit DB2. Therefore, the address driver 6 generates a pixel data pulse having a pulse voltage corresponding to the logic level of this pixel driving data bit DB2. Incidentally, the address driver 6 generates a pixel data pulse having a high voltage when the logic level of the pixel driving data bit DB is “1” and a pixel data pulse having a low voltage (0 V) when the logic level is “0”. The address driver 6 groups the pixel data pulses so generated into the form of pixel data pulse groups DP1 to DPn for each display line and serially applies them to the column electrodes D1 to Dm as shown in FIG. 14.

[0148] In the pixel data write step W, the second sustain driver 8 generates the scan pulse SP of a negative polarity at the application timing of each of the pixel data pulse group DP1 to DPn, and serially applies them to all the row electrodes Y1 to Yn as shown in FIG. 14. Here, discharge (selective write discharge) occurs in only the discharge cells at the intersections between the display lines to which the scan pulse SP is applied and the column to which the pixel data pulse of a high voltage is applied. After such selective write discharge is terminated, the wall charge is generated inside the discharge cells and these discharge cells shift to the “light emission cell” state. On the other hand, such selective write discharge does not occur in the discharge cells to which the scan pulse SP is applied but the pixel data pulse of a low voltage is applied. These discharge cells sustain the state initialized by the simultaneous reset step R′, that is, the “light non-emission cell” state. In other words, this pixel data write step W′ sets each discharge cell to either the “light emission cell” state or the “light non-emission cell” state in accordance with the pixel data based on the input image signal.

[0149] When the selective write address method described above is employed, the second data conversion circuit 34 uses the conversion table shown in FIG. 15 in place of the conversion table shown in FIG. 5 and converts the luminance suppression pixel data PDL to the pixel driving data GD. Consequently, in the sub-field SF corresponding to the bit digit which is at the logic level “1” among the pixel driving data GD (represented by double-circle in FIG. 15), selective write discharge and sustain discharge described above are generated.

[0150] Therefore, when the selective write address method is employed as the pixel data write method, too, similarly to the case in which the selective erase address method is employed, the discharge cells arranged in the odd-numbered row/odd-numbered column execute light emission of the five gradations having respectively the following luminance levels by the driving operation based on the light emission driving format A using the pixel driving data GD described above:

[0151] [0, 20, 72, 156, 272]

[0152] In the discharge cells arranged in the odd-numbered row/even-numbered column, light emission of four gradations having respectively the following luminance levels is executed by the driving operation based on the light emission driving format B:

[0153] [0, 28, 88, 180]

[0154] In the discharge cells arranged in the even-numbered row/odd-numbered column, light emission of five gradations having respectively the following luminance levels is executed by the driving operation based on the light emission driving format C:

[0155] [0, 12, 56, 132, 2401]

[0156] In the discharge cells arranged in the even-numbered row/even-numbered column, light emission of five gradations having respectively the following luminance levels is executed by the driving operation based on the light emission driving format D:

[0157] [0, 4, 40, 108, 208]

[0158] As described above in detail, when only the discharge cells set to the light emission cell state in accordance with the input image signals are allowed to emit light the number of light emissions allotted in accordance with weighting of the sub-fields, the present invention renders the number of light emissions to be allotted different for each discharge cell inside the discharge cell block. Consequently, multi-gradation display equivalent to the dither processing can be accomplished without adding dither coefficients having mutually different values to the pixel data corresponding to each discharge cell inside the discharge cell block.

[0159] According to the present invention, the luminance difference becomes constant among the discharge cells inside all the discharge cell blocks, and an excellent dither processing can be executed without lowering display quality.

[0160] This application is based on Japanese Patent Application No. 2000-186530 which is hereby incorporated by reference.

Driving method of plasma display panel

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