Patent Grant
11790832
The present invention relates to a display device. More particularly, the present invention relates to a display device with driving circuits and light emitting elements.
Generally, pulse amplitude of a driving current flowing through a light emitting element in a display device is adjusted to control a gray level of a sub-pixel to be displayed. However, since the amplitude of the driving current does not linear with the brightness of the light emitting element, the light emitting element cannot display at the accurate gray level by only controlling the pulse amplitude of a driving current.
One embodiment of the present disclosure is to provide a display device. The display device includes a plurality of light emitting elements and a plurality of driving circuits. Each of the driving circuits is configured to generate a driving current to drive one of the light emitting elements to emit light. Each of the driving circuits includes a first transistor, a second transistor, a reset circuit, a first control circuit and a second control circuit. The driving current flows from a first system high voltage terminal through the first transistor, the second transistor and the one of the light emitting elements to a system low voltage terminal. The reset circuit is configured to reset a voltage level of a gate terminal of the second transistor. The first control circuit is configured to control the first transistor to adjust pulse amplitude of the driving current. The second control circuit is configured to control the second transistor to adjust a pulse width of the driving current, and configured to control the second transistor, according to a corresponding one of a plurality of sweep signals, to adjust a phase of the driving current. Each of the driving circuits provides the driving current at different time points according to the sweep signals.
Another embodiment of the present disclosure is to provide a display device. The display device includes a plurality of light emitting element and a plurality of driving circuit. Each of the driving circuits is configured to generate a driving current to drive one of the light emitting elements to emit light. Each of the driving circuits includes a first transistor, a second transistor, a reset circuit, a first control circuit and a second control circuit. The first transistor and the second transistor are electrically in series between a first system high voltage terminal and a system low voltage terminal. The reset circuit is electrically coupled to a gate terminal of the second transistor. The first control circuit is electrically coupled to a gate terminal of the first transistor, and is configured to control the first transistor to adjust pulse amplitude of the driving current. The second control circuit is electrically coupled to the gate terminal of the second transistor, and is configured to control the second transistor to adjust a pulse width of the driving current, and is configured to control the second transistor, according to a corresponding one of a plurality of sweep signals, to adjust a phase of the driving current. Each of the driving circuits provides the driving current at different time points according to the sweep signals.
The other embodiment of the present disclosure is to provide a driving method for driving a display device with a plurality of driving circuits and a plurality of light emitting elements. Each of the driving circuits is configured to generate a driving current to drive the one of light emitting elements to emit light. The driving method includes the following steps. During a global scanning period, simultaneously providing a plurality of first data signals to the driving circuits according to color of each of the light emitting elements to be display. During a progressive scanning period, sequentially providing a plurality of second data signals to the driving circuits according to gray level of each of the light emitting elements to be display, and sequentially providing a plurality of sweep signals to the driving circuits, wherein each of the driving circuits generates the driving current, according to the one of the first data signals, to drive the one of the light emitting elements to emit light, and each of the driving circuits starts or suspends the driving current according to one of the second data signals.
These and other features, aspects, and advantages of the present invention will become better understood with reference to the following description and appended claims.
It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the invention as claimed.
The invention can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows:
Reference will now be made in detail to the present embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
Reference is made to
As shown in
The first control circuit 110 of the driving circuit 100 can be considered as a pulse amplitude modulation circuit, and the first control circuit 110 is configured to control a voltage level at the gate terminal of the first transistor T1, in order to control the pulse amplitude of the driving current. The second control circuit 120 of the driving circuit 100 can be considered as a pulse width modulation circuit, and the second control circuit 120 is configured to control timing for turning off the second transistor T2, in order to control the pulse width of the driving current.
The first control circuit 110 is electrically coupled to a gate terminal of the first transistor T1. The first control circuit 110 is configured to receive a corresponding one of multiple of first data signals VPAM_R/G/B, and the first control circuit 110 is configured to control the first transistor T1, according to the corresponding one of the first data signals VPAM_R/G/B, to adjust pulse amplitude of the driving current during following emission periods.
The second control circuit 120 is electrically coupled to the gate terminal of the second transistor T2. The second control circuit 120 is configured to receive a corresponding one of multiple of the second data signals Vsig(m)_R/G/B according to the fourth control signal SP(n), and the second control circuit 120 is configured to receive the sweep signal Sweep(n), to adjust pulse width of the driving current during the following emission periods.
As shown in
The corresponding one of the second data signals Vsig(m)_R/G/B is decided by a gray level to be displayed by each of the light emitting elements L1. If the gray level to be displayed is relatively large, an absolute value of voltage of the corresponding one of the second data signals Vsig(m)_R/G/B can be relatively small. On the other hand, if the gray level to be displayed is relatively small, an absolute value of voltage of the corresponding one of the second data signals Vsig(m)_R/G/B can be relatively large. In other words, the corresponding one of the second data signals Vsig(m)_R/G/B received by the second control circuit 120 of the driving circuit 100 is decided by the gray level to be displayed by the sub-pixel.
Specifically, reference is made to
A first terminal of the fifth transistor T5 is electrically coupled to the gate terminal of the first transistor T1, a second terminal of the fifth transistor T5 is electrically coupled to the second terminal of the first transistor T1, a gate terminal of the fifth transistor T5 is configured to receive the second control signal SPAM. A first terminal of the sixth transistor T6 is electrically coupled to the first terminal of the fifth transistor T5, a second terminal of the sixth transistor T6 is configured to receive the third control signal VST_PAM, and a gate terminal of the sixth transistor T6 is configured to receive the third control signal VST_PAM.
The second control circuit 120 includes a seventh transistor T7, an eighth transistor T8, an ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12 and the third capacitor C3. A first terminal of the seventh transistor T7 is configured to receive the corresponding one of the second data signals Vsig(m)_R/G/B, a gate terminal of the seventh transistor T7 is configured to receive the fourth control signal SP(n). A first terminal of the eighth transistor T8 is electrically coupled to a second terminal of the seventh transistor T7.
A first terminal of the ninth transistor T9 is electrically coupled to a second terminal of the eighth transistor T8, a second terminal of the ninth transistor T9 is electrically coupled to the gate terminal of the second transistor T2, and a gate terminal of the ninth transistor T9 is configured to receive the fifth control signal Emi_PWM(n). A first terminal of the tenth transistor T10 is electrically coupled to a second system high voltage terminal VDD_PWM, a second terminal of the tenth transistor T10 is electrically coupled to the second terminal of the seventh transistor T7 and the first terminal of the eighth transistor T8, a gate terminal of the tenth transistor T10 is configured to receive the fifth control signal Emi_PWM(n).
A first terminal of the third capacitor C3 is configured to receive the sweep signal Sweep(n), a second terminal of the third capacitor C3 is electrically coupled to the gate terminal of the eighth transistor T8. A first terminal of the eleventh transistor T11 is electrically coupled to a second terminal of the third capacitor C3 and the gate terminal of the eighth transistor T8, a second terminal of the eleventh transistor T11 is electrically coupled to the second terminal of the eighth transistor T8 and the first terminal of the ninth transistor T9, a gate terminal of the eleventh transistor T11 is configured to receive the fourth control signal SP(n). A first terminal of the twelfth transistor T12 is electrically coupled to the second terminal of the third capacitor C3, the gate terminal of the eighth transistor T8 and a first terminal of the eleventh transistor T11, a second terminal of the twelfth transistor T12 is configured to receive the sixth control signal VST(n), a gate terminal of the twelfth transistor T12 is configured to receive the sixth control signal VST(n).
The reset circuit 130 includes a third transistor T3 and a first capacitor C1. A first terminal of the third transistor T3 is electrically coupled to the gate terminal of the second transistor T2, a second terminal of the third transistor T3 is configured to receive the reset signal Vset, a gate terminal of the third transistor T3 is configured to receive the first control signal SET(n). A first terminal of the first capacitor C1 is electrically coupled to the gate terminal of the second transistor T2 and the first terminal of the third transistor T3, a second terminal of the first capacitor C1 is electrically coupled to the second terminal of the third transistor T3, and the second terminal of the first capacitor C1 is configured to receive the reset signal Vset.
A first terminal of the thirteenth transistor T13 is electrically coupled to the first system high voltage terminal VDD_PAM, a second terminal of the thirteenth transistor T13 is electrically coupled to the first terminal of the first transistor T1, and a gate terminal of the thirteenth transistor T13 is configured to receive the fifth control signal Emi_PWM(n). A first terminal of the first transistor T1 is electrically coupled to the second terminal of the thirteenth transistor T13, a second terminal of the first transistor T1 is electrically coupled to the first terminal of the second transistor T2, and a gate terminal of the first transistor T1 is electrically coupled to the first control circuit 110. A first terminal of the second transistor T2 is electrically coupled to a second terminal of the first transistor T1, a second terminal of the second transistor T2 is electrically coupled to the first terminal of the fourteenth transistor T14, and a gate terminal of the second transistor T2 is electrically coupled to the second control circuit 120. A first terminal of the fourteenth transistor T14 is electrically coupled to the second terminal of the second transistor T2, a gate terminal of the fourteenth transistor T14 is configured to receive the seventh control signal Emi_PAM(n).
A first terminal of the light emitting element L1 is electrically coupled to the second terminal of the fourteenth transistor T14, and a second terminal of the light emitting element L1 is electrically coupled to the system low voltage terminal VSS. A first terminal of the fifteenth transistor T15 is electrically coupled to the second terminal of the fourteenth transistor T14, a second terminal of the fifteenth transistor T15 is electrically coupled to the system low voltage terminal VSS, and a gate terminal of the fifteenth transistor T15 is configured to receive a control signal TEST. Before the light emitting element L1 is mounted, the fifteenth transistor T15 is configured to conduct the current path of the driving circuit 100 to determine whether the driving circuit 100 can operate in normal. The aforementioned transistors T1˜T15 can be implemented by P-type MOSFET. However, it should not intend to limit the disclosure. In another embodiment, the person skilled in the art can replace the aforementioned transistors T1˜T15 by N-type MOSFET, C-type MOSFET or other similar switch elements, and accordingly adjust the system voltages (such as, the first system high voltage terminal VDD_PAM, the second system high voltage terminal VDD_PWM and the system low voltage terminal VSS), control signals (such as, the first control signal SET(n), the third control signal VST_PAM, the fourth control signal SP(n), the fifth control signal Emi_PWM(n) and the sixth control signal VST(n)) and the data signals, in order to achieve the functions of the present disclosure.
For better understanding the operation of the driving circuit 100, reference is made to
In one frame of the operation timing of the driving circuit 100 can include multiple of reset and emission periods EM. As a result, during each of the reset and emission periods EM in one frame, the emission time length of the light emitting element L1 can be controlled, in order to control the gray level to be displayed by the light emitting element L1.
In other words, once the driving circuit 100 receive the corresponding one of the first data signals VPAM_R/G/B and the corresponding one of the second data signals Vsig(m)_R/G/B, the driving circuit 100 can repeat the multiple of the reset and emission periods EM in the following periods.
That is, the operation timing of the driving circuit 100 can includes the first writing period GW (which can be considered as a global writing period), the second writing period PW (which can be considered as a progressive writing period) and multiple of the reset and emission periods EM (such as, 13 reset and emission periods EM in one frame), and each of the reset and emission periods EM includes the fifth period P5 (the reset period) and the sixth period P6 (the emission period).
Specifically, during the first period P1, the third control signal VST_PAM has a first logical level (such as, the low logic level), and during the second period P2 to the sixth period P6, the third control signal VST_PAM has a second logical level (such as, the high logic level). During the second period P2, the second control signal SPAM has the low logic level; and during the first period P1, the third period P3 to the sixth period P6, the second control signal SPAM has the high logic level. During the third period P3, the sixth control signal VST(n) has the low logic level; and during the first period P1, the second period P2 and the fourth period P4 to the sixth period P6, the sixth control signal VST(n) has the high logic level. During the fourth period P4, the fourth control signal SP(n) has the low logic level; and during the first period P1 to the third period P3, the fifth period P5 and the sixth period P6, the fourth control signal SP(n) has the high logic level.
During the fifth period P5, the first control signal SET(n) has the low logic level; and during the first period P1 to the fourth period P4 and the sixth period P6, the sixth period P6 has the high logic level. During the sixth period P6, the fifth control signal Emi_PWM(n) has the low logic level; and during the first period P1 to the fifth period P5, the fifth control signal Emi_PWM(n) has the high logic level. During the sixth period P6, the seventh control signal Emi_PAM(n) has the low logic level; and during the first period P1 to the fifth period P5, the seventh control signal Emi_PAM(n) has the high logic level. During the sixth period P6, the sweep signal Sweep(n) is gradually pulled down from the high logic level to the low logic level; and during the first period P1 to the fifth period P5, the sweep signal Sweep(n) has the high logic level.
During the first period P1, since the third control signal VST_PAM has the low logic level, the sixth transistor T6 conducts. On the other hand, since the second control signal SPAM has the high logic level, the fourth transistor T4 and the fifth transistor T5 turns off. In additional, in the first period P1, the time length during the third control signal VST_PAM at the low logic level can be one time unit (such as, 10 μs).
Specifically, in the first period P1, the third control signal VST_PAM is transmitted through the sixth transistor T6 to the second terminal of the second capacitor C2, such that the voltage level at the second terminal of the second capacitor C2 is pulled down to the low logic level.
In the second period P2, since the second control signal SPAM has the low logic level, the fourth transistor T4 and the fifth transistor T5 conducts. On the other hand, since the third control signal VST_PAM has the high logic level, the sixth transistor T6 turns off, such that the voltage level at the second terminal of the second capacitor C2 is maintained at the low logic level, same as the initial of the second period P2. In additional, in the second period P2, the time length during the second control signal SPAM at the low logic level can be one time unit (such as, 10 μs).
Specifically, in the initial of the first period P1, since the voltage level at the second terminal of the second capacitor C2 is maintained at the low logic level, the first transistor T1 conducts. And then, the corresponding one of the first data signals VPAM_R/G/B is transmitted through the fourth transistor T4, the first transistor T1 and the fifth transistor T5 to the gate terminal of the first transistor T1 until the first transistor T1 cuts off. Meanwhile, since the second terminal of the second capacitor C2 is electrically coupled to the gate terminal of the first transistor T1, the voltage level at the gate terminal of the first transistor T1 is maintained and stored by the second capacitor C2, such that the first transistor T1 can control/adjust the pulse amplitude of the driving current in the following reset and emission periods EM.
In other words, during the first period P1 of the first writing period GW, the driving circuit 100 reset the voltage level at the gate terminal of the first transistor T1. And, during the second period P2 of the first writing period GW, the corresponding one of the first data signals VPAM_R/G/B is written into the first control circuit 110 and to compensate the threshold voltage of the first transistor T1 also. That is, the first period P1 is the reset period of the first transistor T1, the second period P2 is the writing and compensation period of the first transistor T1.
In the third period P3, since the sixth control signal VST(n) has the low logic level, the twelfth transistor T12 and the eighth transistor T8 conducts. On the other hand, since the fifth control signal Emi_PWM(n) and the fourth control signal SP(n) have the high logic level, the tenth transistor T10, the ninth transistor T9, the seventh transistor T7 and the eleventh transistor T11 turn off. In additional, in the third period P3, the time length during the sixth control signal VST(n) at the low logic level can be one time unit (such as, 10 μs).
Specifically, in the third period P3, the sixth control signal VST(n) is transmitted through the twelfth transistor T12 to the second terminal of the third capacitor C3, such that the voltage level at the second terminal of the third capacitor C3 is stored at the low logic level.
In the fourth period P4, since the fourth control signal SP(n) has the low logic level, the seventh transistor T7 and the eleventh transistor T11 conducts. On the other hand, since the sixth control signal VST(n) has the high logic level, the twelfth transistor T12 turns off. In additional, the fourth period P4, the time length during the fourth control signal SP(n) at the low logic level can be one time unit (such as, 10 μs).
Specifically, in the fourth period P4, since the second terminal of the third capacitor C3 is maintained at the low logic level, the eighth transistor T8 conducts. And, the corresponding one of the second data signals Vsig(m)_R/G/B is transmitted through the seventh transistor T7, the eighth transistor T8 and the eleventh transistor T11 to the gate terminal of the eighth transistor T8 until the eighth transistor T8 cuts off.
In other words, during the third period P3 of the second writing period PW, the driving circuit 100 resets the voltage level at the gate terminal of the eighth transistor T8. And, during the fourth period P4 of the second writing period PW, the corresponding one of the second data signals Vsig(m)_R/G/B is written into the second control circuit 120, and to compensate the threshold voltage of the eighth transistor T8 also. That is, the third period P3 is the reset period of the eighth transistor T8, the fourth period P4 is the writing and compensation period of the eighth transistor T8.
To be noted that, since the first control circuit 110 and the second control circuit 120 are respectively receive the corresponding one of the first data signals VPAM_R/G/B and the corresponding one of the second data signals Vsig(m)_R/G/B according to the second control signal SPAM and the fourth control signal SP(n). Therefore, the corresponding one of the first data signals VPAM_R/G/B and the corresponding one of the second data signals Vsig(m)_R/G/B can be written to the driving circuit 100 at different time periods, instead of at the same time.
And, the second capacitor C2 of the first control circuit 110 stores the voltage level after the corresponding one of the first data signals VPAM_R/G/B is written to the first control circuit 110 during the first writing period GW, and the third capacitor C3 of the second control circuit 120 stores the voltage level after the corresponding one of the second data signals Vsig(m)_R/G/B is written to the second control circuit 120 during the second writing period PW. Therefore, the first writing period GW and the second writing period PW of the driving circuit 100 can operate isolated. Furthermore, in some embodiments, the time interval between the first writing period GW and the second writing period PW may be longer, the said time interval can be occupied by the reset and emission periods EM, in order to increase the ratio of the reset and emission period EM occupied in one frame.
In the fifth period P5, since the first control signal SET(n) has the low logic level, the third transistor T3 conducts. Specifically, during the fifth period P5, the reset signal Vset is transmitted through the third transistor T3 to the gate terminal of the second transistor T2 and the first terminal of the first capacitor C1. Therefore, the voltage level at the first terminal of the first capacitor C1 is stored at the low logic level, and the second transistor T2 conducts. In additional, during the fifth period P5, the time length during the first control signal SET(n) at the low logic level can be four time units (such as, 4*10 μs=40 μs). In some embodiments, the reset signal Vset can be −3 volts.
In the sixth period P6 (the emission period), since the fifth control signal Emi_PWM(n) and the seventh control signal Emi_PAM(n) have the low logic level, the tenth transistor T10, the ninth transistor T9, the thirteenth transistor T13 and the fourteenth transistor T14 conduct, such that the driving current is transmitted through the thirteenth transistor T13, the first transistor T1, the second transistor T2 and the fourteenth transistor T14 to the system low voltage terminal VSS. In additional, during the sixth period P6, the fifth control signal Emi_PWM(n) at the low logic level can be six time units (such as, 6*10 μs=60 μs). During the sixth period P6, the seventh control signal Emi_PAM(n) at the low logic level can be five time units (such as, 5*10 μs=50 μs).
To be noted that, the difference of the time length, such as 10 μs, between the fifth control signal Emi_PWM(n) and the seventh control signal Emi_PAM(n) at the low logic level is only to control the pulse amplitude of the driving current during the low gray level. Therefore, the fifth control signal Emi_PWM(n) of the present can be implemented by the seventh control signal Emi_PAM(n). In additional, in some embodiments, during the sixth period P6 (the emission period), the time lengths of the fifth control signal Emi_PWM(n) and the seventh control signal Emi_PAM(n) at the low logic level are same. For example, during the sixth period P6, the time length of the seventh control signal Emi_PAM(n) at the low logic level can be six time units (such as, 6*10 μs=60 μs).
And, during the sixth period P6 (the emission period), the waveform of the sweep signal Sweep(n) can be a triangular wave, an oblique wave or a sawtooth wave.
As a result, the second control circuit 120 can control the second transistor T2 according to the corresponding one of the second data signals Vsig(m)_R/G/B, in order to adjust the pulse width of driving current during the sixth period P6 (the emission period).
During the sixth period P6 (the emission period), the sweep signal Sweep(n) received by the first terminal of the third capacitor C3 gradually pulls down the voltage level at the gate terminal of the eighth transistor T8, through capacitive coupling effect, until the eighth transistor T8 conducts according to the corresponding one of the second data signals Vsig(m)_R/G/B and the sweep signal Sweep(n), such that the voltage of the second system high voltage terminal is transmitted through the tenth transistor T10, the eighth transistor T8, the ninth transistor T9 to the gate terminal of the second transistor T2, so as to turn off the second transistor T2.
That is, during the initial (such as when the seventh control signal Emi_PAM(n) at the low logic level) of the sixth period P6 (the emission period), the thirteenth transistor T13, the first transistor T1, the second transistor T2 and the fourteenth transistor T14 are conductive, such that the driving circuit 100 starts to generate the driving current. And then, the second control circuit 120 turns off the second transistor T2 according to the corresponding one of the second data signals Vsig(m)_R/G/B and the sweep signals Sweep(n), so as to stop the driving circuit 100 generating the driving current. The time length from aforementioned start to stop generating the driving current can be considered as the pulse width of the driving current.
That is, in the sixth period P6 (the emission period) of the reset and emission period EM, in response to the seventh control signal Emi_PAM(n) at the low logic level, the driving circuit 100 starts to generating the driving current, and then, the second transistor T2 will be turned off, according to the corresponding one of the second data signals Vsig(m)_R/G/B corresponding to a gray level, to stop generating the driving current.
That is, in the sixth period P6 (the emission period) of the reset and emission period EM, the voltage level at the gate terminal of the eighth transistor T8 in the driving circuit 100 is linear with the voltage level of the sweep signal Sweep(n), such that the eighth transistor T8 can determine the timing for tuning off the second transistor T2 according to the corresponding one of the second data signals Vsig(m)_R/G/B written in the fourth period P4, to control the pulse width of the driving current.
For example, if the gray level to be displayed by the light emitting element L1 is high gray level, in the fourth period P4 of the second writing period PW, the voltage(/absolute voltage) of the corresponding one of the second data signals Vsig(m)_R/G/B is larger(/smaller), the voltage level at the gate terminal of the eighth transistor T8 is relatively high, and the voltage level at the second terminal of the third capacitor C3 is also relatively high. Therefore, in the sixth period P6 (the emission period) of the reset and emission period EM, since the voltage level at the gate terminal of the eighth transistor T8 is relatively high, the oblique wave of the sweep signal Sweep(n) will spend more time to pull down the voltage level at the gate terminal of the eighth transistor T8 until the eighth transistor T8 conducts. And, when the eighth transistor T8 conducts, the voltage of a second system high voltage terminal VDD_PWM is transmitted through the tenth transistor T10, the eighth transistor T8 and the ninth transistor T9 to the second transistor T2, so as to turn off the second transistor T2.
In this case, during the sixth period P6 (the emission period), the rime length that the second transistor T2 is conductive is relatively longer. That is, the pulse width of the driving current is relatively large, such that the emission time of the light emitting element L1 longer. And, since the driving circuit 100 generates the driving currents with same pulse width during each of the sixth periods P6 (the emission periods) in one frame, the gray level displayed by light emitting element L1 is relatively high.
On the other hand, if the gray level to be displayed by the light emitting element L1 is low gray level, in the fourth period P4 of the second writing period PW, the voltage(/absolute voltage) of the corresponding one of the second data signals Vsig(m)_R/G/B is smaller(/larger), the voltage level at the gate terminal of the eighth transistor T8 is relatively low, and the voltage level at the second terminal of the third capacitor C3 is also relatively low. Therefore, in the sixth period P6 (the emission period) of the reset and emission period EM, since the voltage level at the gate terminal of the eighth transistor T8 is relatively high, the oblique wave of the sweep signal Sweep(n) will spend less time to pull down the voltage level at the gate terminal of the eighth transistor T8 until the eighth transistor T8 conducts. And, when the eighth transistor T8 conducts, the voltage of the second system high voltage terminal VDD_PWM is transmitted through the tenth transistor T10, the eighth transistor T8 and the ninth transistor T9 to the second transistor T2, so as to turn off the second transistor T2.
In this case, during the sixth period P6 (the emission period), the rime length that the second transistor T2 is conductive is shorter. That is, the pulse width of the driving current is relatively small, such that the emission time of the light emitting element L1 is shorter. And, since the driving circuit 100 generates the driving currents with same pulse width during each of the sixth periods P6 (the emission periods) in one frame, the gray level displayed by light emitting element L1 is relatively low.
Reference is made to
The display panel 1200 includes the driving circuits 100 respectively arranged in a first sub-pixel line LN1 to a xth sub-pixel line LNx, each of the driving circuits 100 is configured to drive the light emitting element L1 (as shown in
As shown in
The driving circuits 100 of the second sub-pixel line LN2 are configured to receive the second control signal SPAM, a fourth control signal SP(2), a sixth control signal VST(2) (not shown), a first control signal SET(2) (not shown), a sweep signal Sweep(2), a fifth control signal Emi_PWM (2) and a seventh control signal Emi_PAM (2); and so on.
To be noted that, during the reset and emission period EM, the driving circuits 100 receive the sweep signal Sweep(n), and start or stop generating the driving current according to the corresponding one of the first data signals VPAM_R/G/B, so as to adjust the pulse width of the driving current.
Therefore, the display device 1000 of the present disclosure respectively provide the corresponding sweep signals Sweep(1)˜Sweep(x) to the driving circuits 100 in the first sub-pixel line LN1 to the xth sub-pixel line LNx, such that the light emitting elements corresponding to the driving circuits 100 in different lines can emit at different reset and emission periods EM.
Reference is also made to
In the first writing period GW of the global scanning period GS, all the driving circuit 100 receive the first data signals VPAM_R/G/B according to the second control signal SPAM and the color of each sub-pixels, respectively.
That is, in the first writing period GW of the global scanning period GS, the second control signal SPAM has a first logic level (such as, a low logic level), the display device 1000 simultaneously provides/writes the first data signals VPAM_R/G/B to the first control circuit 110 of each of the driving circuit 100 in the first sub-pixel line LN1 to the xth sub-pixel line LNx.
In the second writing period PW of the progressive scanning period PS, the driving circuits 100 in the first sub-pixel line LN1 receive the second data signals Vsig(m)_R/G/B according to the fourth control signal SP(1) and the gray level to be displayed by each of sub-pixels; the driving circuits 100 in the second sub-pixel line LN2 receive the second data signals Vsig(m)_R/G/B according to the fourth control signal SP(2) and the gray level to be displayed by each of sub-pixels; and so on.
Specifically, in the reset and emission periods EM1˜EMa of the progressive scanning period PS, the pulse of the fourth control signal SP(1) can be one time unit (such as, 10 μs) earlier to the pulse of the fourth control signal SP(1); the pulse of the fourth control signal SP(3) (not shown) can be one time unit (such as, 10 μs) earlier to the pulse of the fourth control signal SP(2); and so on. The pulse of the fourth control signal SP(x-1) (not shown) can be one time unit (such as, 10 μs) earlier to the pulse of the fourth control signal SP(x) (not shown). As a result, during the progressive scanning period PS, the driving circuits 100 in different sub-pixel lines have different second writing periods PW. Therefore, during the progressive scanning period PS, the display device 1000 sequentially provides/writes multiple of the second data signals Vsig(m)_R/G/B to the driving circuits 100 in the first sub-pixel line LN1 to the xth sub-pixel line LNx.
In other words, in the progressive scanning period PS, the fourth control signals SP(1)˜SP(x) have the low logic level during the second writing periods PW of each of the driving circuits 100 in the first sub-pixel line LN1 to the xth sub-pixel line LNx. The display device 1000 sequentially provides/writes multiple of the second data signals Vsig(m)_R/G/B to the second control circuit 120 of each of the driving circuits 100.
In the progressive scanning period PS, the driving circuits 100 in the first sub-pixel line LN1 are configured to receive the sweep signal Sweep(1), during the reset and emission period EM1 of the driving circuits 100 in the first sub-pixel line LN1, and each of the driving circuits 100 in the first sub-pixel line LN1 controls the pulse width of the driving current generated by itself, according to the corresponding one of the second data signals Vsig(m)_R/G/B. In the progressive scanning period PS, the driving circuits 100 in a second sub-pixel line LN2 are configured to receive the sweep signal Sweep(2), during the reset and emission period EM1 of the driving circuits 100 in the second sub-pixel line LN2, and each of the driving circuits 100 in the first sub-pixel line LN2 controls the pulse width of the driving current generated by itself, according to the corresponding one of the second data signals Vsig(m)_R/G/B; and so on. In the progressive scanning period PS, the driving circuits 100 in the xth sub-pixel line LNx are configured to receive the sweep signal Sweep(x), during the reset and emission period EM1 of the driving circuits 100 in the xth sub-pixel line LNx, and each of the driving circuits 100 in the xth sub-pixel line LNx controls the pulse width of the driving current generated by itself, according to the corresponding one of the second data signals Vsig(m)_R/G/B.
Specifically, in one of the reset and emission period EM1˜EMa of the progressive scanning period PS, the pulse of the sweep signal Sweep(1) (as the sawtooth wave shown in
That is, in the progressive scanning period PS, the driving circuits 100 in different lines (e.g. the first sub-pixel line LN1 to the xth sub-pixel line LNx) respectively receive the sweep signal Sweep(1)˜Sweep(x), so as to control the pulse width of the driving currents during the reset and emission periods EM1˜EMa of each of the driving circuits 100. The reset and emission periods EM2EM3˜EMa-1 and EMa are similar with the reset and emission period EM1, and thus the explanations are omitted.
Specifically, reference is also made to
To be noted that, each of the reset and emission period EM1˜EMa does not represent the actual time length that the driving circuit 100 generates the driving current. The fifth period P5 in each the reset and emission periods EM1˜EMa represents the time period for resetting the voltage level at the gate terminal of the second transistor T2 in the corresponding driving circuit 100. And the sixth period P6 in each the reset and emission periods EM1˜EMa represents the time period in which the corresponding driving circuit 100 can generate the driving current.
In one frame, the driving circuits 100 in the same line of the display device 1000 includes one first writing period GW, one second writing period PW and multiple of reset and emission periods EM1˜EMa. The first writing periods GW of the driving circuits 100 in different lines (e.g. the first sub-pixel line LN1 to the xth sub-pixel line LNx) are at the same time, the second writing periods PW of the driving circuits 100 in different lines (e.g. the first sub-pixel line LN1 to the xth sub-pixel line LNx) are at different time phases, and the reset and emission period EM1˜EMa of each of the driving circuits 100 in different lines (e.g. the first sub-pixel line LN1 to the xth sub-pixel line LNx) are also at different time phases. In some embodiments, the “a” of the reset and emission period EMa can be implemented by 13, that is the number of the reset and emission period EM1˜EMa can be 13.
Since the third control signal VST_PAM or the second control signal SPAM is simultaneously provided to the driving circuits 100 in different lines (e.g. the first sub-pixel line LN1 to the xth sub-pixel line LNx) by the display device 1000. Therefore, the first writing periods GW of the driving circuits 100 in different lines (e.g. the first sub-pixel line LN1 to the xth sub-pixel line LNx) are at the same time.
Since the sixth control signal VST(1)˜VST(x) (not shown) or the fourth control signal SP(1)˜SP(x) (not shown) are progressively provided to the driving circuits 100 in different lines (e.g. the first sub-pixel line LN1 to the xth sub-pixel line LNx) by the display device 1000. Therefore, the second writing periods PW of the driving circuits 100 in different lines (e.g. the first sub-pixel line LN1 to the xth sub-pixel line LNx) are at different time phases.
Since the sweep signals Sweep(1)˜Sweep(x) (not shown), the fifth control signals Emi_PWM(1)˜Emi_PWM(x) (not shown) or the seventh control signal Emi_PAM˜Emi_PAM(x) are progressively provided to the driving circuits 100 in different lines (e.g. the first sub-pixel line LN1 to the xth sub-pixel line LNx) by the display device 1000. Therefore, the reset and emission periods EM1˜EMa of the driving circuits 100 in different lines (e.g. the first sub-pixel line LN1 to the xth sub-pixel line LNx) are at different time phases.
Summary, the third control signal VST_PAM or the second control signal SPAM is simultaneously provided to the driving circuits 100 in different lines (e.g. the first sub-pixel line LN1 to the xth sub-pixel line LNx) by the display device 1000, such that the first data signals VPAM_R/G/B are simultaneously written into the driving circuits 100 in different lines (e.g. the first sub-pixel line LN1 to the xth sub-pixel line LNx). Furthermore, since the display device 1000 only provides the third control signal VST_PAM and the second control signal SPAM to write the first data signals VPAM_R/G/B into the riving circuits 100 in different lines (e.g. the first sub-pixel line LN1 to the xth sub-pixel line LNx), the circuits for generating the control signals can be decrease.
Since the first control circuit 110 of the driving circuit 100 can be implemented by the pulse amplitude adjustment circuit, and the second control circuit 120 can be implemented by the pulse width adjustment circuit. Therefore, the driving circuit 100 can control the gray level of the light emitting element better by controlling the pulse width of the driving current. And, the sweep signals Sweep(1)˜Sweep(x) (not shown) are progressively provided to the riving circuits 100 in different lines (e.g. the first sub-pixel line LN1 to the xth sub-pixel line LNx) by the display device 1000, such that the second writing period PW of each of the driving circuits 100 may not be limited by others, and each of the driving circuits 100 generates the driving current in its own reset and emission periods EM1˜EMa, in order to increase the ratio can be occupied by the reset and emission period EM in one frame.
In some usual cases, the driving circuit of part of the display device needs more transistors (e.g. 18 transistors) to achieve the effects similar with the driving circuit 100 of the present disclosure. In contrast, the driving circuit 100 of the present disclosure only utilizes 15 transistors to achieve the aforementioned operations, therefore the circuit area is relatively small, and the manufacturing cost can be decreased. In additional, in some usual cases, the driving current of the driving circuit of part of the display device has longer falling time (e.g. 18.9 μs). In contrast, the falling time of the driving current of the driving circuit 100 of present disclosure is shorter (e.g. 16.7 μs), and therefore the image uniformity of the display device 1000 in the low gray level can be increased.
And, in the second period P2, the first control circuit 110 of the display device 1000 can compensate the threshold voltage of the first transistor T1. In the fourth period P4, the second control circuit 120 can compensate the threshold voltage of the eighth transistor T8, and therefore the deviation from the pulse amplitude of the driving current caused by the variety in threshold voltage of the first transistor T1 generated from manufacture can be decreased, and the deviation from the pulse width of the driving current caused by the variety of threshold voltage of the eighth transistor T8 generated from the manufacture can be decreased, in order to increase the image uniformity.
Reference is made to
The first control circuit 210 is electrically coupled to a gate terminal of the first transistor T1, and the first control circuit 210 is configured to adjust pulse amplitude of a driving current generated the driving circuit 200. The second control circuit 220 is electrically coupled to a gate terminal of the second transistor T2, and the second control circuit 220 is configured to adjust a pulse width of the driving current generated the driving circuit 200. The reset circuit 230 is electrically coupled to the gate terminal of the second transistor T2, and the reset circuit 230 is configured to reset the voltage level at the gate terminal of the second transistor T2.
The first transistor T1, the second transistor T2, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, the first control circuit 210, the second control circuit 220 and the reset circuit 230 of the driving circuit 200 of the embodiment shown in
In contrast with the driving circuit 100 of the embodiment shown in
Specifically, reference is made to
Reference is made to
The first control circuit 310 is electrically coupled to a gate terminal of the first transistor T1, and the first control circuit 310 is configured to adjust pulse amplitude of the driving current generated by the driving circuit 300. The second control circuit 320 is electrically coupled to a gate terminal of the second transistor T2, and the second control circuit 320 is configured to adjust pulse width of the driving current generated by the driving circuit 300. The reset circuit 330 is electrically coupled to the gate terminal of the second transistor T2, and the reset circuit 330 is configured to reset the voltage level at the gate terminal of the second transistor T2.
The first transistor T1, the second transistor T2, the thirteenth transistor T13, the fifteenth transistor T15, the first control circuit 310, the second control circuit 320 and the reset circuit 330 of the driving circuit 300 of the embodiment shown in
In contrast with the driving circuit 100 of the embodiment shown in
Specifically, reference is made to
Reference is made to
In contrast with the driving circuit 100 of the embodiment shown in
Reference is made to
In contrast with the driving circuit 200 of the embodiment shown in
Reference is made to
In contrast with the driving circuit 300 of the embodiment shown in
And, the second control circuit 620 includes a seventh transistor T7 and a third capacitor C3. A first terminal of the seventh transistor T7 is configured to receive a corresponding one of the second data signals Vsig(m)_R/G/B. A second terminal of the seventh transistor T7 is electrically coupled to a second terminal of the third capacitor C3 and a gate terminal of the eighth transistor T8. A gate terminal of the seventh transistor T7 is configured to receive the fourth control signal SP(n). A first terminal of the third capacitor C3 is configured to receive the sweep signal Sweep(n). In contrast with the driving circuit 300 of the embodiment as shown in
Summary, the display device 1000 simultaneously provides the first data signals VPAM_R/G/B to the driving circuits 100 in different lines. In additional, the display device 1000 progressively provides the sweep signals Sweep(n) to the driving circuits 100 in different lines such that the emission periods of the driving circuit 100 in different lines has different time phase, in order to increase the ratio occupied by the emission period in one frame. And, the pulse width of the driving current flowing through the light emitting element L1 is adjusted to control the gray level, in order to increase the image uniformity of the display device.
Although specific embodiments of the disclosure have been disclosed with reference to the above embodiments, these embodiments are not intended to limit the disclosure. Various alterations and modifications may be performed on the disclosure by those of ordinary skills in the art without departing from the principle and spirit of the disclosure. Thus, the protective scope of the disclosure shall be defined by the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 110101013 | Jan 2021 | TW | national |
This application claims priority to U.S. Provisional Application Ser. No. 63/090,333 filed Oct. 12, 2020, and Taiwan Application Serial Number 110101013, filed Jan. 11, 2021, the disclosures of which are incorporated herein by reference in their entireties.
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| Number | Date | Country | |
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| 20220114951 A1 | Apr 2022 | US |
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| 63090333 | Oct 2020 | US |
