DRIVING STRUCTURE FOR DISPLAY PANEL

Information

  • Patent Application
  • 20230410722
  • Publication Number
    20230410722
  • Date Filed
    December 30, 2022
    a year ago
  • Date Published
    December 21, 2023
    9 months ago
Abstract
The present application discloses a driving architecture for display panel, which comprises a plurality of drivers and a plurality of driving groups. Each driver includes an enable input terminal and is coupled to at least one display element of a display panel. The driving groups are disposed on the display panel and mutually coupled in series. Each driving group includes the drivers, the enable input terminals of the drivers of at least one driving group are mutually coupled for mutually transmitting an enable signal, and the enable signal is configured to drive the drivers. The driving architecture according to the present application is applied to the display panel, the number of signal lines may be reduced effectively, the normal operation of the display panel may be maintained, and the usage lifetime of the display panel may be extended.
Description
FIELD OF THE INVENTION

The present application is related to a driving architecture, in particular to a driving architecture for a display panel.


BACKGROUND OF THE INVENTION

Display devices have become an indispensable part of electronic products for displaying information. The display devices have been evolved from liquid crystal displays to mini-LED displays and micro-LED displays. Please refer to FIG. 1, which shows a schematic diagram of the driving architecture according to an embodiment of the prior art. As shown in the figure, the driving architecture according to the prior art is used for driving a display panel 10 to display images. The driving architecture comprises a controller 1, N rows of drivers 2_1, 2_2, . . . , 2_N, and enable signal lines 3. According to the present embodiment, N rows of drivers and the controller 1 are used to illustrate the driving architecture according to the prior art. The drivers 2_1, 2_2, . . . , 2_N and the controller 1 are disposed on the display panel 10. The controller 1 is coupled to and controls the N rows of drivers 2_1, 2_2, . . . , 2_N. According to an embodiment of the present application, the controller 1 may be an independent chip.


Each row of drivers includes a plurality of drivers. For example, the first row includes a plurality of drivers 2_1; the second row includes a plurality of drivers 2_2, and so on. The drivers 2_1, 2_2, . . . , 2_N disposed on the same column are mutually coupled. For example, the drivers 2_1, 2_2, . . . , 2_N disposed on the same column are mutually coupled by signal lines for transmitting pulse-width modulation (PWM) signals, input data (Din), clock signal (DCK), and enable signal (Enable). For convenience, according to the present embodiment, the enable signal lines 3 are used as an example for illustration. The controller 1 sends the enable signal via the enable signal line 3 to the drivers 2_1, 2_2, . . . , 2_N disposed on the same column. The display panel applying this driving architecture needs to include scan lines, which will increase the complexity of the structure of the display panel. In addition, the amount of the drivers 2_1, 2_2, . . . , 2_N disposed on the display panel 10 may be massive. If each driver is directly connected to the controller 1 by the enable signal line 3, there will be extremely numerous signal lines. Moreover, when one of the drivers is failed, the enable signal will not be transmitted to next one of the drivers, thereby, leading to failure of subsequent drivers by receiving no enable signal, the corresponding display elements also may not be driven.


Accordingly, the present application provides a driving architecture for display panel that may solve the above technical problem and simplify the structure of display panel.


SUMMARY OF THE INVENTION

An objective of the present application is to provide a driving architecture for a display panel, in which the driving architecture comprises a plurality of drivers and a plurality of driving groups. Each driver includes an enable input terminal and is coupled to at least one display element of the display panel. The driving groups are disposed on the display panel and mutually coupled in series.


The present application provides a driving architecture for a display panel, in which the driving architecture comprises a plurality of driving groups, which are disposed on the display panel and mutually coupled in series. Each driving group includes the drivers. The enable input terminals of the drivers of the at least one driving group are mutually coupled for mutually transmitting an enable signal. The drivers are driven by the enable signal. By adopting the driving architecture according to the present application to drive the display panel, the problem of inability of transmitting the enable signal to the next driver when one of the drivers fails may be solved and thus maintaining normal operations of the display panel and extending the usage lifetime of the display panel. Besides, since the enable input terminals of all drivers are not required to be mutually coupled, the number of signal lines may be reduced effectively and hence simplifying the driving architecture of the display panel.





BRIEF DESCRIPTION OF DRAWINGS


FIG. 1 shows a schematic diagram of the driving architecture according to an embodiment of the prior art;



FIG. 2 shows a schematic diagram of the driving architecture according to an embodiment of the present application;



FIG. 3 shows a block diagram of the drivers and the display elements according to an embodiment of the present application;



FIG. 4 shows a block diagram of the drivers in FIG. 3 according to an embodiment of the present application;



FIG. 5 shows a schematic diagram of the driving architecture according to an embodiment of the present application;



FIG. 6 shows a schematic diagram of the driving architecture according to an embodiment of the present application; and



FIG. 7 shows a schematic diagram of the driving architecture according to an embodiment of the present application.





DETAILED DESCRIPTION OF THE INVENTION

In order to make the structure and characteristics as well as the effectiveness of the present application to be further understood and recognized, the detailed description of the present application is provided as follows along with embodiments and accompanying figures.


In the specifications and subsequent claims, certain words are used for representing specific devices. A person having ordinary skill in the art should know that hardware manufacturers might use different nouns to call the same device. In the specifications and subsequent claims, the differences in names are not used for distinguishing devices. Instead, the differences in functions are the guidelines for distinguishing. In the whole specifications and subsequent claims, the word “comprising/including” is an open language and should be explained as “comprising but not limited to”. Besides, the word “couple” includes any direct and indirect electrical connection. Thereby, if the description is that a first device is coupled to a second device, it means that the first device is connected electrically to the second device directly, or the first device is connected electrically to the second device via other device or connecting means indirectly.


Please refer to FIG. 2, which shows a schematic diagram of the driving architecture according to an embodiment of the present application. The driving architecture according to the present application is used for driving a display panel 10 to display images. As shown in the figure, the driving architecture comprises a controller 20 and a plurality of driving groups 100_1, 100_2, . . . , 100_N. The controller 20 is coupled to the driving groups 100_1, 100_2, . . . , 100_N. Each of the driving groups 100_1, 100_2, . . . , 100_N includes a plurality of drivers 30_1, 30_2, . . . , respectively. For example, the driving group 100_1 includes a plurality of drivers 30_1; the driving group 100_2 includes a plurality of drivers 30_2, and so on. The arrangement direction of the driving groups 100_1, 100_2, . . . , 100_N is different from the arrangement direction of the drivers 30_1, 30_2, . . . , 30_N. The drivers 30_1, 30_2, . . . , 30_N disposed on the same column are coupled in series. For example, the drivers 30_1, 30_2, . . . , 30_N disposed on the same column are coupled in series by enable signal lines ENLine1, ENLine2, . . . , ENLineN. According to the present embodiment, N rows of driving groups and N rows of drivers are adopted for illustrating the driving architecture of the present application. The display panel 10 is a mini-LED or micro-LED display panel. Nonetheless, the driving architecture according to the present application is not limited to the above two types of display panel.


Please refer to FIG. 2 and FIG. 3. FIG. 3 shows a block diagram of the drivers and the display elements according to an embodiment of the present application. For convenience, only the drivers 30_1, 30_2 are shown in FIG. 3. The driving architecture according to the present application further comprises a pulse-width modulation (PWM) signal line PWMLine, a data line DLine, a clock signal line DCKLine, enable signal lines ENLine1, . . . , ENLine3, and at least one display element 40. The controller 20 is coupled to the drivers 30_1, 30_2 via the PWM signal line PWMLine, the data line DLine, and the clock signal line DCKLine. The drivers 30_1, 30_2 are coupled in series via the enable signal lines ENLine1, ENLine2.


The controller 20 transmits the PWM signal PWM1, the input data Din1, and the clock signal DCK to the drivers 30_1, 30_2 via the PWM signal line PWMLine, the data line DLine, and the clock signal line DCKLine. In addition, the controller 20 transmits the enable signal EN1 to the drivers 30_1 of the driving group 100_1 for driving the drivers 30_1 via the enable signal line ENLine1. Then, the drivers 30_1 generate and transmit the enable signal EN2 to the drivers 30_2 of the driving group 100_2 for driving the drivers 30_2. Following this sequence, at last, the drivers 30_N-1 of the driving group 100_N-1 transmit the enable signal ENN (not shown in the figure) to the drivers 30_N of the driving group 100_N and thus completing the enable operations for the whole display panel 10.


For example, refer to FIG. 3. The controller 20 transmits the enable signal EN1 to the driver 30_1 of the driving group 100_1 via the enable signal line ENLine1 for driving the driver 30_1. Then the driver 30_1 generates the enable signal EN2 to the next stage, the driver 30_2 of the driving group 100_2 for driving the driver 30_2, and so on. According to the present embodiment, each of the drivers 30_1, 30_2, . . . , 30_N includes an enable input terminal ENin and an enable output terminal ENout. Each of the drivers 30_1, 30_2, . . . , 30_N receives the enable signals EN1, EN2, . . . , ENN via the enable input terminal ENin and transmits the enable signals EN2, EN3, . . . , ENN via the enable output terminal ENout. According to another embodiment, the enable signal transmitted by the controller 20 via the enable signal line ENLine1 is also called the initial enable signal, indicating the first enable signal.


The drivers 30_1, 30_2 include at least one display element 40, respectively. According to the present embodiment, six display elements 40 are taken as an example. When the enable signal EN1 is transmitted to the driver 30_1 for enabling the driver 30_1, the driver 30_1 drives the six display elements 40 coupled to the driver 30_1 for driving the display elements 40 to emit light for displaying images. For example, each three display elements 40 may represent red, green, and blue (RGB) colors and form a pixel. According to the present embodiment, the display elements 40 may be mini LEDs or micro LEDs.


Please refer to FIG. 4, which shows a block diagram of the drivers in FIG. 3 according to an embodiment of the present application. As shown in the figure, the controller 20 is coupled to the drivers 30_1, 30_2 via the PWM signal line PWMLine, the data line DLine, and the clock signal line DCKLine. The drivers 30_1, 30_2 include an enable circuit 32, a storage circuit 34, and a driving circuit 36, respectively. The storage circuit 34 is coupled to the controller 20 and stores input data Din1 transmitted by the controller 20. The enable circuit 32 is coupled to the storage circuit 34 and enables the storage circuit 34 to receive the input data Din1. After the enable circuit 32 enables the storage circuit 34, the enable circuit 32 disables the storage circuit 34 and drives the enable circuit 32 of another driver of another driving group to enable the storage circuit 34 of that driver to receive the input data Din1 transmitted by the controller 20. For example, after the enable circuit 32 of the driver 30_1 enables the storage circuit 34, the enable circuit 32 disables the storage circuit 34 and drives the enable circuit 32 of the driver 30_2 of the driving group 100_2 to enable the storage circuit 34 of the driver 30_2 to receive the input data Din1 transmitted by the controller 20. The driving circuit 36 drives at least one display element according to the input data Din1.


Please refer to FIG. 5, which shows a schematic diagram of the driving architecture according to an embodiment of the present application. The driving architecture according to the present application is used for driving a display panel 10 to display images. As shown in the figure, the driving architecture for the display panel 10 comprises a controller 20, a plurality of drivers 30_1, 30_2, . . . , 30_N, and a plurality of driving groups 100_1, 100_2, . . . , 100_N. Each of the drivers 30_1, 30_2, . . . , 30_N comprises an enable input terminal ENin (as shown in FIG. 3) and is coupled to at least one display element 40 of the display panel 10 (as shown in FIG. 3 and FIG. 4). The driving groups 100_1, 100_2, . . . , 100_N are disposed on the display panel 10 and mutually coupled in series. Each of the driving groups 100_1, 100_2, . . . , 100_N includes the drivers 30_1, 30_2, . . . , 30_N. The enable input terminals ENin of all of the drivers 30_1, 30_2, . . . , of at least one of the driving groups 100_1, 100_2, . . . , 100_N are mutually coupled for mutually transmitting the enable signals (such as the enable signals EN1, EN2 shown in FIG. 3 and FIG. 4) for driving the corresponding drivers 30_1, 30_2, . . . , 30_N. For example, the enable signal EN1 drives the driver 30_1. The enable signal EN2 drives the driver 30_2, and so on. The Xth driving group receives the Xth enable signal ENX, where X is a positive integer greater than 1. The controller 20 transmits the enable signal EN1 (as shown in FIG. 4). At least one of the driving groups 100_1, 100_2, . . . , 100_N receives the enable signal EN1 for driving the drivers 30_2, . . . , 30_N of the at least one driving group. For example, the controller 20 transmits the enable signal EN1 to the drivers 30_1, 30_2, . . . , 30_N of the driving group 100_1 via the enable signal line ENLine1 for driving the drivers 30_1, 30_2, . . . , 30_N.


In the embodiment of FIG. 5, the signal transmission method for the PWM signal PWM1, the input data Din1, and the click signal DCK is the same as the one in the embodiment of FIG. 2. Hence, the details will not be described again. The enable input terminals ENin of the drivers 30_2, . . . , 30_N of the driving groups 100_1, 100_2, . . . , 100_N are mutually coupled, and the enable out terminals ENout of the drivers 30_1, 30_2, . . . , 30_N of the driving groups 100_1, 100_2, . . . , 100_N are mutually coupled. The controller 20 transmits the enable signal EN1 to the drivers 30_1, 30_2, . . . , 30_N of the driving group 100_1 via the enable signal line ENLine1 for driving the drivers 30_1, 30_2, . . . , 30_N. In the next driving stage, the drivers 30_1, 30_2, . . . , of the driving group 100_1 transmit the enable signal EN2 to the drivers 30_1, 30_2, . . . , of the driving group 100_2. In this manner, the drivers 30_1, 30_2, . . . , 30_N of the driving group 100_N are driven and hence completing the enable operations of the whole display panel According to an embodiment, the drivers 30_1, 30_2, . . . , 30_N of the driving groups 100_1, 100_2, . . . , 100_N may receive the enable signals EN1, EN2, . . . , ENN from the previous stage simultaneously or non-simultaneously for being driven simultaneously or non-simultaneously.


By using the connection method of the enable signal lines and the signal transmission method described above, the technical problem of inability of transmitting the enable signal to the next driver when one of the drivers fails may be solved and thus maintaining normal operations of the display panel and extending the usage lifetime.


Please refer to FIG. 6, which shows a schematic diagram of the driving architecture according to an embodiment of the present application. The difference between the embodiment in FIG. 6 and the one in FIG. 5 is that, according to the embodiment in FIG. 6, the driving groups 100_1, 100_2, . . . , 100_N includes an Xth driving group and a Yth driving group. The Z driving group difference is between the Xth driving group and the Yth driving group. The Z timing difference is between the timing of the Xth driving group receiving the Xth enable signal and the timing of the Yth driving group receiving the Yth enable signal. X, Y, and Z are positive integers greater 0; Y is greater than X. In FIG. 6, X is equal to 1; Y is equal to 3; and Z is equal to 1. The first and the third driving groups of the driving groups 100_1, 100_2, . . . , 100_N are the driving group 100_1 and the driving group 100_3. The driving group difference between the driving group 100_1 and the driving group 100_3 is one (the driving group 100_2). The driving group 100_1 and the driving group 100_3 receive the first enable signal EN1 and the third enable signal EN3 correspondingly with one timing difference. According to the pattern, the situation may be deduced to the driving group 100_N-2 and the driving group 100_N. According to the present embodiment, the enable signals EN1, EN3, . . . , ENN-2, ENN are transmitted by the controller 20.


According to an embodiment, the enable input terminals ENin of the drivers 30_1, 30_2, . . . , 30_N in the (X+1)th driving group are not mutually coupled. In FIG. 6, the enable input terminals ENin of the drivers 30_1, 30_2, . . . , 30_N in the second driving group 100_2 are not mutually coupled.


According to an embodiment, the enable input terminals ENin of the drivers 30_1, 30_2, . . . , 30_N in the (Y+1)th driving group are not mutually coupled. In FIG. 6, the enable input terminals ENin of the drivers 30_1, 30_2, . . . , 30_N in the fourth driving group 100_4 are not mutually coupled.


By using the connection method of the enable signal lines and the signal transmission method of the driving architecture described above, the technical problem of inability of transmitting the enable signal to the next driver when one of the drivers fails may be solved and thus maintaining normal operations of the display panel and extending the usage lifetime. Besides, since the enable input terminals of all drivers are not required to be mutually coupled, the number of signal lines may be reduced effectively and hence simplifying the driving architecture of the display panel.


Please refer to FIG. 7, which shows a schematic diagram of the driving architecture according to an embodiment of the present application. The difference between the embodiment in FIG. 7 and the one in FIG. 6 is that, according to the embodiment in FIG. 7, the enable input terminals ENin of the drivers 30_1, 30_2, . . . , 30_N in the (X+1)th driving group are mutually coupled. In FIG. 7, X is equal to 1; Y is equal to 3; and Z is equal to 1. The enable input terminals ENin of the drivers 30_1, 30_2, . . . , 30_N in the second driving group 100_2 are mutually coupled.


According to an embodiment, the enable input terminals ENin of the drivers 30_1, 30_2, . . . , 30_N in the (Y+1)th driving group are mutually coupled. In FIG. 7, the enable input terminals ENin of the drivers 30_1, 30_2, . . . , 30_N in the fourth driving group 100_4 are mutually coupled.


By using the connection method of the enable signal lines and the signal transmission method of the driving architecture described above, the technical problem of inability of transmitting the enable signal to the next driver when one of the drivers fails may be solved and thus maintaining normal operations of the display panel and extending the usage lifetime. Besides, since the enable input terminals of all drivers are not required to be mutually coupled, the number of signal lines may be reduced effectively and hence simplifying the driving architecture of the display panel.


Accordingly, the present application conforms to the legal requirements owing to its novelty, nonobviousness, and utility. However, the foregoing description is only embodiments of the present application, not used to limit the scope and range of the present application. Those equivalent changes or modifications made according to the shape, structure, feature, or spirit described in the claims of the present application are included in the appended claims of the present application.

Claims
  • 1. A driving architecture for a display panel, comprising: a plurality of drivers, each said driver including an enable input terminal, and each said driver coupled to at least one display element of said display panel; anda plurality of driving groups, disposed on said display panel and mutually coupled in series, each said driving group including said drivers, said enable input terminals of all said drivers of at least one of said driving groups mutually coupled for mutually transmitting an enable signal, and said enable signal driving said drivers.
  • 2. The driving architecture of claim 1, further comprising: a controller, transmitting said enable signal, at least one of said driving groups receiving said enable signal for driving said drivers in said at least one driving group.
  • 3. The driving architecture of claim 1, wherein a driver in one of said driving groups transmits said enable signal for driving another driver in another of said driving groups.
  • 4. The driving architecture of claim 2, wherein said driving groups include a first driving group adjacent to said controller and receiving said enable signal for driving said drivers in said driving group.
  • 5. The driving architecture of claim 2, wherein said driving groups include an Xth driving group, said Xth driving group receives the Xth enable signal; and X is a positive integer greater than 1.
  • 6. The driving architecture of claim 2, wherein said driving groups include an Xth driving group and a Yth driving group, a Z driving group difference is between said Xth driving group and said Yth driving group, a Z timing difference is between the timing of said Xth driving group receiving said enable signal and the timing of said Yth driving group receiving said enable signal, X, Y, and Z are positive integers greater than 0; and Y is greater than X.
  • 7. The driving architecture of claim 6, wherein said driving groups further include a (X+1)th driving group, and said enable input terminals of said drivers in said (X+1)th driving group are not mutually coupled.
  • 8. The driving architecture of claim 6, wherein said driving groups further include the (Y+1)th driving group; and said enable input terminals of said drivers in said (Y+1)th driving group are not mutually coupled.
  • 9. The driving architecture of claim 6, wherein said driving groups further include the (X+1)th driving group, and said enable input terminals of said drivers in said (X+1)th driving group are mutually coupled.
  • 10. The driving architecture of claim 6, wherein said driving groups further include the (Y+1)th driving group, and said enable input terminals of said drivers in said (Y+1)th driving group are mutually coupled.
  • 11. The driving architecture of claim 2, wherein each said driver includes: a storage circuit, coupled to said controller, and storing input data transmitted by said controller; andan enable circuit, coupled to and enabling said storage circuit for receiving said input data;wherein after said enable circuit enables said storage circuit, said enable circuit disables said storage circuit and drives said enable circuit of another driver in another driving group to enable said storage circuit of said another driver to receive said input data transmitted by said controller.
  • 12. The driving architecture of claim 1, wherein each said driver comprises: a driving circuit, driving said at least one display element according to input data.
  • 13. The driving architecture of claim 1, wherein an arrangement direction of said driving groups is different from an arrangement direction of said drivers.
Provisional Applications (1)
Number Date Country
63266199 Dec 2021 US