Patent Application
20130314307
This non-provisional application claims priority under 35 U.S.C. §119(a) on Patent Application No(s). 101118393 filed in Taiwan, R.O.C. on May 23, 2012, the entire contents of which are hereby incorporated by reference.
1. Technical Field
The disclosure relates to a driving system and method for a dot-matrix light-emitting diode (LED) display device, more particularly to a driving system and method for a dot-matrix light-emitting diode (LED) display device which is capable of eliminating anomalous bright points.
2. Related Art
The display device further comprises a controller 11, a scan line driver 12, and a signal line driver 13. The controller 11 provides the scan line control signal to the scan line driver 12 and provides the signal line control signal to the signal line driver 13. The scan line driver 12 provides the driving voltage to the scan lines WL0, WL1, WL2, WL3 . . . WLn-1 in response to the scan line control signal. The driving voltage is periodically provided to each scan line WL0, WL1, WL2, WL3 . . . WLn-1. At each time only one scan line is provided with the driving voltage. The signal line driver 13 provides the driving current to each signal line BL0, BL1, BL2, BL3 . . . BLm-1 in response to the signal line control signal. The driving current is used to drive the LEDs to emit light.
In the detailed circuit shown in
Because of the metal wire arrangement, each scan line WL0, WL1, WL2, or WL3 has the parasitic capacitor CW0, CW1, CW2, or CW3. Each signal line BL0, BL1, BL2, or BL3 has the parasitic capacitor CB0, CB1, CB2, or CB3.
The dot-matrix LED display device according to the prior art may generate anomalous bright points which are also called as ghost. When each lateral line of LEDs is lighted in turn, if the LEDs which should not emit light and are adjacent to the normally lighting LED emits light slightly, this phenomenon is called ghost. If the row of LEDs at the upper side of the normal LEDs does not emit light normally, this is called up-ghost. On the other hand, if the row of LEDs at the lower side of the normal LEDs does not emit light normally, this is called down-ghost.
The following will explain how the up-ghost is formed. When the scan line WL0 is drove, the switch K0 is conducted and the parasitic capacitor CW0 on the scan line WL0 is charged to the high voltage level approximate to the power supply source VBB. When the scan line is switched to the WL1 from WL0, the switch K0 is not in conduction while switches K1 and F2 are in conduction. The LED D12 is lighted. At this time, the voltage of the signal line BL2 connected to the cathode of the LED D12 changes to the low voltage level approximated to the ground voltage. The forward bias voltage on the LED D02 at this moment is greater than the conduction specified voltage, and thus the LED D02 is in conduction. The electric charge on the parasitic capacitor CW0 is discharged by the LED D02 and the switch F2. As a result, the LED D02 cannot emit light normally. Therefore, the up-ghost of the normal LED D12 is formed.
The following will explain how the down-ghost is formed. When the scan line WL0 is drove and the switches K0 and F3 are in conduction, the LED D03 is lighted. At this time, the parasitic capacitor CB3 on the signal line BL3 has the low voltage level approximate to the ground voltage. When the scan line is switched to WL1 from WL0, the switch K0 is not in conduction while the switch K1 is in conduction. The scan line WL1 connected to the anode of the LED D13 has the high voltage level approximate to the power supply source VBB. The forward bias voltage on the LED D13 at the moment is greater than the conduction specified voltage, and thus the LED D13 is in conduction. The parasitic capacitor CB3 is charged by the LED D13. As a result, the LED D13 cannot emit light normally. The down-ghost of the normal LED D03 is formed.
In the prior art, additional circuits are designed to eliminate the anomalous bright points.
Therefore, the additional ghost eliminating circuits will add the circuit cost. Furthermore, the resistors used in the ghost eliminating circuit 21 as shown in
In one aspect, a driving system for a dot-matrix light-emitting diode (LED) display device is disclosed. The driving system is used to drive a display panel comprising a plurality of LEDs. Each LED is disposed at intersections drive a display panel comprising a plurality of LEDs. The driving system comprises a controller, a scan line driver, and a signal line driver. The controller is used to provide a scan line control signal and a signal line control signal. The scan line driver is used to generate a scan line driving signal to drive the plurality of the scan lines in response to the scan line control signal. The scan line driving signal is divided into an ON period and a OFF period. The signal line driver is used to generate a signal line driving signal in response to the signal line control signal. The signal line driving signal drives the plurality of LEDs to emit light during the ON period. The signal line driver generates a charging or discharging control signal during the OFF period so that the signal line driver and the plurality of signal lines form a plurality of discharging paths through which parasitic capacitors on the plurality of scan lines are discharged or the signal line driver and the plurality of signal lines form a plurality of charging paths through which parasitic capacitors on the plurality of signal lines are charged.
In another aspect, a driving method for a dot-matrix light-emitting diode (LED) display device is disclosed. The driving method is used to drive a display panel which comprises a plurality of LEDs. Each LED is disposed at intersections of a plurality of scan lines and a plurality of signal lines. The driving method comprises providing a scan line control signal and a signal line control signal, generating a scan line driving signal in response to the scan line control signal, generating a signal line driving signal in response to the signal line control signal, and generating a charging or discharging control signal during the OFF period so that the plurality of signal lines form a plurality of discharging paths through which parasitic capacitors on the plurality of scan lines are discharged or the signal line driver and the plurality of signal lines form a plurality of charging paths through which parasitic capacitors on the plurality of signal lines are charged The scan line driving signal is divided into an ON period and a OFF period. The signal line driving signal drives the plurality of LEDs to emit light during the ON period. The plurality of LEDs do not emit light during the OFF period.
The present disclosure will become more fully understood from the detailed description given herein below for illustration only, and thus are not limitative of the present disclosure, and wherein:
In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawing.
The detailed characteristics and advantages of the disclosure are described in the following embodiments in details, the techniques of the disclosure can be easily understood and embodied by a person of average skill in the art, and the related objects and advantages of the disclosure can be easily understood by a person of average skill in the art by referring to the contents, the claims and the accompanying drawings disclosed in the specifications.
The dot-matrix LED display comprises a display panel 30 comprising a plurality of LEDs D00-D33, as shown in
As described in the prior art, because of the metal wire arrangement, each lateral scan line WL0, WL1, WL2, or WL3 has a parasitic capacitance CW0, CW1, CW2, or CW3 respectively, and each vertical signal line BL0, BL1, BL2, and BL3 has parasitic capacitance CB0, CB1, CB2, or CB3 respectively.
The dot-matrix LED display further comprises a controller 31, a scan line driver 32, and a signal line driver 33. The controller 31 provides a scan line control signal and a signal line control signal.
The scan line driver 32 generates the scan line driving signal to the scan lines WL0, WL1, WL2, WL3 in response to the scan line control signal. The scan line driving signal is periodically provided to each scan line WL0, WL1, WL2, or WL3. At each time only one scan line is provided with the driving voltage. The scan line driving signal is divided into an ON period and a OFF period. As shown in
The signal line driver 33 generates the signal line driving signal to the signal lines BL0, BL1, BL2, and BL3 in response to the signal line control signal. During the ON period of each scan line driving signal, the signal line driving signal drives the plurality of LEDs on each signal line to emit light. On the other hand, during the OFF period of each scan line driving signal, the signal line driving signal does not drive the plurality of LEDs on each signal line to emit light.
In the embodiments of the disclosure, the signal line driver 33 does not only provide the signal line driving signal, but also provides the discharging control signals DP0, DP1, DP2, DP3 and/or pre-charging control signals PP0, PP1, PP2, PP3 during the OFF period TDEAD of the scan line driving signal. In this case, the signal line driver 33 is further defined as the signal line driver which is of capable eliminating the anomalous bright points. The signal line driver 33 comprises a driving circuit, a discharging circuit, and a charging circuit. In an embodiment, a driving circuit and a discharging circuit may share a same circuit path, and additional logic gates are used to achieve the circuit path share. In another embodiment, an additional discharging circuit having the same components as the driving circuit is used.
As shown by the circuit of
As described above, the signal line driver 33 further comprises a discharging circuit and a charging circuit. The parasitic capacitors CW0, CW1, CW2, and CW3 are discharged by the discharging circuit. The parasitic capacitors CB0, CB1, CB2, and CB3 are charged by the charging circuit. In an embodiment, the discharging circuit can share with the driving circuit, as shown in
The discharging circuit sharing with the driving circuit comprises not only the switches F0, F1, F2, and F3, but also the current sources J0, J1, J2, and J3 respectively connected to the switches F0, F1, F2, and F3. The logic gates L0, L1, L2, and L3 generates control signals for controlling the switches F0, F1, F2, and F3 according to the signal line driving signals and the discharging control signals. In other words, each switch F0, F1, F2, or F3 is controlled by the signal SA0, SA1, SA2, or SA3 outputted from the logic gates L0, L1, L2, or L3. In this embodiment, all the logic gates may be OR gates. The two inputs of the logic gates L0, L1, L2, and L3 are inputted with the discharging control signals DP0, DP1, DP2, and DP3 and the signal line driving signal SF0, SF1, SF2, and SF3 respectively. Therefore, if one of the signal line driving signal (SF0, SF1, SF2, or SF3) and the discharging control signal (DP0, DP1, DP2, or DP3) is at a high voltage level, the logic gate will output a signal at a high voltage level to conduct the switch (F0, F1, F2, or F3). More particularly, if the signal line driving signal SF0, SF1, SF2, or SF3 is at a high voltage level, the logic gate L0, L1, L2, or L3 will output a signal at a high logic level to conduct the switch F0, F1, F2, or F3. At this time, the driving circuit instead of the discharging circuit is formed. If the discharging control signal DP0, DP1, DP2, or DP3 is at a high voltage level, the logic gate L0, L1, L2, or L3 will output a signal at a high logic level to conduct the switch F0, F1, F2, or F3. At this time, the discharging circuit instead of the driving circuit is formed.
Also with reference to
In the embodiment of
The detailed charging process and discharging process will be explained with reference to
Furthermore, the ON period TACTIVE is divided into three parts which are a first predetermined time period T5, a display time period TDISPLAY, and a second predetermined time period T7. For example, during the display time period TDISPLAY, when the n+1th line of LEDs is displayed, the switch SKn+1 will be open. After the first predetermined time T5, the switch Fn in the signal line driver 33 is conducted to drive the LED to emit light. The time period for emitting light is further defined as the display time period TDISPLAY. After the display time period and then the second predetermined time T7, all switches Kn will be closed to enter the OFF period TDEAD because a new line of scan line, for example, n+2 th line, will be scanned. The first predetermined time period T5 and the second predetermined time period T7 may be zero or non-zero. The length of the above mentioned time periods can be controlled.
The OFF period TDEAD is used for the discharging process and charging process of the parasitic capacitors. That is, the OFF period TDEAD is used to eliminate the up-ghost and down-ghost. It should be noted that the embodiment comprises eliminating both up-ghost and down-ghost. However, the disclosure is not limited this way. For example, an embodiment can only eliminate the up-ghost or the down-ghost.
The following will explain the process for eliminating up-ghost.
When a scan line is switched to be the next line, for example, from the nth line to the n+1 th line. During the OFF period TDEAD, after a first waiting time T0 of the OFF period TDEAD, the scan line driver outputs a discharging control signal. As a result, the logic gates L0, L1, L2, and L3 output the control signals SA0, SA1, SA2, and SA3 at a high voltage level to conduct one or more current switches Fn in the signal line driver for a first conduction time T1. At this time, the electric charge on the parasitic capacitor CWn on the nth scan line WLn is discharged by a discharging path which is formed by the signal line and the opening switch Fn in the current driving device. The discharged current is equal to the current value of the current source Jn. This discharge process is different from the discharge process by LEDs as described in the prior art. In the discharge process, the voltage of the parasitic capacitor CWn on the nth scan line WLn decreases, and the forward bias voltage of the LED connected to the nth scan line WLn is smaller than the conduction specified voltage of the LED. Thus, the up-ghost is eliminated.
The electric charge on the parasitic capacitor CWn can be discharged by the original discharge circuit in the signal line driver, as shown in
It should be noted that, the first waiting time T0 before generating the discharging control signal can be zero or non-zero. The length of the first waiting time can be controlled. In addition, the first conduction time T1 for the current switch Fn in the signal line driver can be zero or non-zero. The length of the first conduction time T1 is also can be controlled. Furthermore, the current of the current source Jn for the discharging process can be controlled.
The following will explain the process for eliminating the down-ghost.
After the first conduction time T1 and the second waiting time T2, one or more switches Gn in the signal line driver are in conduction for a second conduction time T3. At this time, because of the conduction of the switch Gn, the parasitic capacitor CBn on the vertical signal line BLn is charged to be at a high voltage level. The forward bias voltage of the LED connected to the n+1 th line of scan line WLn+1 is smaller than the conduction specified voltage of the LED. Thus, the down-ghost can be eliminated. Then, after the third waiting time T4, the display period for the next scan line (n+1)th line) will begin. The driving switch SKn+1 for the (n+1)th scan line will be open for the operation of the next scan line.
It should be noted that, the second waiting time T2 can be zero or non-zero. The second conduction time T3 can be zero or non-zero. The third waiting time T4 after the pre-charging process can be zero or non-zero. Furthermore, the second predetermined time T7 after displaying the LED image can be zero or non-zero. The length of the time mentioned above can be controlled.
During a period (T6) which is after the first conduction time T1 (i.e., after generating the discharging control signal) and before the end of the TDEAD, the state of the switch SKn+1 of the scan line does not influence eliminating the down-ghost. Thus, in the period T6 of the OFF period TDEAD, the plurality of scan lines can be drove or not to be drove. The time T6 can be zero or non-zero, and the length of the time can be controlled.
Based on the above, the signal line driver provides a discharging control signal or a charging control signal during the OFF period of the scan line driving signal. As a result, the signal line driver provides a discharging path in response to the discharging control signal or provides a charging path in response to the charging control signal. Furthermore, the parasitic capacitors on the plurality of scan lines can be discharged by the discharging path and the parasitic capacitors on the plurality of signal lines can be charged by the charging path.
The present disclosure provides a driving system for a dot-matrix light-emitting diode (LED) display which is capable of eliminating anomalous bright points (or called as up-ghost and down-ghost). The driving system configures a discharging circuit and/or a charging circuit in the signal line driving system. The control signals for controlling the discharging circuit and/or the charging circuit are generated during the time period when the LED does not emit light. As a result, the parasitic capacitors on the scan lines or the signal lines can be discharged or charged by the signal lines but not by LEDs. Therefore, the anomalous bright points can be eliminated.
Based on the embodiment disclosed as above, no additional circuits are needed to eliminate the up-ghost and down-ghost. In this case, the circuit cost can be reduced. Furthermore, LED does not need to carry the reverse bias voltage which is beyond the specified standard, and thus the service life of the LED is not impacted.
Note that the specifications relating to the above embodiments should be construed as exemplary rather than as limitative of the present invention, with many variations and modifications being readily attainable by a person skilled in the art without departing from the spirit or scope thereof as defined by the appended claims and their legal equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 101118393 | May 2012 | TW | national |
