Patent Application
20240364204
A current mode voltage converter controls the current delivered by the converter to a load to regulate the output voltage to the load. In lighter load conditions (e.g., the load draws less current), the converter causes its output current to decrease. Conversely, in heavier load conditions (e.g., the load draws more current). the converter causes its output current to increase. The converter responds to changes in load condition by causing corresponding changes in the magnitude of the current it provides to the load. For some current mode voltage converters, a change in load condition (e.g., the load transitions from a sleep state (light load condition) to a fully operational state (e.g., heavy load condition), or vice versa), the sudden change in load condition may result in a transient in the output voltage from the converter. For example, responsive to a change in load condition from a light load condition to a heavy load condition, the converter's output voltage may experience a temporary downward transient in which the output voltage decreases and then recovers back to its original level (also referred to as an undershoot), and responsive to a change in load condition from a heavy load condition to a light load condition, the converter's output voltage may experience a temporary upward transient in which the output voltage increases and then recovers back to its original level (also referred to as an overshoot).
A voltage regulator includes a transconductance amplifier having an input and an output. The input is coupled to a voltage regulator output. A droop compensation circuit is coupled to the output of the transconductance amplifier. The droop compensation circuit includes a voltage source circuit configured to cause a voltage at an output of the voltage regulator to change from a first voltage level to a second voltage level in response to a first change in a load condition and remain at the second voltage level until a second change in the load condition. The droop compensation circuit also is configured to cause the voltage at the output of the voltage regulator to change from the second voltage level back to the first voltage level in response to the second change in the load condition.
The same reference numbers or other reference designators are used in the drawings to designate the same or similar (either by function and/or structure) features.
Although two load conditions are depicted in
The example converter 100 in
The transconductance amplifier 120 has a negative (−) input, a positive (+) input, and an output 121. The voltage output terminal 115 from the converter 100 may be coupled to one of the inputs of the transconductance amplifier 120. The signal provided to the negative input of the transconductance amplifier 120 is a feedback (FB) signal. In one example, the voltage output terminal 115 may be coupled to the negative input of the transconductance amplifier 120, and, as such, the signal FB is the output voltage VOUT. In another example, the output voltage VOUT may be provided to a resistor divider, which divides down the output voltage to provide the signal FB to the negative input of the transconductance amplifier 120. The positive input of the transconductance amplifier 120 is coupled to a voltage source circuit 122, which provides a reference voltage, VREF, to the positive input of the transconductance amplifier.
The output 121 of the transconductance amplifier 120 is coupled to the PI controller 130 and to an input of the V2I converter 150. The output of the V2I converter 150 is coupled to an input of the LS replica circuit 160. The LS replica circuit 160 includes one or more NFETs that are smaller than the LS transistor. The LS replica circuit 160 produces LS_sw_sense and LS_gnd_sense signals to comparator 170. The output signal from comparator 170 is a valley_comp signal. Converter 100 implements valley current control of the current IL through inductor L1. Other examples of converters within the scope of this disclosure may implement peak current control, average current control, or other types of current control techniques.
The output of comparator 170 is coupled to a set (S) input of SR latch 180. The reset (R) input of SR latch 180 is coupled to a clock circuit and thus receives a clock signal CLK. The Q output of SR latch 180 provides the Buck_hs control signal and is coupled to an input of drivers 112.
The transconductance amplifier 120 produces an output current that is a function of the difference between the signal FB and the reference voltage VREF. The PI controller 130 includes a resistor R1 coupled in series with a capacitor C1 between the output 121 of the transconductance amplifier and the reference supply terminal 113. Ignoring, for the time being, droop compensation circuit 140, the current from the transconductance amplifier 120 flows through resistor R1 to charge capacitor C1. Upon signal FB settling to the reference voltage VREF, the current from the transconductance amplifier 120 ceases, and the voltage across the capacitor C1 and at the output 121 of the transconductance amplifier is voltage V_CTRL.
The V2I converter 150 converts voltage V_CTRL to a current I_CTRL. The LS replica circuit 160 transforms the I_CTRL current to a voltage signal so that the resistance variation of the LS transistor (e.g., due to gate driver voltage variations, temperature variations, process tolerances, etc.) can adjust the magnitude of control signals LS_sw_sense and LS_gnd_sense. The LS_sw_sense signal has the voltage information taken from the drain of the LS FET, and the voltage on the drain of the LS transistor is a function of inductor current L1. As noted above, the LS replica circuit 160 may include a scaled-down version of the LS transistor, which is used as resistive element to transform the I_CTRL to a suitable voltage signal. Comparator 170 forces the valley_comp signal to a logic high level in response to the LS_sw_sense signal being higher than the LS_gnd_sense signal, and logic low otherwise. The valley_comp signal (provided to the S input of SR latch 180) being logic high sets SR latch 180 thereby forcing its Q output signal Buck_hs logic high. Drivers 112 respond to a logic high assertion of the Buck_hs signal by turning on the HS transistor and turning off the LS transistor (with a small amount of dead-time to ensure both transistors are not on at the same time). A logic high assertion of the clock signal CLK to the R input of SR latch 180 resets the SR latch causing the Buck_hs signal to a logic low state. Drivers 112 respond to a logic low assertion of the Buck_hs signal by turning off the HS transistor and, with after a dead time, turning on the LS transistor.
Referring to
Another transient (overshoot) 227 occurs upon the change in the load condition from the higher load condition 203 to the lower load condition 205. The inductor current IL temporarily remains at the higher level which causes the upward increase in the output voltage VOUT. The increase in the output voltage causes the capacitor C1 to at least partially discharge thereby causing a decrease in the magnitude of voltage V_CTRL as indicated at 210. A lower magnitude of voltage V_CTRL causes the timing of the Buck_hs signal to change such that the drivers 112 turn on the HS transistor for a shorter period of time during each switching cycle thereby causing a decrease in the inductor current IL, which in turn causes a decrease in the output voltage VOUT.
The droop compensation circuit 140 helps to avoid the transients 222 and 227 upon the lighter-to-heavier load condition change and the heavier-to-lighter load condition change, respectively. In the example of
With the inclusion of the droop compensation circuit 140, in response to a change from a lighter load condition 201 to a heavier load condition 203, voltage V_CTRL increases as shown at 228, but the voltage at the output 145 of buffer 142 remains at the fixed voltage level equal to the voltage of the voltage source circuit 144. Accordingly, a potential difference develops across the series combination of resistors R1 and R2, and thus a current I1 flows from the output 121 of the transconductance amplifier 120, through resistors R1 and R2, and through buffer 142 to the reference supply terminal 113. The current I1 represents an increase in the output current from the transconductance amplifier 120. The transconductance amplifier 120 is the source of current I1. The output current I1 from the transconductance amplifier 120 is a function of the difference between the voltages on its positive and negative inputs. The voltage on the positive input of the transconductance amplifier 120 is a fixed voltage, VREF from voltage source circuit 122. In the steady state, the voltage on the negative input, the FB signal, is forced to decrease so that the transconductance amplifier 120 can supply the increased current I1. The FB signal is, or is derived from, the output voltage, VOUT, and thus output voltage VOUT is forced to decrease as shown at 235 in
In this description, the term “couple” may cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action: (a) in a first example, device A is coupled to device B by direct connection; or (b) in a second example, device A is coupled to device B through intervening component C if intervening component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.
As used herein, the terms “terminal”, “node”, “interconnection”, “pin” and “lead” are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to mean an interconnection between or a terminus of a device element, a circuit element, an integrated circuit, a device or other electronics or semiconductor component.
A circuit or device that is described herein as including certain components may instead be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and/or inductors), and/or one or more sources (such as voltage and/or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and/or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and/or the sources to form the described structure either at a time of manufacture or after a time of manufacture, for example, by an end-user and/or a third-party.
While the use of particular transistors is described herein, other transistors (or equivalent devices) may be used instead with little or no change to the remaining circuitry. For example, a field effect transistor (“FET”) (such as an n-channel FET (NFET) or a p-channel FET (PFET)), a bipolar junction transistor (BJT—e.g., NPN transistor or PNP transistor), an insulated gate bipolar transistor (IGBT), and/or a junction field effect transistor (JFET) may be used in place of or in conjunction with the devices described herein. The transistors may be depletion mode devices, drain-extended devices, enhancement mode devices, natural transistors or other types of device structure transistors. Furthermore, the devices may be implemented in/over a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN) or a gallium arsenide substrate (GaAs).
References may be made in the claims to a transistor's control input and its current terminals. In the context of a FET, the control input is the gate, and the current terminals are the drain and source. In the context of a BJT, the control input is the base, and the current terminals are the collector and emitter.
Circuits described herein are reconfigurable to include additional or different components to provide functionality at least partially similar to functionality available prior to the component replacement. Components shown as resistors, unless otherwise stated, are generally representative of any one or more elements coupled in series and/or parallel to provide an amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as the single resistor or capacitor.
While certain elements of the described examples are included in an integrated circuit and other elements are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features illustrated as being external to the integrated circuit may be included in the integrated circuit and/or some features illustrated as being internal to the integrated circuit may be incorporated outside of the integrated. As used herein, the term “integrated circuit” means one or more circuits that are: (i) incorporated in/over a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; and/or (iv) incorporated in/on the same printed circuit board.
Uses of the phrase “ground” in the foregoing description include a chassis ground, an Earth ground, a floating ground, a virtual ground, a digital ground, a common ground, and/or any other form of ground connection applicable to, or suitable for, the teachings of this description. In this description, unless otherwise stated, “about,” “approximately” or “substantially” preceding a parameter means being within +/−10 percent of that parameter or, if the parameter is zero, a reasonable range of values around zero.
Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.
