Claims
- 1. A method for configuring a dynamic random access memory (DRAM) memory cell comprising:
connecting a first circuit having a first transistor and a first capacitor to a first bitline BL and connecting a second circuit having a second transistor and second capacitor to a second bitline BL#; connecting a gate of said first transistor to a gate of second transistor; and connecting said first bit line BL and said second bit line BL# to a sense amplifier for measuring a binary bit from sensing a voltage difference between said first and second capacitor independent from a pre-charged bit-line voltage.
- 2. The method of claim 1 further comprising:
connecting said gate of said first transistor and said gate of said second transistor to a wordline WL.
- 3. A method for configuring a DRAM memory cell comprising:
forming two capacitors symmetrically disposed in said DRAM cell for storing electrical charges therein and detecting a binary bit based on a voltage difference between said two capacitors.
- 4. The method of claim 3 further comprising:
connecting a first transistor to said first capacitor for forming a first transistor capacitor circuit and connecting a second transistor to said second capacitor for forming a second transistor-capacitor circuit.
- 5. The method of claim 4 further comprising:
connecting said first transistor capacitor circuit to a first bitline BL and connecting said second transistor-capacitor circuit to a second bitline BL#; and connecting a gate of said first transistor to a gate of second transistor.
- 6. The method of claim 5 further comprising:
connecting said first bit line BL and said second bit line BL# to a sense amplifier for detecting said voltage difference independent of a pre-charged voltage to one of said first and second bit-lines.
- 7. The method of claim 6 further comprising:
connecting said gate of said first transistor and said gate of said second transistor to a wordline WL.
- 8. A dynamic random access memory (DRAM) memory cell comprising:
a first circuit having a first transistor and a first capacitor connected to a first bitline BL and a second circuit having a second transistor and a second capacitor connected to a second bitline BL#; and a gate of said first transistor connected to a gate of said second transistor a sense amplifier connected to said first bit line BL and said second bit line BL# for measuring a binary bit from sensing a voltage difference between said first and second capacitors independent from a pre-charged bit-line voltage.
- 9. The DRAM cell of claim 7 further comprising:
a wordline WL connected to said gate of said first transistor and said gate of said second transistor.
- 10. A DRAM memory cell comprising:
two capacitors symmetrically disposed in said DRAM cell for storing electrical charges therein and for detecting a binary bit based on a voltage difference between said two capacitors.
- 11. The DRAM memory cell claim 10 further comprising:
a first transistor connected to said first capacitor constituting a first transistor-capacitor circuit and a second transistor connected to said second capacitor constituting a second transistor-capacitor circuit.
- 12. The DRAM memory cell of claim 11 further comprising:
a first bitline connected to said first transistor-capacitor circuit and a second bitline connected to said second transistor-capacitor circuit; and a gate of said first transistor connected to a gate of second transistor.
- 13. The DRAM memory cell of claim 14 further comprising:
a sense amplifier connected to said first bit line BL and said second bit line BL# for detecting said voltage difference independent of a pre-charged voltage to one of said first and second bit-lines.
- 14. The DRAM memory cell of claim 12 further comprising:
a wordline connected to said gate of said first transistor and said gate of said second transistor.
- 15. A method for configuring a memory cell comprising:
connecting a first and a second capacitors to a sensing means provided for sensing a difference of electromagnetic characteristics between said capacitors.
- 16. The method of claim 15 further comprising:
connecting a first and second transistors each to one of said two capacitors to form a first and second transistor-capacitor circuits symmetrically disposed in said memory cell for storing electrical charges therein for detecting a binary bit based on a voltage difference between said two capacitors.
- 17. The method of claim 16 further comprising:
connecting said first transistor capacitor circuit to a first bitline BL and connecting said second transistor-capacitor circuit to a second bitline BL#; and connecting a gate of said first transistor to a gate of second transistor.
- 18. The method of claim 17 further comprising:
connecting said first bit line BL and said second bit line BL# to a sense amplifier for detecting said voltage difference independent of a pre-charged voltage to one of said first and second bit-lines.
- 19. The method of claim 17 further comprising:
connecting said gate of said first transistor and said gate of said second transistor to a wordline WL.
- 20. A memory cell comprising:
a first and a second capacitors connected to a sensing means provided for sensing a difference of electromagnetic characteristics between said capacitors.
- 21. A memory device comprising a plurality of memory cells wherein each of said memory cells further comprising:
a first and a second capacitors connected to a sensing means provided for sensing a difference of electromagnetic characteristics between said capacitors for detecting a data bit stored in said memory cell.
Parent Case Info
[0001] This is a Formal Application of a Provisional Application 60/322,477 filed on Sep. 13, 2001. The Provisional Patent Application 60/322,477 is a Continuous-In-Part (CIP) Application of a previously filed co-pending Application with Ser. No. 08/653,620 filed on May 24, 1996 and another co-pending application Ser. No. 08/805,290 filed on Feb. 25, 1997 and another co-pending application Ser. No. 09/753,635 filed on Jan. 2, 2001 by one of the inventors for this Formal CIP Application.
Provisional Applications (1)
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Number |
Date |
Country |
|
60322477 |
Sep 2001 |
US |