Dual edge pulse de-multiplexer with equalized path delay

Abstract

A pulse domain 1 to 2N demultiplexer has a (i) pair of N stage counters each of which is responsive to an incoming pulse train in the pulse domain, one of the counters being responsive to leading edges of the pulses in the incoming pulse train and the other one of the counters being responsive to trailing edges of the pulses in the incoming pulse train and (ii) a control logic responsive to the states through which the pair of counters count, the control logic including 2N gate arrangements, each of the 2N gate arrangements generating a output signal of the pulse domain 1 to 2N demultiplexer.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application is related to the technology disclosed in U.S. Pat. No. 7,515,084, the disclosure of which is hereby incorporated herein by reference.

This application is also related to the technology disclosed in U.S. patent application Ser. No. 14/144,903 filed Dec. 31, 2013 and entitled “Time Encoded Circuits and Methods and a Time Encoder Based Beamformer for Use in Receiving and Transmitting Applications”, the disclosure of which is hereby incorporated herein by reference.

TECHNICAL FIELD

This invention relates to a demultiplexer which is responsive to an incoming signal in this pulse domain.

BACKGROUND

The pulse domain (also known as the time domain) is becoming a more and more desirable domain for information encoding and/or transfer. In the analog domain signals are typically represented by both their amplitudes and shapes. In the digital domain, signals represent binary numbers and the intervals between the 1's and 0's of the digital information is typically regulated by a clock in the digital domain. The digital domain has both advantages and disadvantages compared to the analog domain. The digital domain is resistant to amplitude excursions which hamper the analog domain, but a digital domain signal is typically just an approximation of a corresponding analog signal. Information can be lost when an analog signal is digitized.

In contrast, in the pulse domain information (data) is encoded by pulses and it is the interval between successive pulses (and not their amplitudes) which encodes the information (data) being conveyed by a pulse domain signal. So a pulse domain signal has certain advantages over signals in either the digital or analog domains.

The present invention relates to a demultiplexer which demultiplexes a pulse domain signal applied thereto. The disclosed invention in it preferred embodiments utilizes circuits which are used in the prior art in the digital domain and therefore are typically regulated by a clock to transfer data from one gate of a circuit to a following gate. In the disclosed preferred embodiments the data is encoded by the timing of the pulses and therefore the gate operate asynchronously in the disclosed embodiments.

Additionally, with the increasing demands of low supply voltage and small feature size in modern semiconductor process technology used to make various circuits and gates, this inevitably introduces analog circuit design challenges, of which the limited voltage headroom and process-voltage-temperature (PVT) variation are the most noticeable ones. These analog circuit design challenges can impact the asynchronous circuits and gates used in the pulse domain. In the prior art, to combat these challenges, circuit design has trend to be digital-centric which uses a few analog circuits as reasonably possible.

However, researchers have been seeking an alternative domain to the analog domain which uses voltage amplitude (or similarly, the amount of current) to convey signal information. Several time-domain signal processing theories and algorithms, which utilize a voltage-to-time converter to transfer amplitudes (voltages) of input signals into either pulse-widths (in the pulse domain) or widths between spikes (spike domain) of a constant-amplitude asynchronous pulse train at outputs, and recovery the original input signals from the pulse domain or spike domain information, have been investigated and proposed.

When dealing with high speed/large input signals, the voltage-to-time converter has to run at high speed and generate the asynchronous pulse train outputs at high switching rates, which may not be processed directly by the following time-to-digital converter due to the semiconductor process limits noted above. Therefore, a pulse de-multiplexer that can extract all the pulse-widths of a high speed asynchronous pulse train into multiple relatively low speed channels to compensate the circuits speed gap in between the voltage-to-time converter and time-to-digital converter will be extremely useful and practical for the realization of time-domain signal processing theories and algorithms. This invention serves the purpose of such a pulse domain de-multiplexer.

BRIEF DESCRIPTION OF THE INVENTION

In one aspect the present invention relates to a one to 2N pulse domain de-multiplexer. The disclosed pulse domain de-multiplexer includes a pair of asynchronous counters, one of which is responsive to the leading edges of the pulses in an incoming pulse train (to change its count though N possible states) while the other counter is responsive to the trailing edges of the same pulses in the incoming pulse train (to change its count through the same N possible states). The changing of the counts in the two counters is detected by a control logic which has 2N output channels over which the pulses in the incoming pulse train are repeatedly demultiplexed.

The counters and the control logic can introduce variations in the timing of the pulses on the 2N output channels due to the process-temperature-voltage (PVT) variations in modern semiconductor process technology as noted above. Therefore, in another aspect the present invention proposes a hardware architecture and calibration algorithm that can de-multiplex the pulse widths of both rising-to-falling and falling-to-rising edges of a high speed asynchronous pulse train into multiple low speed channels, and equalize the path delays of each channel, which are introduced by the process-temperature-voltage (PVT) variations in modern semiconductor process technology. The proposed hardware architecture and calibration algorithm can work with all the voltage/amplitude-to-time converters, such as Pulse-Wdith-Modulation (PWM) controller, Time-Encode Machine (TEM), Asynchronous Pulse Processor (APP), and etc, to provide multiple asynchronous pulse trains with proper switching rates set by the technology limit to realize the theories and algorithms of time-domain signal processing.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1a is a schematic diagram the overall architecture of the proposed dual edge pulse de-multiplexer with equalized path delay.

FIGS. 1b and 1c show the state diagrams of the UP and DOWN counters depicted in the schematic diagram of FIG. 1a.

FIGS. 2a and 2b depict a preferred embodiment of the UP and DOWN counters depicted in the schematic diagram of FIG. 1a.

FIGS. 3a and 3b show the states through which the counters of FIGS. 2a and 2b respectively count.

FIG. 3c depicts an exemplary incoming asynchronous pulse train with the count states of the counters of FIGS. 2a and 2b associated therewith, while FIG. 3d conveys this information in a tabular format.

FIG. 4 is a schematic diagram of one embodiment of the control logic 200 of FIG. 1.

FIGS. 5a, 5b and 6 illustrate the proposed calibration algorithm and a circuit for calibration measurements, while FIGS. 5c and 5d show exemplary implementations for the TDC and TEM, respectively.

FIG. 7 depicts an alternative way of generating two exemplary output channel signals (Y_ch1 and Y_ch6) where the critical paths for those two output signals are time-wise different, thereby yielding a less desirable way of generating output channel signals.

FIG. 8a shows a generic schematic for the gate arrangement 202 in each channel of the CTRL Logic block 200.

FIG. 8b shows an alternative schematic to the one shown in FIG. 4 for the CTRL Logic block 200.

FIG. 9 depicts the flow chart of the calibration procedure.

DETAILED DESCRIPTION

FIG. 1a is a schematic of the overall architecture of the proposed dual edge pulse de-multiplexer with equalized path delay. The proposed dual edge pulse de-multiplexer can de-multiplex the pulse widths of both rising-to-falling and falling-to-rising edges of a relatively high speed (for example, 2 GHz or greater) incoming asynchronous pulse train into multiple relatively low speed channels, and equalize the path delays of each channel, which are introduced by the process-temperature-voltage (PVT) variations in modern semiconductor process technology. The schematic of FIG. 1a includes two counters (100_UP and 100_DOWN) and a control logic unit 200. The counters each have a CLK input which is coupled to the incoming pulse train.

FIGS. 1b and 1c show the state diagrams of the UP and DOWN counters (100_UP and 100_DOWN), respectively. Each counter has N states (V₁ through V_N) in addition to an initial state (0) after a power-on-reset (POR) occurs. The state of the UP counter 100_UP changes when the CLK asserts from logic 0 to logic 1 (rising-edge) as shown in FIG. 1b. The state of the DOWN counter 100_DOWN changes when the CLK de-asserts from logic 1 to logic 0 (falling-edge) as shown in FIG. 1c. FIG. 1d shows that the DOWN counter can be realized by cascading an inverter and an UP counter.

FIGS. 2a and 2b depict preferred embodiments of the UP and DOWN counters (100_UP and 100_DOWN), respectively for a 1-to-10 pulse de-multiplexer based on the architecture suggested herein. Each counter has three flip flops FF₁-FF₃ which, with the depicted OR gate in a feedback path, counts through five states as is generally shown by FIGS. 3a and 3b. The flip flops FF₁-FF₃ may be of a conventional clocked design. But it should be noted that they are not clocked by a clock signal CLK as are conventional flip flips, rather their CLK inputs are connected to the incoming pulse domain pulse train. The UP counter 100_UP changes state on rising (leading) edge transitions of the incoming pulse domain pulse train (signal CLK) as shown by FIG. 3a. The DOWN counter 100_DOWN goes through a similar sequence of states (shown in FIG. 3b), but the transitions occur on falling (trailing) edge transitions of the incoming pulse domain pulse train (from logic 1 to logic 0) instead of on the rising (leading) edges thereof. The two counters 100 are preferably identical to each other except for (i) the presence of an inverter INV in one of them (the inverter occurs at the front of the DOWN counter 100_DOWN in these embodiments) and (ii) the flop-flops reset to different values in order for them to follow the counting patterns shown in FIGS. 3a and 3b. Flip-flops FF₁-FF₃ of FIG. 2a all reset (on a Power on Reset) to a zero state, while flip-flop FF₃ of FIG. 2b resets (on a Power on Reset) to a one state and flip-flops FF₁ and FF₂ of FIG. 2b both reset (on a Power on Reset) to a zero state. FF₃ on FIG. 2b is drawn with a grey background in to help reflect this difference it how it resets compared to the other flip-flops of FIGS. 2a and 2b.

So each counter 100 automatically generates five (10 divided by 2) different values in this embodiment. After the power on reset, the output of the UP counter 100_UP (which has 5-states in this embodiment, excluding the power-on-reset state) becomes all zeros (Q_up=000) while the output of the DOWN counter 100_DOWN (which also has 5-states in this embodiment, excluding the power-on-reset state) becomes 001 (Q_down=001). Then when the signal CLK transitions from a logic 0 level to a logic 1 level (on the rising edge), the output of the UP counter 100_UP changes to Q_up=100. Every time when the signal CLK transitions from a logic 0 to logic 1 (on a rising or leading edge), the output Q_up changes and follows the sequence as shown in FIG. 3a. The DOWN counter follows the same sequence, except it does it when the signal CLK transitions from a logic 1 level to a logic 0 level (on the trailing or falling edge) and thus the output of the DOWN counter is labeled Q_down. By applying the incoming asynchronous pulse train to the CLK inputs of the UP and DOWN counters 100_UP and 100_DOWN (instead of a traditional clock signal), the output values of UP and DOWN counters change at the rising and falling edges of the pulse train, respectively.

So, upon a Power on Reset the UP counter 100_UP assumes a value of “000” while the DOWN counter 100_DOWN assumes a value of “001”. These values do not cause the gates 202₁-202₁₀ of FIG. 4 (or the alternative gate arrangement embodiments of FIG. 8b) to assert (become true) as no data has yet be detected in incoming pulse domain pulse train (signal CLK). But when the first pulse is detected after a Power on Reset, the UP counter 100_UP changes from its reset value of “000” to “100” (as mentioned above) due to the action of the OR gate in FIG. 2a. While the first pulse is being detected (its falling edge has yet to be encountered), the DOWN counter 100_DOWN is still at its reset value of “001”, and the gate arrangement 202₁ asserts the signal Ych1 as true while the other gate arrangements 202₂-202₁₀ remain at a false state. If the DOWN counter 100_DOWN had reset to a “000” (like the UP counter 100_UP does) then value the signal Ych1 would not be correctly asserted on the leading edge of the first pulse after a reset. On detection of the falling edge, the DOWN counter 100_DOWN changes from its reset value of “001” to “100” due to the action of the OR gate in FIG. 2b. The logic feedback implemented by the OR gates in FIGS. 2a and 2b conveniently cause the first state to be encountered by the counters to be a “100” state whether their reset value is a “000” or a “001”.

The number of states through which each counter counts is equal to one-half the number of channels in the de-multiplexer. So if the de-multiplexer has 2N channels CH1 (which carries signal Y_ch1) through CH2N (which carries signal Y_ch2N), then the number of states through which each of the two counters 100_UP and 100_DOWN count is then N. In this particular embodiment N is set equal to five and thus the de-multiplexer is a 1 to 10 demultiplexer with ten output channels CH1-CH10 carrying signals Y_ch1-Y_ch10. The relationship between the five states of each counter 100 (and their output values Q_up and Q_down) and the data output by the ten channels of the demultiplexer is depicted by FIG. 3c and also by the table of FIG. 3d. Since each counter 100 preferably counts through the same sequence, a limited number of the combinations for both counter output values Q_up and Q_down occur. These combinations of values of Q_up and Q_down are detected by control logic 200 that in combination with the counters 100 demultiplexes the incoming pulse widths onto the ten output channels CH1-CH10 with respective signals Y_ch1-Y_ch10. Generally speaking, for other embodiments (for example, when N has a different value) then the number of flip flops in each counter (arranged with appropriate feedback logic) equals either (i) log₂ (N) when N is equal to a power of the number 2 or (ii) equals ┌log₂ (N)+1┐ when N is otherwise. The ceiling function (┌ ┐) signifies that the calculated value is rounded up to the next whole integer/number.

As shown in FIGS. 3a and 3b, when the outputs values Q_up of the UP counter 100_UP and the outputs values Q_down of the DOWN counter 100_DOWN are “100” and “001”, respectively, the pulse width (from rising to falling edges) for channel 1 (Y_ch1) will be generated. The sample principle applies on the pulse-widths of CH2 to CH10. A logic minimization approach based on the truth table (see FIG. 3c) to implement the pulse-width extraction for each channel may lead to large variations on the path-delays of each channel. For example, Y_ch1 and Y_ch6 can be implemented by the schematic shown in FIG. 7, where the critical paths for Y_ch1 and Y_ch6 are (AND4+AND2) and (NOR4+AND2), respectively, are different. Therefore, the path-delays of Y_ch1 and Y_ch6 are different in that embodiment. Also, due to the different complexities of the gate (essentially the numbers of transistors), race conditions can occur since the time needed for their gates to react to their inputs may be different resulting in hiccups in the data being outputted. In order to overcome these disadvantages, the pulse-width extraction logic for each channel in CTRL Logic 200 is preferably implemented with the same number of asynchronously logic stages and the same number of asynchronously logic gates per channel as shown in FIG. 4 to minimize the path-delay difference within each channel. In this connection it should be noted that there are ten gate arrangements 202₁ through 201₁₀ each one of which is identical (except for the polarities of the bits from the counters 100) with gate arrangement 202₁ generating channel CH1 (Y_ch1), gate arrangement 2022 generating channel CH2 (Y_ch2), gate arrangement 2023 generating channel CH3 (Y_ch3), and so forth. Each gate arrangement 202 is of the same complexity so any delay in generating the outputs signals Y_ch1 through Y_ch10 will be independent of the channel. Additionally within each gate arrangement 202, the output gate (AND2) has two identical gates (AND3) connected to its inputs and therefor the propagation times through these gates in arrangements 202 should not be subject a race condition where the propagation time for the inputed signal form the counter is bitwise different. So this arrangement 202 minimizes that likelihood of a race condition arising at their outputs.

FIG. 8a shows a generic schematic for the gate arrangement 202 of each channel of the CTRL Logic block 200 in FIG. 1a. The schematic consists of two-level gate logics. The 1^st level are two L-input AND gates (AND gates with a number “L” inputs), each of which takes the outputs of the UP and DOWN counters 100_UP and 100_DOWN, respectively. The 2^nd level is a 2-input AND gate, which takes the outputs of the aforementioned two L-input AND gates. However, as the number of de-multiplexed channels (2N) increases, there may be a fan-in issue on the L-input AND gate since L is proportional to N as indicated in FIG. 8a. That issue can be resolved by replacing the L-input AND with a cascade of multiple small-number-input AND gates (e.g. 2-input AND gates). For example, FIG. 8b shows an alternative schematic to the one shown in FIG. 4 where each 3-input AND is replaced by three 2-input ANDs.

A static offset of pulse-width in each channel can exist due to the process-temperature-voltage (PVT) variations in semiconductor process technology. To help compensate for this static offset, FIGS. 5a-5d and 6 propose an approach to estimate this static measurement offset for each channel. Using CH1 as an example, when a constant (DC) input (d_k) is applied on the voltage-to-time converter (TEM in FIG. 6), a periodic pulse train will be generated, and the pulse width of positive and negative half-period (Δt₁ and Δt₂) can be derived analytically. Therefore, the static offset for a constant input (d_k) is calculated as (Δ₁)_dk=(Δt_CH1)_dk=(Δt₁)_dk where (Δt_CH1)_dk is the measurement value. By repeating the same procedure with various values of constant input (d_k), the static measurement offset for CH1 is estimated as

${\Delta }_1=\frac{1}{M}\sum _{k=1}^M{\left({\Delta }_1\right)}_{d_k}.$ The approach applies on CH2 to CH10. The static offsets (Δ₁, Δ₂, Δ₃, . . . ) of pulse-width measurements for each channel are generated as a result of PVT. The approach proposed in FIGS. 6a, 6b and 7 (and summarized in FIG. 9) is for estimating those offsets so the pulse-width measurement (Δt_CH1, Δt_CH2, Δt_CH3, . . . ) for each channel can be calibrated by subtracting those estimated offsets as needed.

FIGS. 5a, 5b and 6 illustrate the s calibration algorithm and a circuit for calibration measurements. As shown in FIG. 5a, the calibration procedure utilizes, a programmable DC source (PROG DC), a voltage-to-time (V2T) converter such as time-encoder machine (TEM) or pulse-width modulator (PWM), as well as a bank of time-to-digital converters (TDCs), each of which can measure the pulse-widths of the corresponding channel output of the CTR Logic 200 of FIG. 1a. FIG. 5c (from Raisanen-Ruotsalainen, Elvi; Rahkonen, T.; Kostamovaara, J., “An integrated time-to-digital converter with 30-ps single-shot precision,” Solid-State Circuits, IEEE Journal of Solid-State Circuits, vol. 35, no. 10, pp. 1507, 1510, October 2000) and FIG. 5d (from Lazar, A. A.; Toth, L. T., “Perfect recovery and sensitivity analysis of time encoded bandlimited signals,” IEEE Transactions on Circuits and Systems I: Regular Paper, vol. 51, no. 10, pp. 2060, 2073, October 2004) show the exemplary implementations for the TDC and TEM, respectively.

One of the most important features of such V2T (e.g. TEM) is that it can generate a periodic pulse train when a constant voltage (DC) is applied on its input. Furthermore, the value of this constant voltage input controls the duty cycle (the positive and negative pulse widths) of the periodic pulse train output. Given a known value of the DC input (d), the positive and negative pulse widths (Δt₁ and Δt₂) can be derived analytically. When applying the generated periodic pulse train to the 1-to-10 dual-edge pulse de-multiplexer, positive and negative pulse widths of the periodic input will appear at the odd channels (CH1, CH3, CH5, CH7 and CH9), and even channels (CH2, CH4, CH6, CH8 and CH10), respectively.

As shown in FIG. 5b, for the odd channels, their measurement values—Δt_CH1, Δt_CH3, Δt_CH5, Δt_CH7, Δt_CH9—should be the same and equal to Δt₁ if there is no PVT variation. However, the constant offsets—Δ₁, Δ₃, Δ₅, Δ₇, Δ₉—are incorporated into the measurement values of each odd channel, respectively when the PVT variations are involved. It makes the measurement values—Δt_CH1, Δt_CH3, Δt_CH5, Δt_CH7, Δt_CH9—not equal anymore. The calibration procedure computes the average of the measurement values—(Δt_CH1)_dk, (Δt_CH3)_dk, (Δt_CH5)_dk, (Δt_CH7)_dk, (Δt_CH7)_dk, (Δt_CH9)_dk—under the condition of applying d_k as the DC input, and denotes this average value as (Δt₁)_dk. The calibration procedure further estimates the constant offset—(Δ₁)_dk, (Δ₃)_dk, (Δ₅)_dk, (Δ₇)_dk, (Δ₉)_dk—for each odd channel under the same DC input (d_k) condition by using this average value (Δt₁)_dk. Using CH1 as an example, the (Δ₁)_dk is computed as (Δt_CH1)_dk—(Δt₁)_dk. The same operation applies on other odd channels (CH3 to CH9). The above procedure is repeated with respect to various DC input (d_k) values. Finally the estimated constant offset for each odd channel is computed as the average value of the estimated constant offsets with respect to each DC input (d_k). Using CH1 as an example, the estimated constant offset, Δ₁, is computed as

$\frac{1}{M}\sum _{k=1}^M{\left({\Delta }_1\right)}_{d_k}.$ The same computation applies on other odd channels (CH3 to CH9). The estimated constant offsets—Δ₁, Δ₃, Δ₅, Δ₇, Δ₉—will be used to calibrate the measurement values. Using CH1 as an example, the calibrated measurement value, Δt_CH1-CAL, is computed as Δt_CH1−Δ₁. The same computation applies on other odd channels (CH3 to CH9).

For the even channels (CH2, CH4, CH6, CH8, and CH10), their calibrated measurement values are obtained through the same approach described above. The calibration procedure for the even channels can be executed concurrently (in parallel) with the one for odd channels.

FIG. 9 depicts the flow chart of the suggested calibration procedure and summarizes the materials presented in the preceding five paragraphs. In FIG. 9, the control flow and the blocks of positive/negative pulse width computation, measurement average, constant offset estimation, constant offset estimation average, and measurement calibration are executed in the calibration engine (CAL ENG), which is shown in FIG. 5a, and can be implemented through a micro-controller/processor.

The use of this calibration procedure is optional in that the PVT variations may not be so significant in some applications to require that they be compensated for. PVT variations are undesirable and therefor occur unintentionally, but they can occur as an intrinsic artifact of modern semiconductor manufacturing technologies.

Testing results show that the asynchronous de-multiplexer disclosed herein can de-multiplex the pulse train with at least 2 GHz average pulse rates, counting both positive and negative pulses, so it is capable of high speed operation.

This concludes the description of embodiments of the present invention. The foregoing description of these embodiments and the methods of making same has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form or methods disclosed. Many modifications and variations are possible in light of the above teachings. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.

Claims

1. A pulse domain 1 to 2N demultiplexer comprising: i. a pair of N stage counters each of which is responsive to an incoming pulse train in the pulse domain, one of said counters being responsive to leading edges of the pulses in said incoming pulse train and the other one of said counters being responsive to trailing edges of the pulses in said incoming pulse train;ii. control logic responsive to the states through which said pair of counters count, the control logic including 2N gate arrangements, each of the 2N gate arrangements generating a output signal of said pulse domain 1 to 2N demultiplexer.

2. The pulse domain 1 to 2N demultiplexer of claim 1 wherein each of the N stage counters has two multi-bit outputs, one of which is in true logic (Q) and the other of which is in inverted logic (Q), different bits of the true logic (Q) and inverted logic (Q) being applied to each of the 2N gate arrangements so that each gate arrangement is responsive to one of the N possible counts of each of said N stage counters.

3. The pulse domain 1 to 2N demultiplexer of claim 2 wherein N=5 so the demultiplexer is a 1 to 10 demultiplexer and wherein the N stage counter responsive to leading edges of pulses in said incoming pulse train comprises three flip-flops with an up counter feedback circuit whereby the N stage counter responsive to leading edges in said incoming pulse train is arranged to count a through sequence of 100, 110, 111, 011, 001 in response to leading edges of pulses in said incoming pulse train and wherein the N stage counter responsive to trailing edges of pulses in said incoming pulse train comprises three flip-flops with a down counter feedback circuit whereby the N stage counter responsive to trailing edges in said incoming pulse train is arranged to count through a sequence of 100, 110, 111, 011, 001 in response to trailing edges of pulses in said incoming pulse train.

4. The pulse domain 1 to 2N demultiplexer of claim 2 wherein each of the 2N gate arrangements has an identical complexity in terms for the number and types of gates used to implement each of the 2N gate arrangements.

5. The pulse domain 1 to 2N demultiplexer of claim 1 in combination with a calibration algorithm for estimating a pulse width measurement offset to counteract process-temperature-voltage (PVT) variations occurring in semiconductor process technology.

6. The pulse domain 1 to 2N demultiplexer of claim 1 wherein said pair of counters are asynchronous counters each comprising a number of flip flops arranged with feedback logic, where the number of flip-flop equals either (i) log2(N) when N is equal to a power of 2 or (ii) equals ┌log2(N)+1┐ when N is otherwise.

7. The pulse domain 1 to 2N demultiplexer of claim 1 wherein said pair of counters are asynchronous counters each comprising three flip flops and wherein five of the flip flops in said two counters reset to a first state in response to a power up reset signal and wherein one of the flip flops in said two counters resets to a different state than said first state in response to said power up reset signal.

8. A method of demultiplexing a pulse domain signal with pulses having leading and trailing edges, a time interval between leading and trailing edges and/or between trailing and leading edges of pulses in said conveying information to be demultiplexed, said method comprising; a. detecting leading edges of the pulses in said pulse domain signal in a first circuit, the first circuit counting through a fixed number of different states in a fixed pattern in response to said leading edges of the pulses in said pulse domain signal;b. detecting trailing edges of the pulses in said pulse domain signal in a second circuit, the second circuit counting states in the same fixed number of different states in the same fixed pattern as the first circuit in response to said trailing edges of the pulses in said pulse domain signal;c. comparing the states of the first and second circuits and generating a number (2N) of different pulse domain output signals based on this comparing step, the different pulse domain output signals each corresponding to a demultiplexed version of said pulse domain signal.

9. The method of claim 8, wherein the number (2N) of different pulse domain output signals is equal to twice said fixed number.

10. The method of claim 8 wherein said comparing step is performed by 2N gate arrangements, each said gate arrangement being of equal complexity to each other gate arrangement so that each of the 2N of different pulse domain output signals is generated with a common amount of intentional time delay relative to said pulse domain signal.

11. The method of claim 10 in combination with a calibration algorithm for estimating a pulse width measurement offset for each of said 2N of different pulse domain output signals to counteract process-temperature-voltage (PVT) variations occurring in semiconductor process technology.

12. A circuit for demultiplexing a pulse domain signal, the pulse domain signals having pulses with leading and trailing edges, a time interval between leading and trailing edges and/or between trailing and leading edges of pulses in said conveying information to be demultiplexed, said method comprising; a. a first circuit for detecting leading edges of the pulses in said pulse domain signal, the first circuit counting through a fixed number of different states in a fixed pattern in response to said leading edges of the pulses in said pulse domain signal;b. a second circuit for detecting trailing edges of the pulses in said pulse domain signal, the second circuit counting states in the same fixed number of different states in the same fixed pattern as the first circuit in response to said trailing edges of the pulses in said pulse domain signal;c. logic means for comparing the states of the first and second circuits and generating a number (2N) of different pulse domain output signals based on this comparing step, the different pulse domain output signals each corresponding to a different demultiplexed version of said pulse domain signal.

13. The circuit of claim 12 wherein each of said first and second circuits comprises a number of flip flips connected in series with a feedback circuit so that the flip flops in said first and second circuits count through a predetermined sequence of states respectively in response to the leading and trailing edges of the pulses in said pulse domain signal.

14. The circuit of claim 13 wherein the logic means comprises 2N gate arrangements, each gate arrangement being responsive to a current state of each of said flip flops in said first and second circuits.

15. The circuit of claim 14 each said 2N gate arrangement are of equal complexity to each other so that each of the 2N of different pulse domain output signals is generated with a common amount of intentional time delay relative to the pulse domain signal being demultiplexed.