Embodiments of the present disclosure generally relate to the field of integrated circuits (IC), and more particularly, to connectors for dual-in-line memory modules (DIMMs).
In computer devices, a printed circuit board (PCB) or motherboard may be coupled to a plurality of connectors or slots to receive one or more smaller circuit boards or modules, such as a smaller PCB (daughterboard), e.g., dual in-line memory modules (DIMMs). A DIMM is a small circuit board that includes a plurality of electrical components, such as for example, dynamic random access memory (DRAM) integrated circuits. DIMM connectors may be designed for use on a PCB in a chassis of, e.g., platform devices, and/or including, e.g., personal computers, workstations, servers, and consumer products. As central processing unit (CPU) power increases significantly from generation to generation, additional and/or larger components, e.g., CPU heat sinks in the chassis (a metal enclosure or structure used to house a server) are often needed for additional cooling. When the space over the DIMMs is occupied by a heat sink or other component, however, difficulties accessing the DIMMs may occur due to the clearance required to remove or insert the DIMMs. The clearance required is due to the design of the connector, which typically includes raised ends on the opposite sides of the connector (often referred to as connector towers or module support towers), which also integrate a latch or extractor member. When the DIMM (or other daughterboard) is removed, the DIMM is typically ejected and lifted upwards to clear the connector and the latch.
Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings.
Embodiments described include apparatuses, methods, and systems related to a connector and latches to couple a memory module or board, e.g., a dual in-line memory module (DIMM), to a printed circuit board (PCB). In embodiments, a housing body of the connector includes first and second opposing ends coupled to respective first and second latches to engage the DIMM. In embodiments, the first and the second opposing ends have respective first and second heights having a connector tower height relative to a height of the housing body that allows the DIMM to be inserted or removed at an angle. In some embodiments, one or more of the latches are removably coupled to the connector and/or can be rotated into a lay-flat position to allow the DIMM to be removed at an angle.
In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that embodiments of the present disclosure may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.
In the following detailed description, reference is made to the accompanying drawings that form a part hereof, wherein like numerals designate like parts throughout, and in which is shown by way of illustration embodiments in which the subject matter of the present disclosure may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of embodiments is defined by the appended claims and their equivalents.
For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), (A) or (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
The description may use perspective-based descriptions such as top/bottom, in/out, over/under, and the like. Such descriptions are merely used to facilitate the discussion and are not intended to restrict the application of embodiments described herein to any particular orientation.
The description may use the phrases “in an embodiment,” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous.
The term “coupled with,” along with its derivatives, may be used herein. “Coupled” may mean one or more of the following. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other. The term “directly coupled” may mean that two or more elements are in direct contact.
As shown,
In the embodiment, DIMM 101A is coupled via a latch 105A (of a plurality of latches 105) of a connector 123A at a connector tower end 107 to a printed circuit board (PCB) 110. In embodiments that will be discussed further below, latch 105A may be a removably-coupled latch and/or lay-flat latch. Note that example chassis interior 100 includes volume 111 above first plurality of DIMMs 101. In the embodiment, chassis interior 100 also includes a volume 115 that may be a volume that accommodates a standard CPU heatsink. In embodiments, the connector tower end heights (note: a view of connector tower end is shown in more detail in
Accordingly,
To begin, as shown in
Referring now to
Referring now to
Referring now to
Referring now to
In some embodiments, electronic device 800 is enclosed in a chassis. In embodiments, electronic device 800 further includes a heatsink and the chassis includes a volume above a plurality of DIMMs including the DIMM.
In embodiments, a memory device mounted on the DIMM includes an NVM device, e.g., a byte-addressable write-in-place three dimensional crosspoint memory device, or other byte addressable write-in-place NVM devices (also referred to as persistent memory), such as single or multi-level Phase Change Memory (PCM) or phase change memory with a switch (PCMS), NVM devices that use chalcogenide phase change material (for example, chalcogenide glass), resistive memory including metal oxide base, oxygen vacancy base and Conductive Bridge Random Access Memory (CB-RAM), nanowire memory, ferroelectric random access memory (FeRAM, FRAM), magneto resistive random access memory (MRAM) that incorporates memristor technology, spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thyristor based memory device, or a combination of any of the above, or other memory.
In embodiments, DIMM is a double data rate (DDR) synchronous random-access memory (DDR SRAM) DIMM and/or the RAM components include a memory unit or medium including a cross-point memory array.
Note that a memory subsystem as described herein may be compatible with a number of memory technologies, such as DDR3 (Double Data Rate version 3, original release by JEDEC (Joint Electronic Device Engineering Council) on Jun. 27, 2007), DDR4 (DDR version 4, initial specification published in September 2012 by JEDEC), DDR4E (DDR version 4), LPDDR3 (Low Power DDR version3, JESD209-3B, August 2013 by JEDEC), LPDDR4) LPDDR version 4, JESD209-4, originally published by JEDEC in August 2014), WIO2 (Wide Input/Output version 2, JESD229-2 originally published by JEDEC in August 2014, HBM (High Bandwidth Memory, JESD325, originally published by JEDEC in October 2013, DDR5 (DDR version 5, currently in discussion by JEDEC), LPDDR5 (currently in discussion by JEDEC), HBM2 (HBM version 2), currently in discussion by JEDEC, or others or combinations of memory technologies, and technologies based on derivatives or extensions of such specifications.
Additionally, electronic device 800 may include mass storage devices 806 (such as diskette, hard drive, compact disc read-only memory (CD-ROM) and so forth), input/output (I/O) devices 808 (such as display, keyboard, cursor control and so forth) and communication interfaces 810 (such as network interface cards, modems and so forth). The elements may be coupled to each other via system bus 812, which may represent one or more buses. In the case of multiple buses, they may be bridged by one or more bus bridges (not shown). Each of these elements may perform its conventional functions known in the art. In particular, in some embodiments, memory 804 and mass storage devices 806 may be employed to store a working copy and a permanent copy of the programming instructions configured to perform one or more processes or memory/storage transactions for the electronic device 800. The programming instructions may be collectively referred to as controller logic 822. The various elements may be implemented by assembler instructions supported by processor(s) 802 or high-level languages, such as, for example, C, that can be compiled into such instructions.
The number, capability and/or capacity of the elements shown in
Otherwise, the constitutions of the elements shown in
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an” and “the” are intended to include plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Thus various example embodiments of the present disclosure have been described including, but not limited to:
Example 1 may include an apparatus, comprising: a connector to couple a dual in-line memory module (DIMM) to a printed circuit board (PCB), wherein the connector includes first and second opposing ends; and a housing body between the first and second opposing ends, wherein the housing body includes a top lengthwise edge to receive the DIMM and a bottom lengthwise edge to couple the DIMM to the PCB; and a first latch and a second latch coupled at the respective first and second opposing ends of the connector to engage the DIMM, wherein the first and the second opposing ends have respective first and second heights relative to a height of the housing body to allow the DIMM to be inserted or removed at an angle when disengaged from the first and second latch.
Example 2 may be the apparatus of Example 1, wherein the first and second heights include respective first and second connector tower end heights.
Example 3 may be the apparatus of Example 2, wherein the connector tower end heights are higher than the top lengthwise edge of the housing body by approximately 1-3 millimeters (mm).
Example 4 may be the apparatus of Example 1, wherein the first latch and the second latch are to engage the DIMM when the first latch and the second latch are in a perpendicular position relative to the PCB and to disengage the DIMM when the first latch and the second latch are in a lay-flat position relative to the PCB.
Example 5 may be apparatus of Example 4, wherein the perpendicular position is a substantially vertical position and the lay-flat position is a substantially horizontal position.
Example 6 may be the apparatus of Example 1, wherein the first latch and the second latch are removably coupled to the connector.
Example 7 may be the apparatus of Example 5, wherein the first latch and the second latch are removable from the connector after disengagement of the DIMM.
Example 8 may be the apparatus of Example 5, wherein the first latch and the second latch are rotatable to an unlock position prior to disengagement of the DIMM.
Example 9 may be the apparatus of any one of Examples 1-8, wherein the DIMM comprises a double data rate (DDR) synchronous random-access memory (DDR SRAM) DIMM.
Example 10 may be a method of coupling a dual in-line memory module (DIMM) to a printed circuit board (PCB), comprising aligning the DIMM with a top lengthwise edge of a housing body of a connector, wherein aligning the DIMM includes tilting the DIMM at an angle from horizontal; inserting the DIMM into the housing body of the connector to couple the DIMM to mating signaling connectors of the PCB; and engaging a latch coupled at an end of the connector to secure the DIMM to the PCB, wherein the end of the connector has a height relative to a height of the top lengthwise edge to allow the DIMM to be inserted or removed from the connector at the angle from the horizontal, when the DIMM is disengaged from the latch.
Example 11 may be the method of Example 10, wherein prior inserting the DIMM into the housing body, the method includes rotating the latch to an unlock position.
Example 12 may be the method of Example 10, wherein the end of the connector has a connector tower end height that is higher than the top lengthwise edge of the housing body by approximately 1-3 millimeters (mm).
Example 13 may be a system, comprising: a dual in-line memory module (DIMM); a printed circuit board (PCB); and a connector including: a housing body to couple the DIMM to the PCB, wherein the housing body includes a top lengthwise edge to receive the DIMM and a bottom lengthwise edge to couple the DIMM to the PCB; first and second opposing ends of the connector; and a first latch and a second latch coupled at the respective first and second opposing ends of the connector to engage the DIMM, wherein the first and the second opposing ends have respective first and second heights relative to the height of the housing body at the top lengthwise edge to allow the DIMM to be inserted or removed at an angle when disengaged from the first and second latch.
Example 14 may be the system of Example 13, wherein the first and second heights include first and second connector tower end heights that are higher than the top lengthwise edge of the housing body by approximately 1-3 mm.
Example 15 may be the system of Example 13, wherein the first and the second latches are to engage the DIMM when the latches are in a perpendicular position relative to the PCB and to disengage the DIMM when the latches are in a lay-flat position relative to the PCB.
Example 16 may be the system of Example 13, wherein the first and the second latches are removably coupled to the connector.
Example 17 may be the system of Example 16, wherein the first and the second latches are removable from the connector after disengagement of the DIMM.
Example 18 may be the system of Example 13, wherein the first latch and the second latches are rotatable to an unlock position prior to disengagement of the DIMM.
Example 19 may be the system of Example 13, further comprising a heatsink and a chassis including a volume above a plurality of DIMMs including the DIMM to fit the heatsink.
Example 20 may be the system of any of Examples 13-19, wherein the DIMM includes one or more byte-addressable persistent memory devices.
Various embodiments may include any suitable combination of the above-described embodiments including alternative (or) embodiments of embodiments that are described in conjunctive form (and) above (e.g., the “and” may be “and/or”). Furthermore, some embodiments may include one or more articles of manufacture (e.g., non-transitory computer-readable media) having instructions, stored thereon, that when executed result in actions of any of the above-described embodiments. Moreover, some embodiments may include apparatuses or systems having any suitable means for carrying out the various operations of the above-described embodiments.
The above description of illustrated implementations, including what is described in the Abstract, is not intended to be exhaustive or to limit the embodiments of the present disclosure to the precise forms disclosed. While specific implementations and examples are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure, as those skilled in the relevant art will recognize.
These modifications may be made to embodiments of the present disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit various embodiments of the present disclosure to specific implementations disclosed in the specification and the claims. Rather, the scope is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.