Patent Application
20050138288
The present invention generally relates to PC modular expansion devices for modular systems and more particularly to a dual mode USB and PCI Express device compatible with the ExpressCard™ architecture.
The ExpressCard™ architecture was unveiled in September, 2003 by the PCMCIA (Personal Computer Memory Card International Association). ExpressCard™ leverages two conventional serial buses, USB 2.0 and PCI Express, to achieve space reduction and enhanced performance.
ExpressCard™ modules will be available in two sizes; a 34 mm wide module generally designated 100 is shown in
The universal serial bus (USB) is a standard serial electrical interface within the ExpressCard™ standard. A pin out of an ExpressCard™ module 132 using only the USB interface is shown in
The PCI Express bus is a high speed standard serial electrical interface within the ExpressCard™ standard. A pin out of the ExpressCard™ module 500 using only the PCI Express interface is shown in
It is anticipated that ExpressCard™ modules will become popular in varied applications. While many mobile and desktop PC chipsets already include USB 2.0 and PCI Express busses, some hosts such as digital cameras may not support both interfaces. As such there is a need in the art for an ExpressCard™ module capable of providing either the USB 2.0 interface or the PCI Express interface on demand.
Flash memory has become an important means for storing data as such memory provides the advantage of mobility and non-erasability. Flash memory is an extremely useful way of storing data for portable devices such as handheld devices. The convenience that flash memory provides gives it numerous advantages over traditional mass storage devices such as hard disks. Besides portability, flash memory further offers advantages such as low power consumption, reliability, small size and high speed.
Flash memory is non-volatile which means that it retains its stored data even after power to the memory is turned off. This is an improvement over standard random access memory (RAM), which is volatile and therefore looses stored data when power is turned off.
In order to provide different functional requirements, current small-sized IA products, such as PDAs, industrial computers, digital cameras, and the like are commonly provided with an operating system, for example, Win CE/Linux. The hardware architecture of these devices requires a CPU and a NOR type flash memory for storing program code. If it is necessary to store data, a SRAM, or built-in NAND flash memory, or an external memory card is needed. These ways of storing data do not provide a standard interface to Win CE/Linux. In order to provide an interface a designer needs to modify the driving program or application program of these operating systems. These modifications require much effort and are costly when developing a new product.
As the number of mobile, portable, or handheld devices grows, the popularity of flash memory increases. The most common type of flash memory is in the form of a removable memory card such as an ExpressCard™ module. Removable cards allow the contents of the flash memory to be transferred easily between devices or computers.
Conventionally, when moving the flash memory card between devices, an additional host or adapter is required in order for the host to communicate with the flash card. Many devices may not have the built-in ability to connect to a flash card, therefore a special adapter or card must be installed in the host device. In addition, the bus architecture can limit the speed of data transfer between the host and flash memory device.
Therefore, there is a need for an ExpressCard™ module capable of providing either the USB 2.0 interface or the PCI Express interface on demand. Such a module preferably includes a flash memory device that can be directly connected to a host device without the need for special cables or adapters.
In accordance with one aspect of the invention, a flash memory device for connecting to an ExpressCard™ host includes at least one flash memory module, an ExpressCard™ connector for connecting to the ExpressCard™ host, a first serial interface coupled to the ExpressCard™ connector, and a controller coupled to the first serial interface and the at least one flash memory module.
In another aspect of the invention, a flash memory device for connecting to an ExpressCard™ host includes at least one flash memory module, an ExpressCard™ connector for connecting to the ExpressCard™ host, a PCI Express serial interface coupled to the ExpressCard™ connector, a USB serial interface coupled to the ExpressCard™ connector, and a controller coupled to the USB and PCI Express serial interfaces and the at least one flash memory module.
In yet another aspect of the invention, a flash memory device for connecting to an ExpressCard™ host includes at least one flash memory module, an ExpressCard™ connector for connecting to the ExpressCard™ host, a PCI Express serial interface coupled to the ExpressCard™ connector, a USB serial interface coupled to the ExpressCard™ connector, and a controller coupled to the USB and PCI Express serial interfaces and the at least one flash memory module, the controller comprising a microprocessor coupled to a FIFO system buffer, a flash memory controller, a RAM, and a ROM.
In yet another aspect of the invention, a flash memory device for connecting to an ExpressCard™ host includes at least one flash memory module having a boot state machine, an ExpressCard™ connector for connecting to the ExpressCard™ host, a PCI Express serial interface coupled to the ExpressCard™ connector, a USB serial interface coupled to the ExpressCard™ connector, and a controller coupled to the USB and PCI Express serial interfaces and the at least one flash memory module, the controller comprising a microprocessor coupled to a FIFO system buffer, a flash memory controller, and a RAM.
These and other features, aspects, and advantages of the present invention will become better understood with reference to the following drawings, description, and claims.
The following detailed description is of the best mode of carrying out the invention. The description is not to be taken in a limiting sense, but is made merely for the purpose of illustrating the general principles of the invention, since the scope of the invention is best defined by the appended claims.
Referring to
The controller 132 is a major component of the flash memory integrated circuit device 130. The controller 132 may control commands and data between the ExpressCard™ host and the flash memory integrated circuit device 130. The controller 132 may also manage data in the at least one flash memory chip 134. The controller 132 is preferably of a single chip design that does not need external ROM or RAM.
The controller 132 may perform numerous functions. The controller 132 may control the USB interface 11 and the PCI Express interface 12. The controller 132 follows the USB or the PCI Express specification for the electrical and logical protocols of each interface. The controller 132 may further comprise a FIFO controller buffer 146 (
When the ExpressCard™ host sends a write command, an interrupt may be generated and sent to a controller microprocessor 140 to inform the microprocessor 140 of the command and a command location. The microprocessor 140, for example a 8 or 16-bit microprocessor, is a major component of the controller 132. The microprocessor 140 may be implemented with an 8 bit 8051 machine. The microprocessor 140 may also be implemented with a 16 bit 80186 machine, a 32 bit ARM CPU, or a 32 or 64 bit MIPS CPU. The microprocessor 140 may read the commands and parameters from the register. The microprocessor 140 may also execute the commands with parameters. The microprocessor 140 may manage and map a FIFO address to the FIFO controller buffer 146 while receiving or transferring data to and from the ExpressCard™ host. Further, the microprocessor 140 may manage commands such as erase, program, or read for the at least one flash memory chip 134. In addition, the microprocessor 140 may execute an addressing method according to an algorithm of the controller 132.
The controller 132 may receive and transfer data to and from the ExpressCard™ host according to the USB or the PCI Express logical and electrical specification within the ExpressCard™ standard. The addressing method may include managing the flash memory erase, read, and write commands and managing the logical to physical mapping.
The controller 132 is the major component of the flash memory integrated circuit 130. The controller 132 may control commands and data between the ExpressCard™ connector 131 and the ExpressCard™ host and manage data in the at least one flash memory chip 134. Preferably the controller 132 is of a single chip design that does not need external ROM or RAM. A bus 133 between the at least one flash memory chip 134 and the controller 132 may be an 8 bit bus. Bus 133 may be a 8-bit, 16-bit, 32-bit or 64-bit bus.
Microprocessor ROM 141 may store program code of the controller 132 and may be built in the controller 132. Microprocessor RAM 142 may be a system RAM used by the controller 132 when executing commands or the controller algorithm. By eliminating the requirement for off-chip memory, the system cost is reduced.
FIFO controller buffer 146 may be used as a cache which may be provided for buffering between a USB Serial Engine 148 and a PCI Express Serial Engine 147 and a flash memory array controller 144. FIFO controller buffer 146 may also serve as the FIFO for each serial protocol. The microprocessor 140 may manage the addresses of the FIFO controller buffer 146. As required, the FIFO controller buffer 146 may be accessed by byte or word.
The flash memory array controller 144 may control the read and write commands to the at least one flash memory chip 134. Preferably, the flash memory array controller 144 is a pure hardware circuit.
An ECC circuit 145 encodes the ECC code while data is writing from the FIFO controller buffer 146 to the flash memory array controller 144 and decodes the ECC code while data is read from the flash memory array controller 144 to the FIFO system buffer 146. If an ECC error occurs, the ECC circuit 145 may determine the address in the buffer cache and correct the error.
As will be appreciated by those skilled in the art, data may flow in two directions. For writing to at least one flash memory chip 134, the data starts from the ExpressCard™ host. The data may move through one of the serial interfaces 11,12 and the ExpressCard™ connector 131 into one of the serial engines 147,148. The data may then be moved to the FIFO system buffer 146. From the FIFO system buffer 146, the data may be moved to the flash memory controller 144 and then to the at least one flash memory chip 134.
For reading from the at least one flash memory chip 134, first the data may be read out of the at least one flash memory chip 134 into the flash memory controller 260. Then the data may be moved into the FIFO system buffer 146. From the FIFO system buffer 146 the data may be moved to one of the serial engines 147,148. Finally, the data may be sent out through one of the serial interfaces 11,12 and the ExpressCard™ connector 131 to the ExpressCard™ host.
The FIFO system buffer 146 may be accessed in multiple ways. A first way may include using the microprocessor 140 to move the data. A second way may include a DMA block (not shown) for use in moving data between one of the serial engines 147,148 and the FIFO system buffer 146 or between the FIFO system buffer 146 and the flash memory controller 144. A third way may include making the serial engines 147,148 and the flash memory controller 144 a bus master and move data directly.
In order to increase the read speed, the FIFO system buffer 146 may be used as a cache. The data can be read ahead. Once the cache hit is detected for a read operation, the data in the cache can be supplied to the requester immediately. No flash memory read operation may be required.
Advantageously, the at least one flash memory chip 134 and controller 132 may be of single chip design to minimize the dimensions of the flash memory integrated circuit device 130 without the need of external RAM or ROM.
In an alternative embodiment of the present invention and with reference to
In operation, a first of the at least one flash memory chips 134 may have a PRE (Power-On-Read-Enable) pin activated. After power up, the microprocessor 140 may be put in reset mode. The boot state machine 151 may then be activated. The boot state machine 151 may monitor the Ready/Busy# signal from a first flash memory chip. When the signal indicates that the first flash memory chip is ready, the boot state machine 151 starts reading the pre-fetched data by using the normal read cycles. The read return data may be sent to the RAM 142. This conventionally means that the flash controller 144 may be a bus master of the local bus. The process continues until enough boot code is relocated from the first flash memory chip into RAM 142. Upon completion, the boot state machine 151 releases the microprocessor reset and the microprocessor 140 may start executing the code stored in RAM 142. The remaining code may be loaded by the microprocessor 140 using the boot load program stored in RAM 142.
In another alternative embodiment of the present invention, the at least one flash memory chip 134 may include a multi level cell (MLC) flash memory. Conventionally and as shown in
Typical flash memory uses single level cell (SLC) flash memory with Vt levels such as shown in
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
