Patent Application
20250038721
Aspects of the present disclosure relate generally to amplifiers, and, more particularly, to amplifiers for resistor calibration.
A chip may include one or more programmable on-chip resistors. For example, the one or more programmable on-chip resistors may be used in a voltage reference circuit for generating a reference voltage on the chip, a current reference circuit for generating a reference current on the chip, and/or another type of circuit. The one or more programmable on-chip resistors may also be used as termination resistors (e.g., to provide impedance matching in a front-end transceiver). The chip may also include a resistor calibration system configured to set the resistance of a programmable on-chip resistor to a desired resistance (e.g., based on the resistance of an external resistor).
The following presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an extensive overview of all contemplated implementations and is intended to neither identify key or critical elements of all implementations nor delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is presented later.
A first aspect relates to an apparatus. The apparatus includes a multi-stage amplifier and a feedback switch. The multi-stage amplifier includes a first amplifier having a first input, a second input, and an output, a second amplifier having an input and an output, wherein the input of the second amplifier is coupled to the output of the first amplifier, and a third amplifier having an input and an output, wherein the input of the third amplifier is coupled to the output of the first amplifier. The feedback switch is coupled between the output of the third amplifier and the second input of the first amplifier.
A second aspect relates to a method of operating a multi-stage amplifier, the multi-stage amplifier including a first amplifier having a first input and a second input, a second amplifier, and a third amplifier. The method includes, during a first phase, coupling an output of the third amplifier to the second input of the first amplifier, and driving an input of the third amplifier using an output of the first amplifier. The method also includes, during a second phase, driving an input of the second amplifier using the output of the first amplifier.
The detailed description set forth below, in connection with the appended drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.
The on-chip resistor 115 may be implemented with a network of resistors and switches in which the resistance of the on-chip resistor 115 is adjusted (i.e., tuned) by controlling the on/off states of the switches in the network. In other implementations, the on-chip may be implemented with a network of resistors and fuses in which the resistance of the on-chip resistor 115 is adjusted by controlling which fuses are blown in the network. It is to be appreciated that the on-chip resistor 115 is not limited to the above examples, and that the on-chip resistor 115 may be implemented with another type of programmable resistor.
The calibration system 110 includes a current source 150, a first switch 155, a second switch 160, a switched-capacitor amplifier 130, and a control circuit 140 (e.g., finite state machine (FSM)). The first switch 155 is coupled between the current source 150 and the external resistor 120, and the second switch 160 is coupled between the current source 150 and the on-chip resistor 115. The switched-capacitor amplifier 130 has a first input 132 coupled between the first switch 155 and the external resistor 120, a second input 134 coupled between the second switch 160 and the on-chip resistor 115, and an output 136.
The control circuit 140 is coupled to the output 136 of the switched-capacitor amplifier 130. The control circuit 140 is configured to control the on/off states of the first switch 155 and the second switch 160, and adjust the resistance of the on-chip resistor 115 (e.g., using a digital code labeled “RESCODE”) based on the output 136 of the switched-capacitor amplifier 130, as discussed further below. Each of the first switch 155 and the second switch 160 may be implemented with a transistor or another type of switch.
In certain aspects, the calibration system 110 calibrates the resistance of the on-chip resistor 115 as follows. During a first phase (also referred to as a calibration phase), the control circuit 140 closes (i.e., turns on) the first switch 155 and opens (i.e., turns off) the second switch 160. This causes the current of the current source 150 to flow through the external resistor 120, which generates a voltage drop across the external resistor 120 that is proportional to the resistance of the external resistor 120. The switched-capacitor amplifier 130 samples the voltage drop across the external resistor 120.
During a second phase (also referred to as a compare phase), the control circuit 140 opens the first switch 155 and closes the second switch 160. This causes the current of the current source 150 to flow through the on-chip resistor 115, which generates a voltage drop across the on-chip resistor 115 that is proportional to the resistance of the on-chip resistor 115. The switched-capacitor amplifier 130 samples the voltage drop across the on-chip resistor 115, and outputs a compare signal at the output 136 indicating whether the sampled voltage drop across the on-chip resistor 115 is greater than or less than the sampled voltage across the external resistor 120. Since the voltage drop across the on-chip resistor 115 is proportional to the resistance of the on-chip resistor 115 and the voltage drop across the external resistor 120 is proportional to the resistance of the external resistor 120, the compare signal indicates whether the resistance of the on-chip resistor 115 is greater than or less than the resistance of the external resistor 120.
The control circuit 140 receives the compare signal from the switched-capacitor amplifier 130, and adjusts (i.e., tunes) the resistance of the on-chip resistor 115 based on the compare signal. For example, if the compare signal indicates the resistance of the on-chip resistor 115 is less than the resistance of the external resistor 120, then the control circuit 140 may increase the resistance of the on-chip resistor 115.
The control circuit 140 may repeat the above process until the resistance of the on-chip resistor 115 is approximately equal to the resistance of the external resistor 120. For example, in some implementations, the compare signal may have a first logic value (e.g., one) when the resistance of the external resistor 120 is greater than the resistance of the on-chip resistor 115, and a second logic value (e.g., zero) when the resistance of the external resistor 120 is less than the resistance of the on-chip resistor 115. In this example, the control circuit 140 may repeat the above process until the compare signal flips logic values.
In the example shown in
The fourth switch 230 is coupled between the second input 134 of the switched-capacitor amplifier 130 and a first terminal 222 of the second capacitor 220. The fifth switch 235 is coupled between the first input 252 of the multi-stage amplifier 250 and the first terminal 222 of the second capacitor 220. A second terminal 224 of the second capacitor 220 is coupled to the second input 254 of the multi-stage amplifier 250. The sixth switch 240 is coupled between the output 256 of the multi-stage amplifier 250 and the second input 254 of the multi-stage amplifier 250.
Exemplary operations of the switched-capacitor amplifier 130 will now be discussed according to certain aspects.
During the first phase, the control circuit 140 closes the first switch 155, the third switch 225, the fifth switch 235, and the sixth switch 240, and opens the second switch 160 and the fourth switch 230. The configurations of the switches 155, 160, 225, 230, 235, and 240 during the first phase are shown in
During the second phase, the control circuit 140 opens the first switch 155, the third switch 225, the fifth switch 235, and the sixth switch 240, and closes the second switch 160 and the fourth switch 230. The configurations of the switches 155, 160, 225, 230, 235, and 240 during the second phase are shown in
The inverter 420 has an input 422 coupled to the output 416 of the OTA 410, and an output 424 coupled to the output 256 of the multi-stage amplifier 250. The inverter 420 is used to produce a rail-to-rail output swing at the output 256. In the example shown in
During the first phase, the multi-stage amplifier 250 operates in a closed loop. This is because the sixth switch 240 is closed during the first phase, and therefore couples the output 256 to the second input 254. Since the multi-stage amplifier 250 operates in a closed loop during the first phase, it is desirable for the multi-stage amplifier 250 to achieve a good stability margin (i.e., above 60 degrees) and a relatively high loop gain.
During the second phase, the multi-stage amplifier 250 operates as an open loop comparator since the sixth switch 240 is open during the second phase. During the second phase, it is desirable for the multi-stage amplifier 250 to provide the compare signal at the output 256 with a rail-to-rail swing to clearly indicate to the control circuit 140 (not shown in
A challenge with the multi-stage amplifier 250 is achieving both a good stability margin for the closed loop during the first phase and a rail-to-rail output swing during the second phase. For instance, the implementation in
To address the above, aspects of the present disclosure provide a multi-stage amplifier including separate output stages for the first phase and the second phase, in which the output stage for the first phase provides good loop stability and the output stage for the second phase provides a rail-to-rail output swing for the compare signal. In certain aspects, the output stage for the first phase includes a source-follower amplifier and the output stage for the second phase includes one or more inverters. The above features and other features of the present disclosure are discussed further below.
In this example, the multi-stage amplifier includes a first amplifier 510, a second amplifier 520, and a third amplifier 540. The first amplifier 510 provides a first-stage amplifier for the multi-stage amplifier 250 that drives both the second amplifier 520 and the third amplifier 540, as discussed further below. The first amplifier 510 may be implemented with a cascode amplifier or another type of amplifier. The first amplifier 510 has a first input 512 coupled to the first input 252 of the multi-stage amplifier 250, a second input 514 coupled to the second input 254 of the multi-stage amplifier 250, and an output 516.
The second amplifier 520 has an input 522 coupled to the output 516 of the first amplifier 510, and an output 524 coupled to the first output 550 of the multi-stage amplifier 250 (which is coupled to the control circuit 140). In certain aspects, the second amplifier 520 is configured to receive the output signal of the first amplifier 510 and generate a rail-to-rail signal at the first output 550 based on the output signal of the first amplifier 510, in which the rail-to-rail signal provides the compare signal to the control circuit 140 during the second phase.
For example, the rail-to-rail signal may swing between a voltage approximately equal to a supply voltage on a supply rail and a voltage approximately equal to a ground potential on a ground rail. In this example, the rail-to-rail signal provides a digital signal in which the supply voltage represents a logic one and the ground potential represents a logic zero. The logic one may indicate the resistance of the external resistor 120 is greater than the resistance of the on-chip resistor 115 and the logic zero may indicate the resistance of the external resistor 120 is less than the resistance of the on-chip resistor 115, or vice versa.
In the example shown in
The third amplifier 540 has an input 542 coupled to the output 516 of the first amplifier 510, and an output 544 coupled to the second output 555 of the multi-stage amplifier 250. In this example, the sixth switch 240 (also referred to as a feedback switch) is coupled between the output 544 of the third amplifier 540 and the second input 514 of the first amplifier 510. As a result, when the sixth switch 240 is closed during the first phase, the first amplifier 510 and the third amplifier 540 are coupled in the closed loop discussed above while the second amplifier 520 is outside of the closed loop. Because the second amplifier 520 is outside the closed loop during the first phase, the one or more inverters (e.g., inverters 532 and 534) in the second amplifier 520 have little to no effect on the stability margin of the loop. As a result, the first amplifier 510 and the third amplifier 540 are not restricted by the limitations placed on the stability margin due to the one or more inverters in the second amplifier 520. This allows the first amplifier 510 and the third amplifier 540 to achieve a good loop stability during the first phase. In contrast, in the amplifier design shown in
In the example shown in
In the example shown in
Thus, in this example, the second amplifier 520 provides rail-to-rail swing for the compare signal during the second phase, and the third amplifier 540 provides good loop stability during the first phase. Since the one or more inverters (e.g., inverters 532 and 534) in the second amplifier 520 are separate from the third amplifier 540, the one or more inverters are able to provide rail-to-rail output swing during the second phase while not affecting the stability margin of the closed loop during the first phase. In this example, the second amplifier 520 is used as a first output stage for the second phase to generate the compare signal, and the third amplifier 540 is used as a second output stage for the first phase to provide good stability in the closed loop configuration.
In the example in
The first amplifier 510 also includes a third transistor 720, a fourth transistor 725, a fifth transistor 730, a sixth transistor 735, a seventh transistor 740, an eighth transistor 745, a ninth transistor 750, and a tenth transistor 755. In this example, each of the transistors 720, 725, 730, and 735 is implemented with a respective NFET, and each of the transistors 740, 745, 750, and 755 is implemented with a respective PFET.
The sources of the third transistor 720 and the fourth transistor 725 are coupled to a ground. The drain of the third transistor 720 is coupled to the source of the fifth transistor 730, and the drain of the fourth transistor 725 is coupled to the source of the sixth transistor 735. The gates of the third transistor 720 and the fourth transistor 725 are biased by a first bias voltage (labeled “Vb1”). The gates of the fifth transistor 730 and the sixth transistor 735 are biased by a second bias voltage (labeled “Vb2”). The drain of the first transistor 710 is coupled between the drain of the third transistor 720 and the source of the fifth transistor 730, and the drain of the second transistor 715 is coupled between the drain of the fourth transistor 725 and the source of the sixth transistor 735.
The sources of the ninth transistor 750 and the tenth transistor 755 are coupled to a supply rail, the drain of the ninth transistor 750 is coupled to the source of the seventh transistor 740, the drain of the tenth transistor 755 is coupled to the source of the eighth transistor 745, and the gates of the ninth transistor 750 and the tenth transistor 755 are coupled to the drain of the seventh transistor 740. The drain of the seventh transistor 740 is coupled to the drain of the fifth transistor 730, the drain of the eighth transistor 745 is coupled to the drain of the sixth transistor 735, and the gates of the seventh transistor 740 and the eighth transistor 745 are biased by a third bias voltage (labeled “Vb3”). The output 516 of the first amplifier 510 is coupled between the drain of the sixth transistor 735 and the drain of the eighth transistor 745.
In this example, the folded cascode configuration provides the first amplifier 510 with a high output impedance, which translates into a high gain (e.g., for a high loop gain in the first phase). However, it is to be appreciated that the first amplifier 510 is not limited to a folded-cascode amplifier, and that the first amplifier 510 may be implemented with other amplifier configurations.
In some implementations, the multi-stage amplifier 250 may include switches to selectively enable/disable the amplifiers 510, 520, and 540. For example, the switches may be used to disable the amplifiers 510, 520, and 540 to prevent leakage current after resistor calibration is done and the calibration system 110 is placed into a low power mode.
In this example, the chip 820 includes a pad 830 for coupling the external resistor 120 to the chip 820. On the chip 820, the first switch 155 is coupled between the current source 150 and the pad 830, and the external resistor 120 is coupled to the pad 830. In the example shown in
In this example, the on-chip resistor 115 may be used in a voltage reference circuit integrated on the chip 820, a current reference circuit integrated on the chip 820, or another type of circuit integrated on the chip. The on-chip resistor 115 may also be used as a termination resistor (e.g., to provide impedance matching in a front-end transceiver integrated on the chip 820).
At block 910, during a first phase, an output of the third amplifier is coupled to the second input of the first amplifier. For example, the output (e.g., output 544) of the third amplifier may be coupled to the second input of the first amplifier by closing a switch (e.g., the sixth switch 240) between the output of the third amplifier and the second input of the first amplifier.
At block 920, during the first phase, an input of the third amplifier is driven using an output of the first amplifier. For example, the input of the third amplifier may correspond to the input 542 of the third amplifier 540 and the output of the first amplifier may correspond to the output 516 of the first amplifier 510.
At block 930, during a second phase, an input of the second amplifier is driven using the output of the first amplifier. For example, the input of the second amplifier may correspond to the input 522 of the second amplifier 520.
In some implementations, the second amplifier includes one or more inverters (e.g., inverters 532 and 534) and the third amplifier includes a source-follower amplifier (e.g., source-follower amplifier 560). For example, the one or more inverters may be used to provide a rail-to-rail signal during the second phase and the source-follower amplifier may be used to provide voltage level shifting during the first phase (e.g., for low common mode voltage operation during the first phase). In some implementations, the first amplifier comprises a cascode amplifier (e.g., a folded-cascode amplifier).
In certain aspects, the method 900 may further include, during the first phase, sampling a first voltage using a first capacitor, and coupling a second capacitor between the first input and the second input of the first amplifier. For example, the first capacitor may correspond to the first capacitor 210 and the second capacitor may correspond to the second capacitor 220. In this example, the first capacitor 210 may sample the first voltage by closing the third switch 225 and the second capacitor 220 may be coupled between the first input and the second input of the first amplifier by closing the fifth switch 235. The second capacitor may be coupled between the first input and the second input of the first amplifier to sample an input offset voltage of the first amplifier (e.g., to compensate for the input offset voltage during the second phase).
The method 900 may further include, during the second phase, sampling a second voltage using the second capacitor, and generating an output signal at the output of the first amplifier based on the first voltage and the second voltage, wherein driving the input of the second amplifier using the output of first amplifier comprises driving the input of the second amplifier with the output signal. For example, the second capacitor 220 may sample the second voltage by closing the fourth switch 230.
In certain aspects, the first voltage may include a voltage across a first resistor (e.g., the external resistor 120) and the second voltage may include a voltage across a second resistor (e.g., the on-chip resistor 115). In this example, the method 900 may further include adjusting a resistance of the second resistor based on an output of the second amplifier.
The control circuit 140 may include a finite state machine, a microcontroller, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, or any combination thereof configured to perform the operations discussed above according to various aspects of the present disclosure.
Implementation examples are described in the following numbered clauses:
Any reference to an element herein using a designation such as “first,” “second,” and so forth does not generally limit the quantity or order of those elements. Rather, these designations are used herein as a convenient way of distinguishing between two or more elements or instances of an element. Thus, a reference to first and second elements does not mean that only two elements can be employed, or that the first element must precede the second element.
Within the present disclosure, the word “exemplary” is used to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term “aspects” does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation. The term “coupled” is used herein to refer to the direct or indirect electrical coupling between two structures. It is also to be appreciated that the term “ground” may refer to a direct current (DC) ground or an alternating current (AC) ground, and thus the term “ground” covers both possibilities. An AC ground may be provided by a DC voltage. As used herein, “approximately” means within 10 percent of the stated value (i.e., within a range between 90 percent of the stated value and 110 percent of the stated value).
The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
