Patent Grant
7057310
1. Field of the Invention
The present invention relates to linear regulators and, more particularly, to a low dropout regulator capable of sinking and sourcing current, and of regulating a first output voltage that is exactly half of a second output voltage.
2. Description of Related Art
Currently, double data rate (DDR) DRAM devices are getting popular and have the potential to replace the synchronous dynamic RAM (SDRAM) devices. As the data rate increases, the data communication between a CPU and a DDR DRAM requires careful design to minimize signal reflection and ringing.
When the line driver 12 output is a high state, 2.5V, the power dissipation of the data line is VDDQ2/(RS+RT), or 94.7 mW. When the line driver 12 output is a low state, the power dissipation is 0. Assuming the line driver 12 has 50% probability in high state, and 50% probability in low state, its average power dissipation would be 47.3 mW.
When the output of line driver 22 is a high state, or 2.5V, its power dissipation is (VDDQ−VTT)2/(RS+RT), or 23.7 mW. When it is a low state, or 0V, the power dissipation is VTT2/(RS+RT), or 23.7 mW. Therefore, either in high or low state, the average power dissipation of the data line is always 23.7 mW.
The calculation above clearly shows that, by connecting the termination resistors to a voltage half of VDDQ, the power dissipation can be cut down by 50%. In a typical DDR DRAM data bus system, there may be as many as 110 data lines. The power dissipation saving will be 2.607 W, a significant amount.
However, in order to achieve power saving, the termination voltage VTT 29 requires both sinking and sourcing current capability. When there are more lines in high states than in low states, VTT 29 needs to draw (sink) current from the data bus system. On the other hand, when there are more lines in low state than in high state, VTT 29 needs to supply (source) current to the data bus system.
VDDQ 21 is typically adjustable between 2.5V and 2.8V with a maximum peak current of 5 A. VTT 29 has a maximum source or sink current of 3 A. In general, VTT 29 is required to be kept at one half of VDDQ 21 voltage.
In a typical computer system, there are 3.3V and 5V power supplies available. A switching regulator or a linear regulator is used to derive the VDDQ voltage from the 5.0V or the 3.3V power source. A linear regulator is not as efficient as a switching regulator, but it requires no inductors and very few external components, and has relatively low cost. Recently, more and more DDR DRAM systems choose linear regulators to supply the VDDQ and VTT power.
The object of the present invention is to provide a dual-output voltage regulator, which integrates two regulators into a 5-pin package for reducing package cost, saving PC board space and simplifying the heat sink issues.
Another object of the present invention is to provide a dual-output voltage regulator fabricated in a single chip that has only five pins.
In the present invention, the dual-output voltage regulator packaged in a 5-pin chip provides a first terminal voltage and a second terminal voltage to a DDR DRAM data bus system. The dual-output voltage regulator comprises a first regulator unit, which includes a first transistor unit and a comparator unit, the first regulator unit receiving input voltage from a PC system and providing the first terminal voltage via the first transistor unit, the comparator unit connecting to one of the pins to provide shutdown function by inputting a shutdown signal via this pin; and a second regulator unit, which includes a second transistor unit, a third transistor unit and a divided voltage unit, the second regulator receiving the input voltage and the first terminal voltage such that the divided voltage unit provides a plurality of reference voltages to control the second transistor in terms of outputting the second terminal voltage, wherein the second terminal voltage is half of the first terminal voltage, and the second regulator unit is capable of sourcing current and sinking current.
In another aspect of the present invention, the dual-output voltage regulator packaged in a 5-pin chip provides a first terminal voltage and a second terminal voltage to double data rate DRAM. The dual-output voltage regulator comprises: a first regulator unit, which includes a first transistor unit and a comparator unit, the first regulator unit receiving an input voltage from a PC system and providing the first terminal voltage via the first transistor unit, the comparator unit connecting to one of the pins to provide shutdown function by inputting a shutdown signal via this pin; and a second regulator unit, which includes a first Darlington pair circuit and a second Darlington pair circuit, and receives the input voltage and the first terminal voltage so as to output the second terminal voltage, wherein the second terminal voltage is half the first terminal voltage, and the second regulator unit is capable of sourcing and sinking current.
Other objects, advantages, and novel features of the invention will be elaborated in the detailed description with drawings.
FIG 1A shows a conventional data bus line termination scheme with a termination resistor connected between a data bus line and the ground;
A first preferred embodiment of the dual-output voltage regulator in accordance with the present invention will be described herein. Referring to
The first LDO 30 comprises an under-voltage lockout circuit (UVLO) 31, a current limit circuit 33, an OP-AMP 35, a P-type MOSFET 34, a bandgap reference 36 and a shut-down comparator 32.
The input (source) of P-type MOSFET 34 is connected to an input voltage 51 via pin 52 of power package 50. The output (drain) of P-type MOSFET 34 provides a VDDQ voltage 53 via pin 37 of power package 50. Under-voltage lockout circuit 31 ensures the proper operation of the first LDO 30 and the second LDO 40 of the power package 50. In other words, the first LDO 30 and the second LDO 40 can operate when the voltage of input voltage 51 is higher than a preset threshold level, for example, 3.0V.
The current limit circuit 33 senses the magnitude of load current passing through P-type MOSFET 34. If it detects an over-current condition, a signal will be sent to OP-AMP 35 to reduce the source-gate voltage (VSG), thus throttling down the output current. Bandgap reference 36 provides a precise reference, for example, 1.24V±1%, for the OP-AMP 35.
The output of OP-AMP 35 is connected to the gate of P-type MOSFET 34. It regulates the VSG voltage of P-type MOSFET 34, which in turn keeps VDDQ 53 at a constant voltage. The positive input of OP-AMP 35 is connected to the ADJ pin 38, which is connected to a voltage divider comprising resistors 54 and 55. Since OP-AMP 35 has a large DC gain, it will force the voltage on its positive input (ADJ pin 38) to follow the negative input, i.e. the 1.24V reference. As a result, VDDQ 53 remains at 1.24V·(1+R54/R55).
If VDDQ 53 tries to move higher than 1.24V·(1+R54/R55), due to, for instance, a reduced load current, the voltage on ADJ 38 will start to move above 1.24V. OP-AMP 35 will then in turn push the gate voltage of P-type MOSFET 34 higher, thus reducing VSG of P-type MOSFET 34 and the current supplied to the output. The output voltage therefore quickly restores to 1.24V·(1+R54/R55).
On the other hand, if VDDQ 53 tries to move lower than 1.24V·(1+R54/R55), for example, due to an increased load current, the voltage on ADJ 38 will start to move below 1.24V. OP-AMP 35 will then pull the gate voltage of P-type MOSFET 34 lower, thus increasing VSG of P-type MOSFET 34 and the current supplied to the output, whose voltage therefore quickly restore to 1.24V·(1+R54/R55).
Further, ADJ pin 38 can also function as a shutdown pin. A shutdown input 57 can be connected to ADJ pin 38 via a diode 56. If shutdown input 57 is kept low, typically less than 0.5V, diode 56 will be off and appear as high impedance, which nevertheless will not interfere with the normal voltage divider operation of resistors 54 and 55. However, if the shutdown input 57 is pulled higher than, for example, 2.7V, the diode 56 will conduct, trigger the comparator 32 and shut down the first LDO 30 and the second LDO 40.
The second LDO 40, capable of sourcing and sinking output current, comprises a plurality of divided voltage resistors 41, 42 and 43, two OP-AMPs 44,45 and two N-type MOSFETs 46 and 47.
The input (drain) of N-type MOSFET 46 is connected internally to pin 37. In other words, the drain of N-type MOSFET 46 is connected to VDDQ output voltage 53. The output (source) of N-type MOSFET 46 provides a source current to a VTT voltage 58 via VTT pin 48. The external of VTT pin 48 is also connected to a filter capacitor 59. The input (drain) of N-type MOSFET 47 is connected internally to VTT pin 48. The output (source) of N-type MOSFET 47 is connected to ground via GND pin 39.
VTT pin 48 is connected internally to the negative input of OP-AMP 44, as well as the positive input of OP-AMP 45. The voltage-dividing resistors 41, 42, and 43 create two reference voltages, one 49% of VDDQ voltage 53, the other 51% of VDDQ voltage 53. The positive input of OP-AMP 44 has a reference voltage of 0.49·VDDQ. The negative input of OP-AMP 45 has a reference voltage of 0.51·VDDQ.
If VTT voltage 58 tries to move below 1.25V, such as in a result of VTT load's pulling more current from the filter capacitor 59, OP-AMP 45 will have a low output voltage, and thus turn off N-type MOSFET 47. OP-AMP 44 will have a higher output voltage, which in turn pushes VGS of N-type MOSFET 46 higher and increases the supplied current to VTT pin 48, restoring the VTT voltage 58 to 1.25V.
On the other hand, if the VTT voltage 58 tries to move above 1.25V, such as when VTT load sends back current from the data bus system to filter capacitor 59, OP-AMP 44 will have a low output voltage and turn off N-type MOSFET 46. OP-AMP 45 will have a higher output voltage, and thus will pull VGS of N-type MOSFET 47 higher, and sink more current coming from VTT voltage 58 to ground, quickly restoring VTT voltage 58 to 1.25V.
Since the input (source) of P-MOSFET 34 is connected to 3.3V input, the maximum voltage available for controlling the VSG of P-MOSFET 34 is 3.3V.
Similarly, the maximum voltage available for controlling the VGS of N-MOSFET 46 is 3.3V−1.25V=2.05V. The maximum voltage available for controlling the VGS of N-MOSFET 47 is 3.3V.
In comparison to N-type MOSFET 46 of
When P-MOSFET 93 sources current to VTT voltage 98, its voltage steps down from 3.3V to 1.25V directly. However, its overall efficiency is exactly the same as that of the circuit shown in
However, since MOSFET 93 derives VTT power directly from the input voltage 81, instead of from the VDDQ voltage 83, it cannot share the current limit circuit 82 of the first LDO 80. A separate current sense circuit 97 is required to provide the current limit or over-current protection for sourcing current to and sinking current from VTT voltage 98. If current sense circuit 97 detects a sourcing current exceeding a preset value, it will bring a control line 95 to a higher voltage, which in turn will force OP-AMP 91 to reduce the VSG of P-type MOSFET 93, thus cutting down the output current to VTT voltage 98.
On the other hand, if current sense 97 detects a sinking current exceeding a preset value, it will bring a control line 96 to a higher voltage, which in turn will force OP-AMP 92 to reduce the VGS of N-type MOSFET 94, thus cutting down the current through N-type MOSFET 94.
The input (emitter) terminal of PNP transistor 112 is connected to input voltage 111 via VIN pin 101. The output (collector) terminal of PNP transistor 112 is connected to VDDQ pin 102. The base current for PNP transistor 112 is drained to ground with the control of OP-AMP 113. Fabricated with a high-gain bipolar transistor, PNP transistor 112 is capable of providing a low dropout voltage of less than 500 mV at 5A of output current.
A voltage divider comprising resistors 114 and 115 is connected to the non-inverting input of OP-AMP 113 via ADJ pin 103. As described in
The input (collector) of NPN transistor 127 is connected to VDDQ pin 102 internally. The output (emitter) of NPN transistor 127 sources current to VTT voltage 134 via VTT pin 105. A second NPN transistor 126 supplies the base current of NPN transistor 127, whereas OP-AMP 124 supplies the base current of NPN transistor 126 via a base resistor 125. NPN transistors 126 and 127 form a Darlington pair in a cascade structure. Almost all the collector current of NPN transistor 126 flows into the base of NPN transistor 127. Since VTT voltage 134 is 1.25V, the operating voltage required to drive Darlington pair 126 and 127 is about 1.25V+0.7V+0.7V=2.65V. OP-AMP 124 can easily support this voltage, with input voltage 111 supplying a 3.3V operating voltage to OP-AMP 124.
The input (collector) terminal of NPN transistor 133 is connected to VTT pin 105 internally. The output (emitter) terminal of NPN transistor 133 is connected to ground. A second PNP transistor 132 supplies the base current of NPN transistor 133, whereas OP-AMP 124 controls the base current of PNP transistor 132 via a base resistor 131. PNP transistor 132 and NPN transistor 133 form a second Darlington pair. Since VTT voltage 134 is 1.25V, the operating voltage required to drive PNP transistor 132 is approximately 1.25V−0.7V=0.55V. PNP transistor 132 can easily operate in this condition.
Unlike the above-mentioned MOSFET embodiments of the present invention, as shown in
An internal voltage divider, comprising resistors 121 and 122 of a same resistance value, provides a reference voltage 123 of exactly 50% of VDDQ voltage 116 to the positive input of OP-AMP 124. On the other hand, the inverting input of OP-AMP 124 is connected internally to VTT pin 105. Since OP-AMP 124 has a high DC gain, it will force VTT voltage 134 to follow the reference voltage 123, which is exactly one half of VDDQ voltage 116.
When VTT voltage 134 is trying to drop below 50% of VDDQ voltage 116, such as in the case of a data bus system drawing more current from VTT voltage 134, the output voltage of OP-AMP 124 starts to increase. As soon as the output voltage of OP-AMP 124 reaches 0.55V, Darlington pair 132–133 turns off. As the voltage has risen to approximately 2.65V, Darlington pair 126–127 starts to turn on, thus supplying more current to VTT voltage 134 and restoring VTT voltage 134 quickly to 50% of VDDQ voltage 116.
When VTT voltage 134 is trying to rise above 50% of VDDQ voltage 116, such as in the case of a data bus system returning current to VTT voltage 134, the output voltage of OP-AMP 124 starts to decrease from a high level to a low level. As soon as the output voltage of OP-AMP 124 drops below 2.65V, Darlington pair 126–127 turns off. As the voltage has dropped to approximately 0.55V, Darlington pair 132–133 starts to turn on, thus sinking more current from VTT voltage 134, and quickly restoring VTT voltage 134 to 50% of VDDQ voltage 116 level.
The description above shows that the invention is able to package the two LDOs into a chip with only five pins. Each LDO provides a VDDQ voltage or a VTT voltage via at least one transistor (i.e., MOSFET or BJT) and at least one operational amplifier. The VTT voltage is half of the VDDQ voltage, saving the cost of the package and capable of using small PCB.
Although the present invention has been explained in relation to its preferred embodiment, it is to be understood that many other possible modifications and variations can be made without departing from the spirit and scope of the invention as hereinafter claimed.
| Number | Date | Country | Kind |
|---|---|---|---|
| 91123252 A | Oct 2002 | TW | national |
| Number | Date | Country | |
|---|---|---|---|
| 20040070276 A1 | Apr 2004 | US |
