Input port 106 is the inverting, or negative, input port of operational amplifier A1. Output port 108 of operational amplifier A1 is connected to the gate of transistor Mn. In the embodiment of
Output port 108 is connected to input port 114, the non-inverting, or positive, input port of operational amplifier A2. Output port 116 is connected to the inverting, or negative, input port of operational amplifier A2. Operational amplifier A2 is configured as a unity-gain buffer so that the voltage at output port 116 follows that of output port 108. Output port 116 is also connected to the gate of transistor Mp. In the embodiment of
With the drain of transistor Mp connected to positive input port 112, there is a first feedback loop comprising operational amplifier A1, operational amplifier A2, and transistor Mp. With the drain of transistor Mn connected to positive input port 112, there is a second feedback loop comprising operational amplifier A1 and transistor Mn. This is the motivation for referring to an embodiment represented by
In operation, if the voltage at node 102, VREG, were to increase above its desired regulated value, VREF, then the output voltage at output port 108 would increase. Because operational amplifier A2 is configured as a unity-gain buffer, the voltage at output port 116 would also increase, reducing the magnitude of the gate-to-source voltage of pass transistor Mp, causing pass transistor Mp to source less current to load 104, and thereby counteracting an increase in voltage at node 102. In addition, when the voltage at output port 108 increases, there is an increase in the gate-to-source voltage of transistor Mn. As a result, transistor Mn shunts current from node 102 to ground, further counteracting an increase in voltage at node 102. Accordingly, transistor Mn may be referred to as a shunt transistor.
For some embodiments, the operating bandwidth of the second feedback loop may be designed to be larger than that of the first feedback loop. For such embodiments, operational amplifier A2 lowers the magnitude of the gate-to-source voltage of transistor Mp slower than the rate that operational amplifier A1 increases the gate-to-source voltage of transistor Mn.
If the voltage VREG at node 102 were to decrease below VREF, then the output voltage at output port 108 would decrease, thereby increasing the magnitude of the gate-to-source voltage of pass transistor Mp, causing pass transistor Mp to source more current to load 104, thereby counteracting a decrease in voltage at node 102. In addition, a decrease in voltage at output port 108 below VREG decreases the gate-to-source voltage of shunt transistor Mn, causing shunt transistor Mn not to shunt current to ground. If for some embodiments the operating bandwidth of the second feedback loop is larger than that of the first feedback loop, then amplifier A2 would increase the gate-to-source voltage of transistor Mp slower than the rate that amplifier A1 would decrease the magnitude of the gate-to-source voltage of transistor Mn.
Transistor Mn shunts current from node 102 to ground when its gate-to-source voltage exceeds its threshold voltage. Although the shunting function provided by transistor Mn may degrade efficiency, the relatively fast response of the second feedback loop provided by amplifier A1 in conjunction with transistor Mn allows for the use of a smaller output de-coupling capacitor than might be needed if the second feedback loop were not present. Letting ZREG denote the small-signal impedance of the dual path linear voltage regulator as seen by voltage rail 118, ZREG is expected to have a phase not below −90 degrees. As a result, it is expected that output de-coupling capacitor 120 need not be as large as what might be needed if the second feedback loop were not present, and embodiments need not be over-damped in order for the phase of ZREG not to fall below −90 degrees. ZREG may be referred to as the regulator impedance.
An expression for the regulator impedance as seen by voltage rail 118 may be derived from a small-signal circuit model for
With the variables shown in
The variables Rx and ωx in the above expression are defined as:
In the above-displayed expression, Aohbw is the open loop DC gain of operational amplifier A1, Aolbw is the open loop DC gain of operational amplifier A2, ωlbw is the open loop bandwidth of operational amplifier A2, and ωhbw is the open loop bandwidth of operational amplifier A1.
Embodiments of the present invention are expected to find wide applications. One such application is to regulate the voltage provided to one or more circuits in one or more microprocessor execution cores by utilizing one or more dual path linear voltage regulators.
Various modifications may be made to the disclosed embodiments without departing from the scope of the invention as claimed below.
It is to be understood in these letters patent that the meaning of “A is connected to B”, where A or B may be, for example, a node or device terminal, is that A and B are connected to each other so that the voltage potentials of A and B are substantially equal to each other. For example, A and B may be connected together by an interconnect (transmission line). In integrated circuit technology, the interconnect may be exceedingly short, comparable to the device dimension itself. For example, the gates of two transistors may be connected together by polysilicon, or copper interconnect, where the length of the polysilicon, or copper interconnect, is comparable to the gate lengths. As another example, A and B may be connected to each other by a switch, such as a transmission gate, so that their respective voltage potentials are substantially equal to each other when the switch is ON.
It is also to be understood in these letters patent that the meaning of “A is coupled to B” is that either A and B are connected to each other as described above, or that, although A and B may not be connected to each other as described above, there is nevertheless a device or circuit that is connected to both A and B. This device or circuit may include active or passive circuit elements, where the passive circuit elements may be distributed or lumped-parameter in nature. For example, A may be connected to a circuit element that in turn is connected to B.
It is also to be understood in these letters patent that various circuit blocks, such as current mirrors, amplifiers, etc., may include switches so as to be switched in or out of a larger circuit, and yet such circuit blocks may still be considered connected to the larger circuit because the various switches may be considered as included in the circuit block.