Patent Application
20140240044
The present invention relates to operational amplifiers. More specifically, the present invention is a dual path operational amplifier with a high frequency path and a low frequency path.
Operational amplifiers (Op-amps) are among the most widely used electronic devices today. It has a variety of functions and is used in many industries. In designing Op-amp, sizes of transistors in differential input stage have to be large in order to obtain good DC characteristics. As a result, frequency poles relating to parasitic capacitances of the transistors are formed at lower frequency. These lower poles impose limitation on bandwidth of the Op-amp. Therefore in designing high speed Op-amp, adding one more signal path in which there are no large transistors can be effective way. The present invention provides one method to design dual-path operational amplifier which is able to drive not only captive load but also resistive load.
All illustrations of the drawings and description of embodiments are for the purpose of describing selected versions of the present invention and are not intended to limit the scope of the present invention.
The present invention comprises of three main sections. The first section, 2 converts an input voltage into an amplified output voltage. The second main section, 5 converts input voltage into an output current. This current is sent through a resistor, rf 8, to get the required voltage corresponding to this section 5. The final section, 9 comprises an operational amplifier in which the output of the first stage 2 is the input at the plus (+) port and the output of the second stage 5 is the input at the minus (−) port.
In the final section 9, for a signal connected to the plus (+) input, the amplifier acts as a voltage follower. A voltage follower is a system where the output voltage follows the input voltage.
On the other hand, for an input signal applied to the minus (−) input, the amplifier acts as a Transimpedance Amplifier (TIA). Where a TIA is a current to voltage converter, usually implemented using an operational amplifier. As a result of this setup, the path connected to the plus input carries low frequencies 2 and the path connected to the minus input carries higher frequencies 5. The path for low frequencies 2 has a high DC (Direct Current) gain and the path for high frequencies 5, has a low DC gain.
Furthermore, in reference to
In reference to
[Vout/Vin]=[Gmi·R·RL(Gmo·rf−1)]/{Gmo·R·RL+R+RL+rf+s·[CL·RL·(R+rf)+cpara·R·(RL+rf)]+s2·cpara·CL·R·RL·rf}≈Gmi·RL(Gmo·rf−1)/[(Gmo·RL+1)·{1+s·CL·RL/(Gmo·RL+1)}{1+s·cpara·rf}]
In this calculation it was assumed that:
[rf·(Gmo+1/RL)·cpara]/CL<<1
Vout—Output voltage
Vin—Input voltage
R—Output resistance of Gmi
cpara—parasitic capacitance value
CL—Load capacitor for the op-amp
RL—Load resistor for the op-amp
From the above obtained expression for the transfer function of the path A2 5, it can be seen that this path has a low DC gain of Gmi·(rf−1/Gmo). The first pole of A2 5 is formed at the output node and is equal to Gmo/CL if Gmo·RL>>1. The second pole of the same path A2 5, lies at 1/(cpara·rf). Therefore, for stability, the unity gain frequency ωu2 of the path A2 5 in the preferred embodiment of the present invention should be smaller than the second pole:
(Gmi·Gmo·rf)/CL<1/[cpara·rf]
This can also be expressed as:
[(Gmi·rf)(Gmo·rf)·cpara]/CL<1
Additionally, each DC mismatch current of differential pairs of transistors ∂I/∂N·ΔN+∂I/∂(W/L)·Δ(W/L) at the Gmi stage is multiplied only by the resistance of rf 8 in the later stage to give little voltage. In this case, N is doping density, W and L represent the width and length of the particular MOSFET. Therefore the mismatch has little influence on input offset. This enables the transistor to be small in size.
In reference to
V
out
/V
in
=[A1(s)+A2(s)]/[1+A1(s)+A2(s)]
In this calculation the common mode gains are ignored.
A1(s)=A1/[(1+s·tf)(1+s·ts)]
Wherein (1+s·tf) represents the first pole and (1+s·ts) represent the second pole respectively.
A2(s)=A2/(1+s·t2)
This results in the following equation:
V
out
/V
in
={A1+A2+s·[A1·t2+A2·(tf+ts)]+s2·[A2·tf·ts]}/{A1+A2+1+s·[tf+ts+t2+A1·t2+A2(tf+ts)]+s2·[tf·ts+ts·t2+t2·tf+A2·tf·ts]+s3tf·ts·t2}≈(A1+s·[A2·tf+A1·t2]+s2·A2·tf·ts)/{A1+s·[(A2+1)·tf+A1·t2]+s2·tf·[(A2+1)·ts+t2]+s3·tf·ts·t2}
When A2>>1 and A2·tf>>A1·t2
(in which the latter condition is equivalent to A2·Gmo/CL>>ωu1 and ωu1 is the unity gain frequency of the path A1 2):
tf—a time constant equal to the inverse of the first pole.
ts—a time constant equal to the inverse of the second pole
The expression above, representing the transfer function of the amplifier, shows us that A2 5 should be as large as possible under condition for stability in order to get a flat curve. If this value is not much larger than 1, a drop appears. This approximately occurs close to the point ùu1/A2 due to the mismatch of position of the first pole and the first zero. Similarly, another drop step might occur due to the mismatch of the second pole and second zero.
In reference to
tf=gm6·(rds6∥rds7)·(rds5·rds3)·Cc
ts=C
1
/Gmo
where
Gmo=gn24·gm28/gm26. If this second pole is cancelled by a zero of 1/(Rc·Cc), ts has a different value reciprocal to a pole occurring from parasitic capacitance.
Although the current invention has been explained in reference to its preferred embodiment, it is to be understood that many other possible modifications and variations can be made without departing from the spirit and scope of the invention as in hereinafter defined by the appending claims.
The current application claims a priority to the U.S. Provisional Patent Application serial number 61770045, filed on Feb. 27, 2013.
| Number | Date | Country | |
|---|---|---|---|
| 61770014 | Feb 2013 | US |
