Claims
- 1. A programmable logic device comprising:
a plurality of programmable logic regions; a dual-port variable depth and width memory array; and a plurality of interconnects for routing signals between the programmable logic regions and the dual-port variable depth and width memory array.
- 2. The programmable logic device of claim 1 wherein the dual-port variable depth and width memory array operates in at least ×1, ×2, ×4, ×8 and ×16 data width modes.
- 3. The programmable logic device of claim 1 wherein the dual-port variable depth and width memory array comprises:
a memory array having a plurality of rows and columns of memory cells for storing data; variable depth and width writing circuitry for performing write operations with selectable-size data words by addressing selected write locations within the memory array and by writing data words into those write locations; and variable depth and width reading circuitry for performing read operations with selectable-size data words concurrently with the write operations performed by the writing circuitry by addressing selected read locations within the memory array and by reading data words from those read locations.
- 4. The programmable logic device of claim 3 wherein the writing circuitry comprises:
a write column decoder and data selection logic responsive to write column address information; and the reading circuitry comprises a read column decoder and data selection logic responsive to read column address information.
- 5. The programmable logic device of claim 1 wherein the programmable logic regions contain a plurality of programmable logic subregions.
- 6. The programmable logic device of claim 1 wherein the memory array is a static random-access memory (SRAM) array.
- 7. A method for concurrently writing to and reading data from a variable depth and width dual-port memory array having a plurality of rows and columns of memory cells for storing data in a programmable logic device having logic circuitry, comprising:
performing write operations with selectable-size data words by addressing selected write locations within the memory array and by writing data words into those write locations; and performing read operations with selectable-size data words concurrently with the write operations performed by the writing circuitry by addressing selected read locations within the memory array and by reading data words from those read locations.
- 8. The method of claim 7 further comprising using input registers to register the data words to be written to the memory array.
- 9. The method of claim 7 further comprising using output registers to register the data words that have been read from the memory array.
Parent Case Info
[0001] This application is a continuation of application Ser. No. 09/519,166, filed Mar. 6, 2000, which is a continuation of application Ser. No. 09/107,533, filed Jun. 30, 1998, now U.S. Pat. No. 6,052,327, which claims the benefit of U.S. provisional application No. 60/062,966, filed Oct. 14, 1997.
Provisional Applications (1)
|
Number |
Date |
Country |
|
60062966 |
Oct 1997 |
US |
Continuations (2)
|
Number |
Date |
Country |
Parent |
09519166 |
Mar 2000 |
US |
Child |
09747191 |
Dec 2000 |
US |
Parent |
09107533 |
Jun 1998 |
US |
Child |
09519166 |
Mar 2000 |
US |