Claims
- 1. A dual-ported operator control panel (OCP) arrangement of a distributed computer system comprising:
a plurality of OCPs, each OCP comprising a plurality of ports coupled to a display, light emitting diodes (LEDs) and push buttons via a multiplexer; a plurality of microprocessors, each coupled to an OCP port; and OCP election logic coupled to the OCP ports and multiplexer, the OCP election logic configured to select a microprocessor coupled to an OCP port to control the display and LEDs of the OCP, the OCP election logic further enabling the multiplexer to allow the selected microprocessor to control the display and LEDs.
- 2. The dual-ported OCP arrangement of claim 1 wherein the push buttons comprises halt, reset and fault state buttons and wherein the LEDs comprises power OK, halt and secure states.
- 3. The dual-ported OCP arrangement of claim 2 wherein the states of the buttons are provided to OCP ports over separate isolated data paths of the OCP.
- 4. The dual-ported OCP arrangement of claim 1 wherein each OCP further comprises a keyswitch having a 4-pole/3-position mechanism with 30° indexing.
- 5. The dual-ported OCP arrangement of claim 4 wherein the keyswitch further comprises make-before-break shorting that provides a plurality of separate and electrically isolated circuits to allow the microprocessors access to read the position of the keyswitch simultaneously.
- 6. The dual-ported OCP arrangement of claim 1 wherein the distributed computer system is a symmetric multiprocessor (SMP) system having a management subsystem comprising a network of microcontrollers, and wherein the microprocessors are system control manager (SCM) microcontrollers of the SMP system.
- 7. The dual-ported OCP arrangement of claim 3 wherein the microprocessors are interconnected by a console serial bus (CSB) subsystem.
- 8. The dual-ported OCP arrangement of claim 7 wherein
the microprocessors negotiate among themselves to elect a master of the CSB subsystem, and the elected master microprocessor asserts a mastership signal to the OCP to which the elected master microprocessor is coupled.
- 9. The dual-ported OCP arrangement of claim 8 wherein the OCPs elect a single OCP to be master OCP based on signals received by the OCPs from the microprocessors coupled thereto.
- 10. The dual-ported OCP arrangement of claim 9 wherein a given OCP is elected the master OCP provided that a single microprocessor coupled to the given OCP asserts the mastership signal, thereby indicated that the respective microprocessor is master of the CSB subsystem.
- 11. The dual-ported OCP arrangement of claim 10 wherein a given OCP is designated a slave OCP where no microprocessor coupled to the given OCP asserts the mastership signal.
- 12. The dual-ported OCP arrangement of claim 11 wherein the assertion of the mastership signal by more than microprocessor coupled to the same OCP is ignored by the OCP.
- 13. The dual-ported OCP arrangement of claim 12 further comprising an OCP master determination table accessible by the OCP election logic for use in determining whether the respective OCP is the master or a slave OCP.
- 14. The dual-ported OCP arrangement of claim 13 wherein the microprocessors and OCPs utilize the EIA-RS232E specification standard.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The present application claims priority from U.S. Provisional Patent Application Ser. No. 60/206,482, which was filed on May 23, 2001, by Stuart Berke and Daniel Wissell for a DUAL-PORTED OPERATOR CONTROL PANEL WITH AUTOMATIC FAILOVER and is hereby incorporated by reference.
Provisional Applications (1)
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Number |
Date |
Country |
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60206482 |
May 2000 |
US |