Liquid crystal display (LCD) technology provides relatively energy efficient, space efficient, high image quality displays. Such displays can be used on devices as small as a wrist watch or as large as a multimedia theater display. However, the inventor herein has recognized that current LCD technology is relatively expensive and/or can be difficult to scale to large sizes. These issues can be addressed by a dual select diode technology that utilizes in-plane switching and/or color-on-array designs.
a-4c schematically show an exemplary process for forming an in-plane switching dual select diode circuit.
a-10 schematically show an exemplary process for forming an in-plane switching dual select diode circuit.
Thin Film Diode (TFD) Liquid Crystal Displays with two select lines per row of pixels can be used in a variety of display applications. When operated in a dual select mode, the pixel circuit can act as an analog switch. This can lead to a performance similar to TFT LCDs, as a result of accurate gray shade control, fast response time, and tolerance for variations in the Thin Film Diode characteristics over time and across the viewing area. Such a Dual Select Diode (DSD) LCD also can be relatively insensitive to RC delays on the select and data lines and can therefore be scaled up to very large area, exceeding 40 in. in diagonal size, for application in LCD TV.
Dual Select Diode (DSD) LCDs can use a two branch diode circuit which can accurately transfer the data voltage to the LC capacitor. Select lines can be located on the active array substrate and data lines on the opposite substrate.
The configuration shown in
Although the conventional DSD AMLCD can be suitable for many display applications, additional improvements in performance and/or cost can increase the applications in which the technology beats competitive technologies. The following are nonlimiting examples of improvements attainable by the technology of the present disclosure:
1) Improve viewing angle as compared to conventional TN mode; 2) Minimize the total combined mask count and process steps for the active array substrate and the top substrate of the LCD; 3) Add a storage capacitance at each pixel to improve gray scale control; 4) Eliminate all patterning steps on the top substrate, so that there is no critical alignment between the two substrates in large area manufacturing (on e.g. ˜2 m×2 m substrates); 5) Minimize RC delays on the buslines so as to improve the possible size of the DSD LCD.
Another LC mode, the In-Plane-Switching (IPS) mode, can give superior viewing angle behavior, as compared to the conventional Twisted Nematic (TN) mode. In the IPS mode, the electrodes controlling the LC orientation can all be on the active matrix substrate. When a voltage is applied between these lateral electrodes, the resulting lateral field causes the LC molecules to rotate parallel to the glass substrates, leading to superior viewing angle behavior. By patterning the color filters on the active substrate, a total combined mask count of five can be achieved. The same dielectric used for the diode (e.g. Si-rich SiNx) can be used for the storage capacitor. By using the IPS mode with color filters on the array, there are no photolithographic patterns on the other plate, eliminating plate-to-plate alignment requirements. By using the color filters as the dielectric between the select lines and the data lines, a low busline cross-over capacitance is obtained, helping to minimize RC delays and allowing large size displays.
a-4c show an exemplary cross-section and layout of a subpixel, as it evolves during manufacturing. The select line metal and the dielectric (e.g., SiNx or Diamond-like Carbon) are deposited sequentially. The first mask delineates the select lines with the SiNx on top. Subsequently, with masks 2, 3, and 4, the three color filters R, G and B are deposited and patterned with contact holes (vias) in the location where the diodes and storage capacitors are designed (red is shown in the example). Then, the data line metal is deposited. With the fifth mask the data lines, top electrodes of the diodes and storage capacitors, and the grid for the IPS electrodes are delineated. The areas of the contact holes determine the diode areas and storage capacitor areas.
The top plate of this IPS DSD LCD is simply a glass plate without any pattern. This means that for very large substrate manufacturing, including up to 2 m×2 m or more, there is no critical alignment between the active substrate and the top substrate.
The simple process for IPS DSD LCDs can be used in conjunction with a pixel circuit having separate select lines, as well as shared select lines.
An offset-scan-and-hold driving method was described in U.S. Pat. Nos. 6,225,968 and 6,222,596, which eliminates or minimizes vertical cross-talk and also can improve charge retention on the pixel. This drive method requires line inversion for the data drive. In the pixel layouts of
In
To achieve the correct image on the display, one half of all the video data (for alternate pixels) can be delayed by a line time. A line memory latch in the data driver or some simple image processing in the controller circuitry of the display can facilitate such a delay.
In some embodiments, the diode and storage capacitor areas can be determined by the contact hole size in the color filters. The process can be optimized to obtain high quality diodes in this process; however, there may be an issue with reproducibility and consistency of the diode characteristics, because the top surface of the SiNx layer is exposed to many processing steps. In addition, the patterning of the color filter may leave some residue in the contact hole areas. These two process issues may lead to poorly defined interface between the SiNx layer and the top metal contact to the diode.
The below described embodiments are meant to address this issue, and also to make the diode process stack compatible with high throughput large scale manufacturing.
An additional metal layer can be deposited on top of the SiNx, optionally in the same pumpdown, to obtain a stack of metal-SiNx-metal, with well-defined interfaces between both metals and the SiNx layers (see
In
After the select lines and capacitor section are patterned, the photoresist can be ashed (or back-etched) so that the thin resist areas are removed while the thicker resist is not fully removed. With a second metal etch step the top metal can be removed such that only top metal remains in the area of the diodes and the storage capacitor, as shown in the figure.
Subsequently, the red, green and blue color filters can be patterned with contact holes on top of the diode and storage capacitor areas.
Finally, the top metal can be deposited and patterned into data lines, interconnects for the diodes and storage capacitors and as an electrode grid for the LC pixels.
Each of the following U.S. Patents and Patent Applications are incorporated by reference for all purposes: 4,731,610; 6,222,596; 6,225,968; 6,243,062; 5,926,236; 6,008,872; 2004/0189885; 2005/0117083; 2005/0105010; 2005/0083283; 2005/0083321.
Although the present disclosure has been provided with reference to the foregoing operational principles and embodiments, it will be apparent to those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope defined in the appended claims. The present disclosure is intended to embrace all such alternatives, modifications and variances. Where the disclosure or claims recite “a,” “a first,” or “another” element, or the equivalent thereof, they should be interpreted to include one or more such elements, neither requiring nor excluding two or more such elements.
This application claims the benefit of U.S. Provisional Application No. 60/673,004, filed Apr. 19, 2005 and U.S. Provisional Application No. 60/705,095, filed Aug. 2, 2005. The entirety of each of the above listed documents is hereby incorporated herein by reference for all purposes.
Number | Date | Country | |
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60673004 | Apr 2005 | US | |
60705095 | Aug 2005 | US |