DUMMY PAGE INSERTION FOR FLEXIBLE PAGE RETIREMENT IN FLASH MEMORY STORING MULTIPLE BITS PER MEMORY CELL

BACKGROUND OF THE INVENTION

This disclosure relates to data processing and storage, and more specifically, to management of a data storage system, such as a flash memory system, to support flexible page retirement in memories storing multiple bits per memory cell.

NAND flash memory is an electrically programmable and erasable non-volatile memory technology that stores one or more bits of data per memory cell as a charge on the floating gate of a transistor or a similar charge trap structure. In a typical implementation, a NAND flash memory array is organized in blocks (also referred to as “erase blocks”) of physical memory, each of which includes multiple physical pages each in turn containing a multiplicity of memory cells. By virtue of the arrangement of the word and bit lines utilized to access memory cells, flash memory arrays can generally be programmed on a page basis, but are erased on a block basis.

As is known in the art, blocks of NAND flash memory must be erased prior to being programmed with new data. A block of NAND flash memory cells is erased by applying a high positive erase voltage pulse to the p-well bulk area of the selected block and by biasing to ground all of the word lines of the memory cells to be erased. Application of the erase pulse promotes tunneling of electrons off of the floating gates of the memory cells biased to ground to give them a net positive charge and thus transition the voltage thresholds of the memory cells toward the erased state. Each erase pulse is generally followed by an erase verify operation that reads the erase block to determine whether the erase operation was successful, for example, by verifying that less than a threshold number of memory cells in the erase block have been unsuccessfully erased. In general, erase pulses continue to be applied to the erase block until the erase verify operation succeeds or until a predetermined number of erase pulses have been used (i.e., the erase pulse budget is exhausted).

A NAND flash memory cell can be programmed by applying a positive high program voltage to the word line of the memory cell to be programmed and by applying an intermediate pass voltage to the memory cells in the same string in which programming is to be inhibited. Application of the program voltage causes tunneling of electrons onto the floating gate to change its state from an initial erased state to a programmed state having a net negative charge. Following programming, the programmed page is typically read in a read verify operation to ensure that the program operation was successful, for example, by verifying that less than a threshold number of memory cells in the programmed page contain bit errors. In general, program and read verify operations are applied to the page until the read verify operation succeeds or until a predetermined number of programming pulses have been used (i.e., the program pulse budget is exhausted).

Some NAND flash memories, referred to in the art as Single Level Cell (SLC), support only two charge states, meaning that only one bit of information can be stored per memory cell. Other NAND flash memories, referred to as Multi-Level Cell (MLC), Three Level Cell (TLC) and Quad Level Cell (QLC), respectively enable storage of 2, 3 or 4 bits information per cell through implementation of additional charge states. The higher storage density provided by NAND flash memories capable of storing multiple bits of information per cell often comes at the cost of higher bit error rates, slower programming times, and lower endurance (e.g., in terms of lifetime program/erase (P/E) cycle counts).

One cause of the lower endurance of NAND flash memories capable of storing multiple bits per cell is the enforcement of early retirement of subsets of these memories. In general, it is common for subsets of a NAND flash memory exhibiting relatively high bit error rates to be retired, for example, as an error threshold is reached. Because NAND flash memories supporting multiple bits per cell often utilize the bits of each memory cell to store data of multiple different data pages, retirement of one subset (e.g., data page) of the flash memory that employs a given memory cell to store one of its data bits generally necessitates the retirement of all other like subsets (e.g., data pages) that also employ that memory cell to store additional data bit(s), regardless of the bit error rates of these other subsets of the NAND flash memory. Consequently, subsets of the NAND flash memory can be withdrawn from use prematurely, that is, prior to those subsets exhibiting the bit error rate or other health metric necessitating retirement.

The present application discloses a technique that provides improved endurance in a data storage system by enabling one memory subset (e.g., data page) to be retired, while still keeping active other memory subsets sharing a common multiple-bit memory cell with the retired memory subsets (e.g., data page).

BRIEF SUMMARY

In at least one embodiment, a controller of a non-volatile memory array retires physical pages within the non-volatile memory array on a page-by-page basis. The physical pages retired by the controller include a first physical page sharing a common set of memory cells with a second physical page. While the first physical page is retired, the controller retains the second physical page as an active physical page, writes dummy data to the first physical page, and writes data received from a host to the second physical page.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1A is a high level block diagram of a data processing environment in accordance with one embodiment;

FIG. 1B is a more detailed block diagram of a flash card of the data storage system of FIG. 1A;

FIGS. 2-5 illustrate an exemplary arrangement of physical memory within a NAND flash memory system in accordance with the present disclosure;

FIG. 6A depicts an exemplary implementation of a block stripe in accordance with the present disclosure;

FIG. 6B depicts an exemplary implementation of a page stripe in accordance with the present disclosure;

FIG. 7 illustrates an exemplary codeword stored in each data page in accordance with the present disclosure;

FIG. 8 depicts an exemplary codeword stored in each data protection page in accordance with the present disclosure;

FIG. 9 is a high level flow diagram of the flash management functions and data structures employed by a flash controller in accordance with one embodiment;

FIG. 10 depicts a more detailed view of an exemplary flash controller 140 in accordance with one embodiment;

FIG. 11 is a high level logical flowchart of an exemplary process by which a flash controller reads data from a NAND flash memory system in accordance with one embodiment;

FIG. 12 depicts an exemplary page status table with which a flash controller tracks the status of physical pages of memory as retired or active (i.e., non-retired) in accordance with one embodiment;

FIG. 13 is a high level logical flowchart of an exemplary process by which a flash controller writes data to a NAND flash memory system in accordance with one embodiment;

FIGS. 14A-14B are more detailed views of a write cache in accordance with one embodiment; and

FIG. 15 is a graph illustrating the endurance gain achieved by implementing page retirement in accordance with one embodiment.

DETAILED DESCRIPTION

With reference to the figures and with particular reference to FIG. 1A, there is illustrated a high level block diagram of an exemplary data processing environment 100 including a data storage system 120 having a non-volatile memory array as described further herein. As shown, data processing environment 100 includes one or more hosts, such as a processor system 102 having one or more processors 104 that process instructions and data. Processor system 102 may additionally include local storage 106 (e.g., dynamic random access memory (DRAM) or disks) that may store program code, operands and/or execution results of the processing performed by processor(s) 104. In various embodiments, processor system 102 can be, for example, a mobile computing device (such as a smartphone or tablet), a laptop or desktop personal computer system, a server computer system (such as one of the POWER series available from International Business Machines Corporation), or a mainframe computer system. Processor system 102 can also be an embedded processor system using various processors such as ARM, Power, Intel X86, or any other processor combined with memory caches, memory controllers, local storage, I/O bus hubs, etc.

Each processor system 102 further includes an input/output (I/O) adapter 108 that is coupled directly (i.e., without any intervening device) or indirectly (i.e., through at least one intermediate device) to a data storage system 120 via an I/O channel 110. In various embodiments, an I/O channel 110 may employ any one or a combination of known or future developed communication protocols, including, for example, Fibre Channel (FC), FC over Ethernet (FCoE), Internet Small Computer System Interface (iSCSI), InfiniBand, Transport Control Protocol/Internet Protocol (TCP/IP), Peripheral Component Interconnect Express (PCIe), etc. I/O operations (IOPs) communicated via I/O channel 110 include read IOPs by which a processor system 102 requests data from data storage system 120 and write IOPs by which a processor system 102 requests storage of data in data storage system 120.

In the illustrated embodiment, data storage system 120 includes multiple interface cards 122 through which data storage system 120 receives and responds to input/output operations (IOP) 102 via I/O channels 110. Each interface card 122 is coupled to each of multiple Redundant Array of Inexpensive Disks (RAID) controllers 124 in order to facilitate fault tolerance and load balancing. Each of RAID controllers 124 is in turn coupled (e.g., by a PCIe bus) to each of multiple flash cards 126 including, in this example, NAND flash storage media. In other embodiments, other lossy storage media can be employed.

FIG. 1B depicts a more detailed block diagram of a flash card 126 of data storage system 120 of FIG. 1A. Flash card 126 includes a gateway 130 that serves as an interface between flash card 126 and RAID controllers 124. Gateway 130 is coupled to a general-purpose processor (GPP) 132, which can be configured (e.g., by program code) to perform various management functions, such as pre-processing of IOPs received by gateway 130 and/or to schedule servicing of the IOPs by flash card 126. GPP 132 is coupled to a GPP memory 134 (e.g., Dynamic Random Access Memory (DRAM)) that can conveniently buffer data created, referenced and/or modified by GPP 132 in the course of its processing.

Gateway 130 is further coupled to multiple flash controllers 140, each of which controls a respective NAND flash memory system 150. Flash controllers 140 can be implemented, for example, by an Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA)) having an associated flash controller memory 142 (e.g., DRAM). In embodiments in which flash controllers 140 are implemented with an FPGA, GPP 132 may program and configure flash controllers 140 during start-up of data storage system 120. After startup, in general operation flash controllers 140 receive read and write IOPs from gateway 130 that request to read data stored in NAND flash memory system 150 and/or to store data in NAND flash memory system 150. Flash controllers 140 service these IOPs, for example, by accessing NAND flash memory systems 150 to read or write the requested data from or into NAND flash memory systems 150 or by accessing one or more read and/or write caches (not illustrated in FIG. 1B) associated with NAND flash memory systems 150.

Flash controllers 140 implement a flash translation layer (FTL) that provides logical-to-physical address translation to enable access to specific memory locations within NAND flash memory systems 150. In general, an IOP received by flash controller 140 from a host device, such as a processor system 102, contains the logical block address (LBA) at which the data is to be accessed (read or written) and, if a write IOP, the write data to be written to data storage system 120. The IOP may also specify the amount (or size) of the data to be accessed. Other information may also be communicated depending on the protocol and features supported by data storage system 120. As is known to those skilled in the art, NAND flash memory, such as that employed in NAND flash memory systems 150, is constrained by its construction such that the smallest granule of data that can be accessed by a read or write IOP is fixed at the size of a single flash memory page, for example, 16 kilobytes (kB). The LBA provided by the host device corresponds to a logical page within a logical address space, the page typically having a size of 4 kilobytes. Therefore, more than one logical page may be stored in a physical flash page. The flash translation layer translates this LBA into a physical address assigned to a corresponding physical location in a NAND flash memory system 150. Flash controllers 140 may perform address translation and/or store mappings between logical and physical addresses in a logical-to-physical translation data structure, such as a logical-to-physical translation table (LPT), which may conveniently be stored in flash controller memory 142.

NAND flash memory systems 150 may take many forms in various embodiments. Referring now to FIGS. 2-5, there is depicted one exemplary arrangement of physical memory within a NAND flash memory system 150 in accordance with one exemplary embodiment.

As shown in FIG. 2, NAND flash memory system 150 may be formed from thirty-two (32) individually addressable NAND flash memory storage devices. In the illustrated example, each of the flash memory storage devices M0a-M15b takes the form of a board-mounted flash memory module capable of storing two or more bits per cell. Thus, flash memory modules may be implemented with Multi-Level Cell (MLC), Three Level Cell (TLC), or Quad Level Cell (QLC) memory. The thirty-two NAND flash memory modules are arranged in sixteen groups of two, (M0a, M0b) through (M15a, M15b). For purposes of the physical addressing scheme, each group of two modules forms a “lane,” also sometimes referred to as a “channel,” such that NAND flash memory system 150 includes sixteen channels or lanes (Lane0-Lane15).

In a preferred embodiment, each of the individual lanes has a respective associated bus coupling it to the associated flash controller 140. Thus, by directing its communications to one of the specific communication buses, flash controller 140 can direct its communications to one of the lanes of memory modules. Because each communication bus for a given lane is independent of the communication buses for the other lanes, a flash controller 140 can issue commands and send or receive data across the various communication buses at the same time, enabling the flash controller 140 to access the flash memory modules corresponding to the individual lanes at, or very nearly at, the same time.

With reference now to FIG. 3, there is illustrated an exemplary embodiment of a flash memory module 300 that can be utilized to implement any of flash memory modules M0a-M15b of FIG. 2. As shown in FIG. 3, the physical storage locations provided by flash memory module 300 are further subdivided into physical locations that can be addressed and/or identified through Chip Enables (CEs). In the example of FIG. 3, the physical memory of each flash memory chip 300 is divided into four Chip Enables (CE0, CE1, CE2 and CE3), each having a respective CE line that is asserted by flash controller 140 to enable access to or from the physical memory locations within the corresponding CE. Each CE is in turn subdivided into multiple dice (e.g., Die0 and Die1) each having two planes (e.g., Plane0 and Plane1). Each plane represents a collection of blocks (described below) that, because of the physical layout of the flash memory chips, are physically associated with one another and that utilize common circuitry (e.g., I/O buffers) for the performance of various operations, such as read and write operations.

As further shown in FIGS. 4-5, an exemplary plane 400, which can be utilized to implement any of the planes within flash memory module 300 of FIG. 3, includes, for example, 1024 or 2048 blocks of physical memory. Note that manufacturers often add some additional blocks as some blocks might fail early. In general, a block 500 is a collection of physical pages that are associated with one another, typically in a physical manner. This association is such that a block is defined to be the smallest granularity of physical storage locations that can be erased within NAND flash memory system 150. In the embodiment of FIG. 5, each block 500 includes, for example, 256 or 512 physical pages, where a physical page is defined to be the smallest individually addressable data unit for read and write access. In the exemplary system, each physical page of data has a common capacity (e.g., 16 kB) for data storage plus additional storage for metadata described in more detail below. Thus, data is written into or read from NAND flash memory system 150 on a page-by-page basis, but erased on a block-by-block basis.

Because NAND flash memory system 150 is implemented is a memory technology supporting multiple bits per cell, it is common for multiple physical pages of each block 500 to be implemented in the same set of memory cells. For example, assuming 512 physical pages per block 500 as shown in FIG. 5 and two bits per memory cell (i.e., NAND flash memory 150 is implemented in MLC memory), Page0 through Page255 (the lower pages) can be implemented utilizing the first bit of a given set of memory cells and Page256 through Page511 (the upper pages) can be implemented utilizing the second bit of the given set of memory cells. In many cases, the endurance of pages within a block 500 vary widely, and in some cases, this variation is particularly pronounced between lower pages (which may generally have a lower endurance) and upper pages (which may generally have a greater endurance). Consequently, as described further herein, it is desirable to be able to independently retire individual physical pages of memory without the necessity of retiring any other physical page in the same block 500, including the other physical page(s) implemented in a common set of memory cells with a retired physical page.

As further shown in FIG. 5, each block 500 preferably includes page status information 502, which indicates the status of each physical page in that block 500 as retired (i.e., no longer used to store user data) or non-retired (i.e., active or still usable to store user data). In various implementations, PSI 502 can be collected into a single data structure (e.g., a vector or table) within block 500, distributed within block 500 (e.g., as one or more bits of metadata appended to each physical page) and/or maintained elsewhere in data storage system 120. As one example, in the embodiment illustrated in FIG. 9 and discussed further below, the page status information of all blocks 500 in a NAND flash memory system 150 is collected in a system-level data structure, for example, a page status table (PST) 946 stored in GPP memory 134 or a flash controller memory 142.

Because the flash translation layer implemented by data storage system 120 isolates the logical address space made available to host devices from the physical memory within NAND flash memory system 150, the size of NAND flash memory system 150 need not be equal to the size of the logical address space presented to host devices. In most embodiments it is beneficial to present a logical address space that is less than the total available physical memory (i.e., to over-provision NAND flash memory system 150). Overprovisioning in this manner ensures that physical memory resources are available when the logical address space is fully utilized, even given the presence of a certain amount of invalid data as described above. In addition to invalid data that has not yet been reclaimed the overprovisioned space can be used to ensure there is enough logical space, even given the presence of memory failures and the memory overhead entailed by the use of data protection schemes, such as Error Correcting Code (ECC), Cycle Redundancy Check (CRC), and parity.

In some embodiments, data is written to NAND flash memory system 150 one physical page at a time. In other embodiments in which more robust error recovery is desired, data is written to groups of associated physical pages of NAND flash memory system 150 referred to herein as “page stripes.” In a preferred embodiment, all pages of a page stripe are associated with different lanes to achieve high write bandwidth. Because in many implementations the smallest erase unit is a block, page stripes can be grouped into a block stripe as is shown in FIG. 6A, where each block in the block stripe is associated with a different lane. When a block stripe is built, any free block of a lane can be chosen, but preferably all blocks within the same block stripe have the same or similar health grade. Note that the block selection can be further restricted to be from the same plane, die, and/or chip enable. The lengths of the block stripes can and preferably do vary, but in one embodiment in which NAND flash memory system 150 includes 16 lanes, each block stripe includes between two and sixteen blocks, with each block coming from a different lane. Further details regarding the construction of block stripes of varying lengths can be found in U.S. Pat. Nos. 8,176,284; 8,176,360; 8,443,136; and 8,631,273, which are incorporated herein by reference in their entireties.

Once a block from each lane has been selected and a block stripe is formed, page stripes are preferably formed from physical pages with the same page number from all blocks in the block stripe. While the lengths of the various page stripes stored into NAND flash memory system 150 can and preferably do vary, in one embodiment each page stripe includes one to fifteen data pages of write data (typically provided by a host device) and one additional page (a “data protection page”) used to store data protection information for the write data. For example, FIG. 6B illustrates an exemplary page stripe 610 including N data pages (i.e., Dpage00 through DpageN-1) and one data protection page (i.e., PpageN). The data protection page can be placed on any lane of the page stripe containing a non-retired page, but typically is on the same lane for all page stripes of the same block stripe to minimize metadata information. The addition of a data protection page as illustrated requires that garbage collection be performed for all page stripes of the same block stripe at the same time. After garbage collection of the block stripe completes, the block stripe can be dissolved, and each block can be placed into the relevant ready-to-use (RTU) queue as explained below.

FIG. 7 illustrates an exemplary format of a codeword stored in each data page within page stripe 610 of FIG. 6B. Typically, a positive integer number of codewords, for example, 2 or 3, are stored in each data page, but an alternative embodiment may also store a single codeword in a data page. In this example, each codeword 700 includes a data field 702, as well as additional fields for metadata describing the data page. Depending on the size of the codeword, the data field 702 holds data for one or more logical pages. In another embodiment it may also hold fractions of data of logical data pages. In the illustrated example, metadata fields include an LBA field 704 containing the LBAs stored in codeword 700, a CRC field 706 containing the CRC value computed for the combination of data field 702 and LBA field 704, and an ECC field 708 containing an ECC value calculated, in the illustrated example, from a combination of contents of data field 702, LBA field 704 and CRC field 706. In case data field 702 holds fractions of logical data pages, the LBA field 704 further holds information on which fractions of logical data pages are stored in the data field 702.

FIG. 8 depicts an exemplary format of a codeword in the data protection page of page stripe 610 of FIG. 6. In one embodiment, each data protection page stores a positive integer number of codewords, but an alternative embodiment a data protection page may store a single codeword. In the depicted example, data protection codeword 800 includes a data XOR field 802 that contains the bit-by-bit Exclusive OR (XOR) of the contents of the data fields 702 of the codewords 700 in page stripe 610. Data protection codeword 800 further includes an LBA XOR field 804 that contains the bit-by-bit XOR of the LBA fields 704 of the codewords 700 in page stripe 610. Data protection codeword 800 finally includes a CRC field 806 and ECC field 808 for respectively storing a CRC value and an ECC value for data protection codeword 800. Such a protection scheme is commonly referred to as RAID 5, since the parity field will not always be located on one particular flash plane. However, it should be appreciated that alternate data protection schemes such as Reed-Solomon can alternatively or additionally be used.

The formats for data pages and data protection pages described above protect data stored in a page stripe using multiple different data protection mechanisms. First, the use of the ECC bits in each data page allows the correction of some number of bit errors within the flash page. Depending on the ECC method used it may be possible correct hundreds of bits or even thousands of bits within a NAND flash page. After ECC checking and correction is performed, the corrected CRC field is used to validate the corrected data. Used together, these two mechanisms allow for the correction of relatively benign errors and the detection of more serious errors using only local intra-page information. Should an uncorrectable error occur in a data page, for example, due to failure of the physical page utilized to store the data page, the contents of the data field and LBA field of the failing data page may be reconstructed from the other data pages and the data protection page for the page stripe.

While the physical memory locations in which the data pages and data protection page of a page stripe will vary within NAND flash memory system 150, in one embodiment the data pages and data protection page that comprise a given page stripe are preferably stored in physical memory locations selected to optimize the overall operation of the data storage system 120. For example, in some embodiments, the data pages and data protection page comprising a page stripe are stored such that different physical lanes are employed to store each of the data pages and data protection page. Such embodiments support efficient access to a page stripe because flash controller 140 can access all of the pages of data that comprise the page stripe simultaneously or nearly simultaneously. It should be noted that the assignment of pages to lanes need not be sequential (i.e., data pages can be stored in any lane in any order), and unless a page stripe is a full length page stripe (e.g., containing fifteen data pages and one data protection page), the lanes utilized to store the page stripe need not be adjacent.

Having described the general physical structure and operation of one exemplary embodiment of a data storage system 120, certain operational aspects of data storage system 120 are now described with reference to FIG. 9, which is a high level flow diagram of the flash management functions and data structures employed by GPP 132 and/or flash controllers 140 in accordance with one embodiment.

As noted above, data storage system 120 does not generally allow external devices to directly address and/or access the physical memory locations within NAND flash memory systems 150. Instead, data storage system 120 is generally configured to present a single contiguous logical address space to the external devices, thus allowing host devices to read and write data to and from LBAs within the logical address space while permitting flash controllers 140 and GPP 132 to control where the data that is associated with the various LBAs actually resides in the physical memory locations comprising NAND flash memory systems 150. In this manner, performance and longevity of NAND flash memory systems 150 can be intelligently managed and optimized. In the illustrated embodiment, each flash controller 140 manages the logical-to-physical translation using a logical-to-physical translation data structure, such as logical-to-physical translation (LPT) table 900, which can be stored in the associated flash controller memory 142.

Flash management code running on the GPP 132 tracks erased blocks of NAND flash memory system 150 that are ready to be used in ready-to-use (RTU) queues 906, which may be stored, for example, in GPP memory 134. In the depicted embodiment, management code running on the GPP 132 preferably maintains one or more RTU queues 906 per channel, and an identifier of each erased block that is to be reused is enqueued in one of the RTU queues 906 corresponding to its channel. For example, in one embodiment, RTU queues 906 include, for each channel, a respective RTU queue 906 for each of a plurality of block health grades. In various implementations, between 2 and 8 RTU queues 906 per lane (and a corresponding number of block health grades) have been found to be sufficient.

A build block stripes function 920 performed by flash management code running on the GPP 132 constructs new block stripes for storing data and associated parity information from the erased blocks enqueued in RTU queues 906. As noted above with reference to FIG. 6A, block stripes are preferably formed of blocks of the same or similar health (i.e., expected remaining useful life) residing in different channels, meaning that build block stripes function 920 can conveniently construct a block stripe by drawing each block of the new block stripe from corresponding RTU queues 906 of different channels. The new block stripe is then queued to flash controller 140 for data placement.

In response to a write IOP received from a host, such as a processor system 102, a data placement function 910 of flash controller 140 determines by reference to LPT table 900 whether the target LBA(s) indicated in the write request is/are currently mapped to physical memory page(s) in NAND flash memory system 150 and, if so, changes the status of each data page currently associated with a target LBA to indicate that it is no longer valid. In addition, data placement function 910 allocates a page stripe if necessary to store the write data of the write IOP and any non-updated data (i.e., in case the write request is smaller than a logical page, there is still valid data which needs to be handled in a read-modify-write manner) from an existing page stripe, if any, targeted by the write IOP, and/or stores the write data of the write IOP and any non-updated (i.e., still valid) data from an existing page stripe, if any, targeted by the write IOP to an already allocated page stripe which has free space left. The page stripe may be allocated from either a block stripe already allocated to hold data or from a new block stripe built by build block stripes function 920. In a preferred embodiment, the page stripe allocation can be based on the health of the blocks available for allocation and the “heat” (i.e., estimated or measured write access frequency) of the LBA of the write data. Data placement function 910 then writes the write data, associated metadata (e.g., CRC and ECC values), and parity information for the page stripe in the allocated page stripe. Flash controller 140 also updates LPT table 900 to associate the physical page(s) utilized to store the write data with the LBA(s) indicated by the host device. Thereafter, flash controller 140 can access the data to service host read IOPs by reference to LPT table 900 as further illustrated in FIG. 9.

Once all pages in a block stripe have been written, flash controller 140 places the block stripe into one of occupied block queues 902, which flash management code running on the GPP 132 utilizes to facilitate garbage collection. As noted above, through the write process, pages are invalidated, and therefore portions of the NAND flash memory system 150 become unused. The associated flash controller 140 (and/or GPP 132) eventually needs to reclaim this space through garbage collection performed by a garbage collector 912. Garbage collector 912 selects particular block stripes for garbage collection based on a number of factors including, for example, the health of the blocks within the block stripes and how much of the data within the erase blocks is invalid. In the illustrated example, garbage collection is performed on entire block stripes, and flash management code running on GPP 132 logs the block stripes ready to be recycled in a relocation queue 904, which can conveniently be implemented in the associated flash controller memory 142 or GPP memory 134.

The flash management functions performed by GPP 132 or flash controller 140 additionally include a relocation function 914 that relocates the still valid data held in block stripes enqueued in relocation queue 904. To relocate such data, relocation function 914 updates LPT table 900 to remove the current association between the logical and physical addresses of the data. In addition, relocation function 914 issues relocation write requests to data placement function 910 to request that the data of the old block stripe be written to a new block stripe in NAND flash memory system 150. Once all still valid data has been moved from the old block stripe, the old block stripe is passed to dissolve block stripes function 916, which decomposes the old block stripe into its constituent blocks, thus disassociating the blocks. Flash controller 140 then erases each of the blocks formerly forming the dissolved block stripe and increments an associated program/erase (P/E) cycle count for the block in P/E cycle counts 944. Based on the health metrics of each erased block, each erased block is either retired (i.e., no longer used to store user data) by a block retirement function 918 among the flash management functions executed on GPP 132, or alternatively, prepared for reuse by placing the block's identifier on the appropriate ready-to-use (RTU) queue 906 in the associated GPP memory 134.

As further shown in FIG. 9, flash management functions executed on GPP 132 include a background health checker 930. Background health checker 930, which operates independently of the demand read and write IOPs of hosts such as processor systems 102, continuously determines one or more block health metrics 942 for blocks belonging to block stripes recorded in occupied block queues 902. Based on the one or more of the block health metrics 942, background health checker 930 may place block stripes on relocation queue 904 for handling by relocation function 914.

Referring now to FIG. 10, there is depicted a more detailed view of a flash controller 140 in accordance with one embodiment. In this embodiment, flash controller 140 is configured (e.g., in hardware, firmware, software or some combination thereof) to support retirement of memory in flash memory modules M0a, M0b, M1a, M1b, . . . , M1a, and M15b of a NAND flash memory system 150 on a page-by-page basis rather than on a block-by-block basis. Flash controller 140 is further configured to retire a physical page of memory while still keeping active other physical page(s) sharing a common set of multiple-bit memory cells with the retired physical page.

In the illustrated embodiment, flash controller 140 includes a compressor 1000 that selectively applies one or more data compression algorithms to data written to the associated NAND flash memory system 150, a decompressor 1002 that decompresses compressed data read from NAND flash memory system 150, and a data scrambler 1004. Flash controller 140 utilizes data scrambler 1004 to apply a predetermined data scrambling (i.e., randomization) pattern to data written to NAND flash memory 150 in order to improve endurance and mitigate cell-to-cell interference.

As further illustrated in FIG. 10, flash controller 140 includes a write cache 1010. Write cache 1010 includes storage for one or more cache lines 1012 for buffering write data in anticipation of writing the data to NAND flash memory system 150. In the illustrated embodiment, each cache line 1012 includes multiple (e.g., 16) segments 1014a-1014p, each providing storage for a respective page stripe of up to sixteen data pages (a maximum of fifteen data pages and one data protection page). As shown, for ease of implementation, it is preferred if flash controller 140 writes each page buffered in a given segment 1014 of cache line 1012 to the corresponding die index, plane index, and physical page index in each of sixteen flash memory modules. Thus, for example, flash controller 140 writes the data pages from segment 1014a to a first physical page (e.g., Page23) in each of flash memory modules M0a-M15a, writes the data pages from segment 1014b to a second physical page in each of flash memory modules M0a-M15a, and writes the data pages from segment 1014p to a sixteenth physical page in each of flash memory modules M0a-M15a.

With reference now to FIG. 11, there is illustrated a high level logical flowchart of an exemplary method of performing a read operation in a data storage system 120 in which physical memory may be retired on a page basis. The method may be performed, for example, by a flash controller 140 and/or GPP 132 in hardware, firmware, software or a combination thereof. For simplicity of explanation, it will hereafter be assumed that the process is performed by flash controller 140. As with the other flowcharts provided herein, steps are presented in logical rather than strictly chronological order, and in some embodiments at least some of the steps may be performed in an alternative order or concurrently.

The illustrated process begins at block 1100 and then proceeds to block 1102, which illustrates flash controller 140 awaiting receipt of a read IOP (read request) from an external host device, such as processor system 102. In general, the read IOP received by flash controller 140 will specify an LBA of a target data page that is requested by the host device, where the LBA may itself be the result of one or more levels of translation of an original LBA received by data storage system 120. In response to receipt of the read IOP, flash controller 140 translates the LBA by reference to LPT 900 to determine the physical address of the physical pages that stores the requested data page (block 1104). Once the physical address is determined, flash controller 124 accesses the target data page utilizing the physical address by issuing a read request to read the target data page from the physical page associated with the physical address (block 1106). The read IOP may request various sizes of data, but for simplification it is assumed that the flowchart given in FIG. 11 will be exercised once for each logical page referenced by the read IOP.

At block 1108, flash controller 140 performs ECC decoding for the data page to attempt to correct any bit errors in the data page. In the depicted embodiment, if the bit errors, if any, in the data page are correctable, the ECC decoder within flash controller 140 corrects the bit errors and returns the number of such bit errors and a correctable status. For example, the ECC decoder will determine that bit errors are correctable if there are 50 bits in error within the codeword and the ECC is capable of correcting greater than 50 bits in error within the codeword. If, on the other hand, the bit errors in the data page are uncorrectable, the ECC decoder returns an uncorrectable status. It will be appreciated that bit errors in the data page can be caused by a variety of factors including, but not limited to, the physical failure of one or more components within a given memory chip (such as the failure of a charge pump), the physical failure of an entire memory chip or the external support structures for that chip (e.g., the breaking of a power line or an address line to a chip), the physical failure of all or part of a chip as a result of environmental factors (e.g., excessive temperature, magnetic field, humidity, etc), trapped charge in the oxide layer of the physical device, leakage of charge from the floating gate (or similar charge trap device) of a memory cell, and/or electrical noise inflicted by writes or reads of adjacent memory cells. It should also be noted that physical regions within a NAND flash memory system can and do exhibit dramatic variations in the probability of bit errors. For example, the probability of having a bit error occurring in page 5 of a block of a particular flash memory product could be 1%, while the probability of a bit error occurring in page 10 of the same block could be 0.001%. Similar variability in the probability of bit errors can also be observed between modules, dies, planes, and blocks of the same flash memory product.

At block 1110, flash controller 140 determines whether or not the ECC decoder returned a correctable status for the data page. If so, in one embodiment, the process passes directly to block 1130, which is described below. However, in response to a determination at block 1110 that the ECC decoder did not return a correctable status for the data page (i.e., the ECC decoder returned an uncorrectable status for the data page), the process proceeds to block 1116.

At block 1116, flash controller 140 marks only the physical page that stores the target data page as retired (i.e., no longer available for allocation to store a data page of user data in a new page stripe) in PST 946 and/or the PSI 502 of the block containing that physical page. FIG. 12 illustrates a logical view of the contents of PST 946 in which the statuses of the physical pages comprising each block in a NAND flash memory system 150 are represented by a bit vector in which a 1 indicates an active page and a 0 indicates a retired page. Thus, in this embodiment, at block 1116 flash controller 140 resets the bit corresponding to the retired physical page from 1 to 0 in PST 946. In this manner, data storage system 120 retires physical memory in NAND flash memory system 150 on a page-by-page basis (rather than on a block-by-block basis). As will be appreciated, retirement of a physical page of physical memory (e.g., 16 kB) rather than a block (e.g., 4 MB) conserves physical memory resources, enhancing the performance and extending the life of NAND flash memory system 150. However, as a consequence of page retirement, the effective sizes of blocks of physical memory of NAND flash memory system 140 will vary, as described further below.

This exemplary implementation waits until a physical page has one or more codewords containing uncorrectable errors before performing the retirement. However, certain implementations may choose to retire a physical page at some point prior to uncorrectability. For example, in one embodiment, flash controller 140 further determines at block 1112 whether the number of corrected bit errors satisfies (e.g., is less than) a bit error threshold T3 lower than the ECC correction threshold. For example, if an implementation uses BCH ECC over approximately 1024 bytes and can correct 50 bits in error, flash controller 140 may decide to retire a page when the number of corrected bit errors reaches a number less than 50, say 48. In such implementations, the process passes from block 1112 to block 1116 in response to a negative determination at block 1112. Additionally, one skilled in the art will also know that, depending on the flash technology used, that flash controller 140 may elect to perform additional steps at block 1110 before determining that the page is truly uncorrectable and should be retired. For example, the flash manufacturer may require flash controller 140 to change certain parameters for that page or block and perform a re-read of the page. If the bit errors, if any, detected upon the re-read are correctable, then flash controller 140 would follow the “Yes” path from block 1110 (and block 1112, if present) to block 1130. In this way, block 1110 may contain many additional steps that, although not illustrated in detail, are performed in determining that the page contains a truly uncorrectable error.

At block 1118, flash controller 140 further determines by reference to PSI 502 whether or not the number of retired pages of physical memory in a physical memory region containing the physical page retired at block 1116 now satisfies (e.g., is greater than and/or equal to) a first threshold T1. In at least some embodiments, the first threshold T1 is configurable. Performance testing has shown that performance of data storage system 120 is optimized if the first threshold T1 is less than about 10% of the physical pages in the physical memory region and, more particularly, is configured to be about 5% of the physical pages in the physical memory region. Still more particularly, it is preferable if the first threshold T1 is configured to be about 4% of the physical pages in the physical memory region. These numbers are exemplary only and can vary dramatically based on the use and requirements of the data storage system. The physical memory region to which the first threshold T1 pertains can be, for example, a block, plane, die, CE or entire flash module.

In response to flash controller 140 determining at block 1118 that the first threshold is not satisfied, the process passes from block 1118 to block 1130. However, in response to flash controller 140 determining at block 1118 that the first threshold T1 is satisfied, flash controller 140 marks the entire physical memory region containing the retired physical page as retired and thus unavailable for allocation to store new page stripes of user data (block 1120). If the physical memory region for which retirement is determined at block 1118-1120 is a smaller region than an entire flash memory module, flash controller 140 may optionally determine whether or not to retire larger physical memory regions containing the retired physical page, as shown at optional blocks 1122-1124. As indicated, the additional determination regarding retirement of larger physical memory regions can be based on a comparison of the number of retired physical memory regions (e.g., pages, blocks, planes, dies or CEs) within the larger physical memory region and a second threshold T2 (which may differ from threshold T1). The process proceeds from either block 1120 or one of blocks 1122 and 1124 to block 1130. It may also be determined that there are now too many retired memory resources within NAND flash memory system 140 to be able to achieve required performance levels, and flash controller 140 may send a response to the user indicating that it is time to replace the physical resource containing NAND flash memory system 150.

At block 1130, flash controller 140 attempts to validate the data field 702 and LBA field 704 of the target data page by computing a cyclic redundancy code and comparing the computed CRC to that contained in CRC field 706. In response to successful validation of the data page, the process proceeds to block 1134, which is described below. However, in response to failure of the CRC validation, flash controller 140 reads the entire page stripe and recovers the correct content of the target data page from the other data page(s) and the data protection page of the page stripe (block 1132). In addition, flash controller 140 relocates the page stripe (including the recovered target data page) to a different physical location in NAND flash memory system 120, for example, utilizing relocation function 914. From block 1130 or block 1132, the process proceeds to block 1134, which illustrates flash controller 140 decompressing the target data page utilizing decompressor 1002 and transmitting the decompressed target data page to the requesting host device. Thereafter, the process of FIG. 11 terminates at block 1140.

As noted above, the order of operations set forth in FIG. 11 is exemplary and embodiments are contemplated where the order of operations is different from that set out above. For example, embodiments are contemplated in which flash controller 140 transmits the decompressed target data page to the host device prior to completing CRC validation and thereafter transmits an indication of whether the target data page is valid or not. Also in some embodiments, the read IOP may access multiple target data pages (e.g., a cache line of data pages) rather than a single target data page.

With reference now to FIG. 13, there is illustrated a high level logical flowchart of an exemplary method of performing a write operation in a data storage system 120 in which physical memory may be retired on a page basis. The method may be performed, for example, by flash controller 140 and/or GPP 132 in hardware, firmware, software or a combination thereof. For simplicity of explanation, it will hereafter be assumed that the process is performed by flash controller 140.

The method of FIG. 13 begins at block 1300 and then proceeds to block 1302, which illustrates flash controller 140 awaiting receipt of a write IOP from a host device, such as processor system 102. The write IOP includes, for example, a cache line of write data to be written into NAND flash memory system 150 and an indication of the base LBA at which the host device would like for the write data to be stored. In response to receipt of a write IOP, the process proceeds from block 1302 to blocks 1304-1306, which illustrate flash controller 140 determining by reference to LPT table 900 whether the target LBAs indicated by the write IOP are currently mapped to physical memory pages and, if so, changing the status of each data page currently associated with one of the target LBAs to indicate that it is no longer valid. As is known in the art, invalidated pages (and the blocks containing them) will eventually be erased and again made available for allocation to store data by garbage collector 912 of flash controller 140.

At block 1308, flash controller 140 allocates a write cache line 1012 in write cache 1010 to buffer the write data of the write IOP (write request) and initializes the contents of the allocated write cache line 1012 to all 0s. In addition, at block 1310, flash controller 140 allocates physical pages in NAND flash memory system 150 to form page stripes to store the write data and retrieves the page status information for the allocated physical pages from PST 946. As noted above with reference to FIG. 10, for simplicity flash controller 140 preferably forms each page stripe from corresponding physical pages of blocks in different lanes. Given the retirement of individual physical pages as discussed above with reference to FIG. 11, the retrieved page status information may indicate that one or more of the physical pages allocated to form the page stripes is/are retired. For example, FIG. 14A illustrates write cache 1010 in an exemplary scenario in which the retrieved page status information for the page stripe corresponding to segment 1014a includes one retired physical page (denoted by a 0), the page stripe corresponding to segment 1014b includes two retired physical pages, and the page stripe corresponding to segment 1014p includes one retired physical page.

At block 1312, flash controller assigns storage for the data protection (e.g., parity)) page of each page stripe to a physical page that is identified by the page status information as an active (i.e., non-retired) page. Although not required, metadata storage is reduced if corresponding physical pages of each page stripe are utilized to store the parity information (e.g., Dpage15 of each page stripe).

Block 1314 illustrates flash controller 140 utilizing compressor 1000 to compress the logical pages of write data specified by the write IOP and then filing segments 1014a-1014p of write cache line 1012 with the compressed logical pages. In filling segments 1014a-1014p at block 1314, any lanes corresponding to retired physical pages are skipped. Flash controller 140 also computes parity information for each page stripe (e.g., by performing a bit-by-bit XOR of all the data pages in the page stripe) and buffers the resulting data protection pages in the storage locations in segments 1014 corresponding to the allocated data protection pages of the page stripes (block 1316). Because the storage locations in segments 1014 corresponding to retired physical pages have a value of all 0s, the contents of these storage locations can be included in the parity computation without affecting the resulting parity information.

FIG. 14B illustrates contents of write cache line 1012 following block 1314 in one exemplary scenario. As shown, in this scenario, storage locations corresponding to retired physical pages (e.g., storage locations 1400a-1400d) remain filled with their initial values of all 0s, storage locations 1402a-1402p corresponding to data protection pages contain parity information, and the remainder of the storage locations within write cache line 1012 contain compressed data pages of user data 1404.

As indicated at block 1318 of FIG. 13, flash controller 140 then utilizes data scrambler 1004 to apply a predetermined scrambling pattern to the contents of each storage location in write cache line 1012 (regardless of the page status of the corresponding physical page) and writes the resulting scrambled data page to the corresponding physical pages in NAND flash memory system 150 (again regardless of the page status of the physical page). Thus, at block 1318, flash controller 140 writes scrambled data pages to both active physical pages and retired physical pages of NAND flash memory 150, where the scrambled data pages written to retired physical pages do not contain any user (e.g., host) data but merely include the predetermined scrambling pattern (i.e., “dummy” data). In this manner, the memory cells corresponding to the retired physical pages are not withdrawn from use, meaning that other physical page(s) sharing the same memory cells can continue to be used to store user data despite the retirement of at least one physical page utilizing the memory cells. In addition, by writing the predetermined scrambling pattern to the retired physical pages, the retired physical pages continue to support the improved performance attributable to having a pseudo-random distribution of bits.

At block 1320, flash controller 140 additionally computes the CRC and ECC values for each data page and stores those values into the CRC field 706 and ECC field 708 of the data page. Flash controller 140 also updates the LPT table 900 to associate the physical pages allocated to store the write data with the LBAs indicated by the host device (block 1320). It should be noted that the retired physical pages remain unmapped by LPT table 900 and are therefore inaccessible to read IOPs. Following block 1322, the process of FIG. 13 ends at block 1324.

It should be noted that blocks 1318 and 1320 will include steps that check whether or not the programming of a physical page completed correctly. If flash controller 140 determines that the write of a physical page did not complete correctly, then flash controller 140 will employ various recovery techniques, such as retrying the write operation. If the write eventually passes, then flash controller 140 will complete successfully. However, if the write is unsuccessful, then flash controller 140 will retire the allocated physical page in the same manner as when a read is unsuccessful. Having retired a physical page, flash controller 140 will change its tables accordingly and allocate an alternative active (i.e., non-retired) physical page to complete either block 1318 or 1320.

With reference now to FIG. 15, there is illustrated a graph depicting the endurance gain achieved in an exemplary NAND flash memory system having multi-bit memory cells by implementing page retirement in accordance with one embodiment. FIG. 15 represents P/E cycle count along the X-axis and a selected BER metric for a block (in this case worst page BER) along the Y-axis. A similar graph would be obtained for other BER metrics, such as mean page BER.

At reference numeral 1500 of FIG. 8, a desired upper BER threshold is illustrated. This upper BER threshold 1500 can represent, for example, the maximum number of bit errors that can be corrected by the ECC implemented by an exemplary flash memory module. Thus, the page retirement policy of flash controller 140 is preferably selected to maintain the BER metric (in this case, the worst page BER) under upper BER threshold 1500.

FIG. 15 further illustrates curves 1502-1504, which respectively correspond to the worst page BERs if page retirement is not employed and if page retirement as disclosed herein is employed. As can be seen by comparison of curves 1502 and 1504, if page retirement is implemented as described herein, the worst page BER crosses upper BER threshold 1500 at a significantly higher P/E cycle count, resulting in a significantly greater endurance (e.g., approximately 40% greater) in terms of P/E cycle count.

The present invention may be a system, a method, and/or a computer program product. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention.

The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

Computer readable program instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network. The network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. A network adapter card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing/processing device.

Computer readable program instructions for carrying out operations of the present invention may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like, and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present invention.

Aspects of the present invention are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer readable program instructions.

These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks.

The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.

As has been described, a controller of a non-volatile memory array retires physical pages within the non-volatile memory array on a page-by-page basis. The physical pages retired by the controller include a first physical page sharing a common set of memory cells with a second physical page. While the first physical page is retired, the controller retains the second physical page as an active physical page, writes dummy data to the first physical page, and writes data received from a host to the second physical page.

While the present invention has been particularly shown as described with reference to one or more preferred embodiments, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention. For example, although aspects have been described with respect to a data storage system including a flash controller that directs certain functions, it should be understood that present invention may alternatively be implemented as a program product including a storage device storing program code that can be processed by a processor to perform such functions or cause such functions to be performed. As employed herein, a “storage device” is specifically defined to include only statutory articles of manufacture and to exclude transitory propagating media per se.

In addition, although embodiments have been described that include use of a NAND flash memory, it should be appreciated that embodiments of the present invention can also be used with other types of non-volatile random access memory (NVRAM) including, for example, phase-change memory (PCM) and combinations thereof.

The figures described above and the written description of specific structures and functions below are not presented to limit the scope of what Applicants have invented or the scope of the appended claims. Rather, the figures and written description are provided to teach any person skilled in the art to make and use the inventions for which patent protection is sought. Those skilled in the art will appreciate that not all features of a commercial embodiment of the inventions are described or shown for the sake of clarity and understanding. Persons of skill in this art will also appreciate that the development of an actual commercial embodiment incorporating aspects of the present inventions will require numerous implementation-specific decisions to achieve the developer's ultimate goal for the commercial embodiment. Such implementation-specific decisions may include, and likely are not limited to, compliance with system-related, business-related, government-related and other constraints, which may vary by specific implementation, location and from time to time. While a developer's efforts might be complex and time-consuming in an absolute sense, such efforts would be, nevertheless, a routine undertaking for those of skill in this art having benefit of this disclosure. It must be understood that the inventions disclosed and taught herein are susceptible to numerous and various modifications and alternative forms. Lastly, the use of a singular term, such as, but not limited to, “a” is not intended as limiting of the number of items.

DUMMY PAGE INSERTION FOR FLEXIBLE PAGE RETIREMENT IN FLASH MEMORY STORING MULTIPLE BITS PER MEMORY CELL

Information

Publication Number

Date Filed

Date Published

Inventors

Original Assignees

CPC

International Classifications

Abstract

Description

Claims