Patent Application
20120249519
This disclosure relates to display devices, including but not limited to display devices that incorporate electromechanical systems.
Electromechanical systems include devices having electrical and mechanical elements, actuators, transducers, sensors, optical components (e.g., mirrors) and electronics. Electromechanical systems can be manufactured at a variety of scales including, but not limited to, microscales and nanoscales. For example, microelectromechanical systems (MEMS) devices can include structures having sizes ranging from about a micron to hundreds of microns or more. Nanoelectromechanical systems (NEMS) devices can include structures having sizes smaller than a micron including, for example, sizes smaller than several hundred nanometers. Electromechanical elements may be created using deposition, etching, lithography, and/or other micromachining processes that etch away parts of substrates and/or deposited material layers, or that add layers to form electrical and electromechanical devices.
One type of electromechanical systems device is called an interferometric modulator (IMOD). As used herein, the term interferometric modulator or interferometric light modulator refers to a device that selectively absorbs and/or reflects light using the principles of optical interference. In some implementations, an interferometric modulator may include a pair of conductive plates, one or both of which may be transparent and/or reflective, wholly or in part, and capable of relative motion upon application of an appropriate electrical signal. In an implementation, one plate may include a stationary layer deposited on a substrate and the other plate may include a reflective membrane separated from the stationary layer by an air gap. The position of one plate in relation to another can change the optical interference of light incident on the interferometric modulator. Interferometric modulator devices have a wide range of applications, and are anticipated to be used in improving existing products and creating new products, especially those with display capabilities.
In many displays, pixels are made uniform throughout the display except at the edge. The same basic masks, processes, etc., are generally used to make all other pixels. However, edge pixels are treated differently. Edge pixels are the only pixels in an array that do not have the same types of structures on both sides.
In general, these edge pixels are not used as part of the “active area” of pixels that is used for the display. In some pixel arrays, photo-resist or black mask material may be used to obscure the edge pixels. Some edge pixels may draw power, move, etc., even though they are not part of the active display area.
The systems, methods and devices of the disclosure each have several innovative aspects, no single one of which is solely responsible for the desirable attributes disclosed herein.
One innovative aspect of the subject matter described in this disclosure can be implemented in an apparatus that includes a small conductive via inside edge subpixels of a passively-addressed display, such as a MEMS-based display. The vias may be configured to make an electrical connection between a movable conductive layer and another conductive layer of the edge subpixel. The vias can prevent the edge subpixels from actuating. The wiring into the active area of the array may pass through the edge pixel by way of these vias in the edge subpixels.
Various implementations of display devices are described herein. Some of these display devices include passively-addressed displays. Some such display devices include a routing area, an active subpixel array and an edge subpixel array. The active subpixel array may include rows and columns of active subpixels. The edge subpixel array may include rows and columns of edge subpixels configured to provide electrical connectivity between the routing area and the active subpixels. Each of the edge subpixels and the active subpixels may include a first conductive layer and a second conductive layer. At least one of the edge subpixels in each row or column also may include a via configured to provide electrical connectivity between the first conductive layer and the second conductive layer.
Each of the edge subpixels and the active subpixels may include a plurality of posts disposed between the first conductive layer and the second conductive layer. The vias may be disposed proximate the posts. Alternatively, a via may be formed in at least one of the posts in each row and column of edge subpixels.
The second conductive layer of each active subpixel may be configured to be movable relative to the first conductive layer when a sufficient voltage is applied between the first conductive layer and the second conductive layer. The second conductive layer may be formed, at least in part, of a reflective material. The edge subpixels and the active subpixels may include electromechanical systems (“EMS”)-based devices. The display may be an organic light-emitting diode (“OLED”) display or a field emission display.
The first conductive layer may be configured to provide electrical connectivity between a row or a column of active subpixels. The second conductive layer may be configured to provide electrical connectivity between a row or a column of active subpixels.
The display device may include a processor that is configured to communicate with the display and a memory device that is configured to communicate with the processor. The processor may be configured to process image data. The display device may include a driver circuit configured to send at least one signal to the display and a controller configured to send at least a portion of the image data to the driver circuit. The display device may include an input device configured to receive input data and to communicate the input data to the processor.
The display device may include an image source module configured to send the image data to the processor. The image source module may include a receiver, a transceiver and/or a transmitter.
Various methods are also described herein. Some such methods involve forming an optical stack, including a first conductive layer, over a substrate, forming a plurality of support structures on the optical stack or on the substrate and forming a second conductive and reflective layer on the support structures. The methods may involve forming an array of active subpixels that include the first conductive layer, the support structures and the second conductive layer such that the second conductive and reflective layer is movable between a first position and a second position when a voltage is applied to the active subpixels.
The methods may involve forming routing area outside the array of active subpixels and forming an edge subpixel array including rows and columns of edge subpixels. The edge subpixels may be configured to provide electrical connectivity between the routing area and the active subpixels. Each of the edge subpixels may include the first conductive layer, the second and reflective conductive layer and the support structures. At least one of the edge subpixels in each row or column may include a via configured to provide electrical connectivity between the first conductive layer and the second conductive and reflective layer.
The methods may involve isolating the first conductive layer or the second conductive and reflective layer of adjacent edge subpixels. The process of forming the edge subpixel array may include forming the vias in the support structures of the edge subpixels. The process of forming the edge subpixel array may involve forming the vias proximate the support structures of the edge subpixels. The process of forming the edge subpixel array may include forming a via in each edge subpixel. The second conductive and reflective layer of the edge subpixels may not be configured to be movable when the edge subpixels provide electrical connectivity between the routing area and the active subpixels.
Various alternative implementations of display devices are described herein, some of which include passively-addressed displays. These display devices may include routing apparatus, active subpixel apparatus and edge subpixel apparatus. The active subpixel apparatus may include a first conductive layer and a second conductive layer. The second conductive layer may be formed, at least in part, from reflective material. The active subpixel apparatus may include apparatus for controlling an optical cavity by moving the second conductive layer from a first position to a second position. The edge subpixel apparatus may be configured for providing electrical connectivity between the routing apparatus. The edge subpixel apparatus also may be configured for providing electrical connectivity between the first conductive layer and the second conductive layer.
The edge subpixel apparatus and the active subpixel apparatus may include a plurality of posts disposed between the first conductive layer and the second conductive layer. The apparatus for providing electrical connectivity between the first conductive layer and the second conductive layer may include a via formed in at least one of the posts in each row and column of edge subpixels. The first conductive layer may be configured to provide electrical connectivity between a row or a column of active subpixels.
The edge subpixel apparatus and the active subpixel apparatus may include electromechanical systems (“EMS”)-based devices. The display may be an organic light-emitting diode (“OLED”) display or a field emission display.
Details of one or more implementations of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Although the examples provided in this summary are primarily described in terms of MEMS-based displays, the concepts provided herein apply to other types of passively-addressed displays, such as organic light-emitting diode (“OLED”) displays and field emission displays. Other features, aspects, and advantages will become apparent from the description, the drawings, and the claims. Note that the relative dimensions of the following figures may not be drawn to scale.
Like reference numbers and designations in the various drawings indicate like elements.
The following detailed description is directed to certain implementations for the purposes of describing the innovative aspects. However, the teachings herein can be applied in a multitude of different ways. The described implementations may be implemented in any device that is configured to display an image, whether in motion (e.g., video) or stationary (e.g., still image), and whether textual, graphical or pictorial. More particularly, it is contemplated that the implementations may be implemented in or associated with a variety of electronic devices such as, but not limited to, mobile telephones, multimedia Internet enabled cellular telephones, mobile television receivers, wireless devices, smartphones, bluetooth devices, personal data assistants (PDAs), wireless electronic mail receivers, hand-held or portable computers, netbooks, notebooks, smartbooks, tablets, printers, copiers, scanners, facsimile devices, GPS receivers/navigators, cameras, MP3 players, camcorders, game consoles, wrist watches, clocks, calculators, television monitors, flat panel displays, electronic reading devices (e.g., e-readers), computer monitors, auto displays (e.g., odometer display, etc.), cockpit controls and/or displays, camera view displays (e.g., display of a rear view camera in a vehicle), electronic photographs, electronic billboards or signs, projectors, architectural structures, microwaves, refrigerators, stereo systems, cassette recorders or players, DVD players, CD players, VCRs, radios, portable memory chips, washers, dryers, washer/dryers, parking meters, packaging (e.g., electromechanical systems (EMS), MEMS and non-MEMS), aesthetic structures (e.g., display of images on a piece of jewelry) and a variety of electromechanical systems devices. The teachings herein also can be used in non-display applications such as, but not limited to, electronic switching devices, radio frequency filters, sensors, accelerometers, gyroscopes, motion-sensing devices, magnetometers, inertial components for consumer electronics, parts of consumer electronics products, varactors, liquid crystal devices, electrophoretic devices, drive schemes, manufacturing processes and electronic test equipment. Thus, the teachings are not intended to be limited to the implementations depicted solely in the Figures, but instead have wide applicability as will be readily apparent to one having ordinary skill in the art.
Some edge pixels may draw power, move, etc., even though they are not part of the active display area. For example, some displays actively drive the edge pixels using a separate drive scheme from that of the pixels in the active display area. Driving the edge pixels in this manner wastes power and adds complexity.
According to some implementations provided herein, edge subpixels of passively-addressed displays are inactive “dummy” subpixels. Some such implementations are made inactive by including a via in each of the edge subpixels, whereas other implementations are made inactive by including at least one via in each subpixel row or column. The edge subpixel vias electrically connect a first conductive layer with a second conductive layer. The active subpixels are driven by applying a voltage between the first conductive layer with the second conductive layer. Because the vias electrically connect the first conductive layer with the second conductive layer of the edge subpixels, the edge subpixels are not actuated when the active subpixels are driven, because no potential difference is created between the first conductive layer and the second conductive layer of the edge subpixels.
Particular implementations of the subject matter described in this disclosure can be implemented to realize one or more of the following potential advantages. Because the vias cause the edge subpixels to become inactive, the edge subpixels do not draw power and do not require a separate drive scheme. Therefore, displays that include edge subpixels as described herein may be more energy efficient and may be somewhat simpler to operate. After the vias are included, the edge subpixels may become slightly more conductive than edge subpixels without such vias. The edge subpixels may, in effect, become part of the routing. In addition, the visual appearance of the edge subpixels can be independent of the driving voltages in the active array and therefore the edge subpixels may be suitable to use as a uniform view area border of the display. In some drive schemes, it is not possible to predict the behavior of ordinary subpixels that are not fully addressed (valid waveforms on both row and column). Various implementations described herein obviate the requirement of having extra driver outputs to control the visual appearance of the edge subpixels.
An example of a suitable electromechanical systems (EMS) or MEMS device, to which the described implementations may apply, is a reflective display device. Reflective display devices can incorporate interferometric modulators (IMODs) to selectively absorb and/or reflect light incident thereon using principles of optical interference. IMODs can include an absorber, a reflector that is movable with respect to the absorber, and an optical resonant cavity defined between the absorber and the reflector. The reflector can be moved to two or more different positions, which can change the size of the optical resonant cavity and thereby affect the reflectance of the interferometric modulator. The reflectance spectrums of IMODs can create fairly broad spectral bands which can be shifted across the visible wavelengths to generate different colors. The position of the spectral band can be adjusted by changing the thickness of the optical resonant cavity, i.e., by changing the position of the reflector.
The IMOD display device can include a row/column array of IMODs. Each IMOD can include a pair of reflective layers, i.e., a movable reflective layer and a fixed partially reflective layer, positioned at a variable and controllable distance from each other to form an air gap (also referred to as an optical gap or cavity). The movable reflective layer may be moved between at least two positions. In a first position, i.e., a relaxed position, the movable reflective layer can be positioned at a relatively large distance from the fixed partially reflective layer. In a second position, i.e., an actuated position, the movable reflective layer can be positioned more closely to the partially reflective layer. Incident light that reflects from the two layers can interfere constructively or destructively depending on the position of the movable reflective layer, producing either an overall reflective or non-reflective state for each pixel. In some implementations, the IMOD may be in a reflective state when unactuated, reflecting light within the visible spectrum, and may be in a dark state when unactuated, reflecting light outside of the visible range (e.g., infrared light). In some other implementations, however, an IMOD may be in a dark state when unactuated, and in a reflective state when actuated. In some implementations, the introduction of an applied voltage can drive the pixels to change states. In some other implementations, an applied charge can drive the pixels to change states.
The depicted portion of the pixel array in
In
The optical stack 16 can include a single layer or several layers. The layer(s) can include one or more of an electrode layer, a partially reflective and partially transmissive layer and a transparent dielectric layer. In some implementations, the optical stack 16 is electrically conductive, partially transparent and partially reflective, and may be fabricated, for example, by depositing one or more of the above layers onto a transparent substrate 20. The electrode layer can be formed from a variety of materials, such as various metals, for example indium tin oxide (ITO). The partially reflective layer can be formed from a variety of materials that are partially reflective, such as various metals, e.g., chromium (Cr), semiconductors, and dielectrics. The partially reflective layer can be formed of one or more layers of materials, and each of the layers can be formed of a single material or a combination of materials. In some implementations, the optical stack 16 can include a single semi-transparent thickness of metal or semiconductor which serves as both an optical absorber and conductor, while different, more conductive layers or portions (e.g., of the optical stack 16 or of other structures of the IMOD) can serve to bus signals between IMOD pixels. The optical stack 16 also can include one or more insulating or dielectric layers covering one or more conductive layers or a conductive/absorptive layer.
In some implementations, the layer(s) of the optical stack 16 can be patterned into parallel strips, and may form row electrodes in a display device as described further below. As will be understood by one having skill in the art, the term “patterned” is used herein to refer to masking as well as etching processes. In some implementations, a highly conductive and reflective material, such as aluminum (Al), may be used for the movable reflective layer 14, and these strips may form column electrodes in a display device. The movable reflective layer 14 may be formed as a series of parallel strips of a deposited metal layer or layers (orthogonal to the row electrodes of the optical stack 16) to form columns deposited on top of posts 18 and an intervening sacrificial material deposited between the posts 18. When the sacrificial material is etched away, a defined gap 19, or optical cavity, can be formed between the movable reflective layer 14 and the optical stack 16. In some implementations, the spacing between posts 18 may be approximately 1-1000 um, while the gap 19 may be less than 10,000 Angstroms (Å).
In some implementations, each pixel of the IMOD, whether in the actuated or relaxed state, is essentially a capacitor formed by the fixed and moving reflective layers. When no voltage is applied, the movable reflective layer 14 remains in a mechanically relaxed state, as illustrated by the IMOD 12 on the left in
The processor 21 can be configured to communicate with an array driver 22. The array driver 22 can include a row driver circuit 24 and a column driver circuit 26 that provide signals to, e.g., a display array or panel 30. The cross section of the IMOD display device illustrated in
In some implementations, a frame of an image may be created by applying data signals in the form of “segment” voltages along the set of column electrodes, in accordance with the desired change (if any) to the state of the pixels in a given row. Each row of the array can be addressed in turn, such that the frame is written one row at a time. To write the desired data to the pixels in a first row, segment voltages corresponding to the desired state of the pixels in the first row can be applied on the column electrodes, and a first row pulse in the form of a specific “common” voltage or signal can be applied to the first row electrode. The set of segment voltages can then be changed to correspond to the desired change (if any) to the state of the pixels in the second row, and a second common voltage can be applied to the second row electrode. In some implementations, the pixels in the first row are unaffected by the change in the segment voltages applied along the column electrodes, and remain in the state they were set to during the first common voltage row pulse. This process may be repeated for the entire series of rows, or alternatively, columns, in a sequential fashion to produce the image frame. The frames can be refreshed and/or updated with new image data by continually repeating this process at some desired number of frames per second.
The combination of segment and common signals applied across each pixel (that is, the potential difference across each pixel) determines the resulting state of each pixel.
As illustrated in
When a hold voltage is applied on a common line, such as a high hold voltage VCHOLD
When an addressing, or actuation, voltage is applied on a common line, such as a high addressing voltage VCADD
In some implementations, hold voltages, address voltages, and segment voltages may be used which always produce the same polarity potential difference across the modulators. In some other implementations, signals can be used which alternate the polarity of the potential difference of the modulators. Alternation of the polarity across the modulators (that is, alternation of the polarity of write procedures) may reduce or inhibit charge accumulation which could occur after repeated write operations of a single polarity.
During the first line time 60a, a release voltage 70 is applied on common line 1; the voltage applied on common line 2 begins at a high hold voltage 72 and moves to a release voltage 70; and a low hold voltage 76 is applied along common line 3. Thus, the modulators (common 1, segment 1), (1,2) and (1,3) along common line 1 remain in a relaxed, or unactuated, state for the duration of the first line time 60a, the modulators (2,1), (2,2) and (2,3) along common line 2 will move to a relaxed state, and the modulators (3,1), (3,2) and (3,3) along common line 3 will remain in their previous state. With reference to
During the second line time 60b, the voltage on common line 1 moves to a high hold voltage 72, and all modulators along common line 1 remain in a relaxed state regardless of the segment voltage applied because no addressing, or actuation, voltage was applied on the common line 1. The modulators along common line 2 remain in a relaxed state due to the application of the release voltage 70, and the modulators (3,1), (3,2) and (3,3) along common line 3 will relax when the voltage along common line 3 moves to a release voltage 70.
During the third line time 60c, common line 1 is addressed by applying a high address voltage 74 on common line 1. Because a low segment voltage 64 is applied along segment lines 1 and 2 during the application of this address voltage, the pixel voltage across modulators (1,1) and (1,2) is greater than the high end of the positive stability window (i.e., the voltage differential exceeded a predefined threshold) of the modulators, and the modulators (1,1) and (1,2) are actuated. Conversely, because a high segment voltage 62 is applied along segment line 3, the pixel voltage across modulator (1,3) is less than that of modulators (1,1) and (1,2), and remains within the positive stability window of the modulator; modulator (1,3) thus remains relaxed. Also during line time 60c, the voltage along common line 2 decreases to a low hold voltage 76, and the voltage along common line 3 remains at a release voltage 70, leaving the modulators along common lines 2 and 3 in a relaxed position.
During the fourth line time 60d, the voltage on common line 1 returns to a high hold voltage 72, leaving the modulators along common line 1 in their respective addressed states. The voltage on common line 2 is decreased to a low address voltage 78. Because a high segment voltage 62 is applied along segment line 2, the pixel voltage across modulator (2,2) is below the lower end of the negative stability window of the modulator, causing the modulator (2,2) to actuate. Conversely, because a low segment voltage 64 is applied along segment lines 1 and 3, the modulators (2,1) and (2,3) remain in a relaxed position. The voltage on common line 3 increases to a high hold voltage 72, leaving the modulators along common line 3 in a relaxed state.
Finally, during the fifth line time 60e, the voltage on common line 1 remains at high hold voltage 72, and the voltage on common line 2 remains at a low hold voltage 76, leaving the modulators along common lines 1 and 2 in their respective addressed states. The voltage on common line 3 increases to a high address voltage 74 to address the modulators along common line 3. As a low segment voltage 64 is applied on segment lines 2 and 3, the modulators (3,2) and (3,3) actuate, while the high segment voltage 62 applied along segment line 1 causes modulator (3,1) to remain in a relaxed position. Thus, at the end of the fifth line time 60e, the 3×3 pixel array is in the state shown in
In the timing diagram of
The details of the structure of interferometric modulators that operate in accordance with the principles set forth above may vary widely. For example,
As illustrated in
In implementations such as those shown in
The process 80 continues at block 84 with the formation of a sacrificial layer 25 over the optical stack 16. The sacrificial layer 25 is later removed (e.g., at block 90) to form the cavity 19 and thus the sacrificial layer 25 is not shown in the resulting interferometric modulators 12 illustrated in
The process 80 continues at block 86 with the formation of a support structure e.g., a post 18 as illustrated in
The process 80 continues at block 88 with the formation of a movable reflective layer or membrane such as the movable reflective layer 14 illustrated in
The process 80 continues at block 90 with the formation of a cavity, e.g., cavity 19 as illustrated in
In some implementations, the rows G1, R1 and B1 are not driven. Similarly, the columns 1 through 3 may not be driven. Instead, the nine “corner” subpixels 921 in this area may all be interconnected. This configuration may result in a significant voltage change at the interface between the edge subpixel array 910, the corner subpixels 921 and the active subpixel array 915, e.g., between the edge subpixels B1 and G2 in column 3, because the drive signals for driving the active subpixel array 915 are going through the edge subpixel G2. The routing area 905a, through which relatively large drive voltages are applied, may sometimes be referred to herein as the “common.” Relatively smaller drive voltages are applied in the routing area 905b, which is also known as the “segment.” In earlier implementations, the relatively large voltages that were applied in the common routing area actuated the edge subpixels that were disposed between the common routing area and the active subpixel array. This caused some power to be consumed pointlessly and caused other problems, such as needless complication of the drive schemes.
In order to address these problems, in the implementation shown in
Because the vias 920 connect the movable reflective layer 14 with the optical stack 16 of the interferometric modulators 12d, the interferometric modulators 12d do not consume power when the active area is being driven. Moreover, the vias 920 may be made from material that has a higher electrical conductivity than the materials used to form the electrical connections between conventional edge subpixels or between the interferometric modulators 12c of the active subpixel array 915. Therefore, the edge subpixels 12d that include the vias 920 can conduct electric current more effectively between the routing area 905 and the active subpixel array 915 than conventional edge subpixels.
If the subpixels 12d having the vias 920 are electrically isolated, the rows and columns used for electrically connecting the routing areas 905a and 905b to the active subpixel array 915 can be maintained. In order to maintain electrical isolation of these rows and columns of the edge subpixel array 910, either the movable reflective layer 14 or the optical stack 16 of each interferometric modulator 12d may be isolated from that of the adjacent edge subpixels 12d. For example, the edge subpixels 12d along the rows that connect the routing area 905a with the active subpixel array 915 may include longer “slot cuts” than the edge subpixels 12c of the active subpixel array 915, in order to isolate adjacent portions of the movable reflective layer 14. Such slot cuts may extend across the posts 18 and connect the mech cuts, as described below with reference to
In block 1010, an optical stack is formed on a substantially transparent substrate.
In block 1015 of process 1000, one or more sacrificial layers are formed on the optical stack. The sacrificial layer is later removed (at block 1080) to form a cavity. Therefore, the sacrificial layer is not shown in
In block 1020 of
In block 1030, a second conductive and reflective layer is formed on the support structures. One example of the second conductive layer is the layer 14 of
Although blocks 1040, 1050 and 1060 are shown as sequential blocks in
In this example, a routing area is formed in block 1050. The routing area may be used supply power and to connect various devices, such as those described below with reference to
In block 1060, edge subpixels are formed. These edge subpixels may be configured to provide electrical connectivity between the routing area and the active subpixels. In this example, at least some of the edge subpixels include a via that electrically connects the first conductive layer and the second conductive and reflective layer. The via may, for example, be similar to one of the vias 920 shown in the subpixels 12d of
In block 1080, the sacrificial layer is released to form an optical cavity between the optical stack 16 and the reflective and conductive layer 14. In the subpixels 12c of the active subpixel array, the reflective and conductive layer 14 of each active subpixel may be configured to be movable relative to the optical stack 16 when a sufficient voltage is applied between the first conductive layer and the second conductive layer.
In block 1085, final processing and packaging operations may be performed. For example, individual displays may be singulated. Processors, driver controllers, etc., may be electrically connected with the routing area. The resulting display devices may be incorporated into a portable device, e.g., a device such as that described below with reference to
Some methods of device fabrication will now be described with reference to
In block 1105 of
In this example, a thin etch stop (Al2O3) layer is deposited first. This etch stop layer is not illustrated in
However, it is desirable to have light reflecting from the remaining portions of the interferometric modulator display. Therefore, in block 1110, the black mask 1200 is patterned and removed from these “active areas” 1227. Block 1110 also may involve forming gaps 1720 in the black mask 1200, e.g., as depicted in
In block 1115 of
As described in more detail below, in some implementations “mech cuts” divide the mechanical layer into columns (see, e.g.,
In such implementations, the row electrodes include a layer 1230, which is a thin layer of molychrome in this example. The layer 1230 may be referred to herein as the M1 layer 1230. In some instances, the layer 1230 may be on the order of 50 angstroms thick. Molychrome is a relatively high-resistance material. Accordingly, the vias that are formed down to the conductive AlSi layer 1220 of the black mask 1200 in block 1115 effectively increase the overall conductivity of the overlying M1 layer 1230. Therefore, electrical signals may be carried across many pixels, e.g., from one routing side of the subpixel array to the other side of the subpixel array via this conductive AlSi layer 1220 of the black mask 1200. If M1 layer 1230 is connected to the conductive AlSi layer 1220 of the black mask 1200 in the vias adjacent to each subpixel, the higher-resistance layer 1230 may be used to convey electrical signals from the edge of the subpixel to the center of the subpixel. This distance may be made small enough that the signal transmission time associated with transmission through the layer 1230 can be kept within acceptable limits.
In this example, dielectric layers 1235 and 1240 are then deposited on the M1 layer 1230 (see block 1125 of
In order to form subpixels 12 that can produce three different colors, subpixels having optical cavities of three different sizes may be formed. In block 1130 of
In block 1135, the layer 1240 is removed from areas outside of the subpixels in this example (see
The top post material 1410 may then be deposited in block 1150 (see
In a via 1430 of the routing area, material may be removed down to M1 layer 1230, which overlies the reflective and conductive layer 1220 of the black mask 1200 (see
Block 1155 may involve a variety of other operations, according to the particular implementation and according to what part of the subpixel array is being formed. In order to form active subpixels 12c, the top post material 1410 and the bottom post material 1325 may be removed from areas 1415 of the subpixels 12c (see
A layer of reflective and conductive material 1440 may then be deposited in block 1160 (see
However, in order to form dummy edge pixels as provided herein, block 1155 may involve alternative operations. In some such implementations, at least one via 920 may be formed in block 1155. In the example shown in
In alternative implementations, block 1155 may involve forming vias 920 in each one of the interferometric modulators 12d of the edge subpixel array 910.
The mechanical layer may include not only the reflective and conductive layer 1440 but also overlying dielectric material. In addition to the layer 1440, this overlying dielectric material also may be deposited and patterned in block 1160.
In some implementations, substantially the same voltage is applied to all three types of subpixels 12c in the active subpixel array 915 (see FIG. 9). Although this is not a necessary feature, such implementations can simplify the control circuitry. In the high gap subpixels 12c there is a greater separation between the M1 layer and layer 1440. Therefore, a smaller electrical force will result from a given voltage. In some implementations, the stiffness of the mechanical layer of the high gap subpixels 12c is therefore configured to be less than that of the other subpixel types, so that less force is required to pull down the mechanical layer of the high gap subpixels 12c. Similarly, the stiffness of the mechanical layer of the low gap subpixels 12c may be configured to be greater than that of the other subpixel types, so that it is relatively harder to pull down the mechanical layer. Such configurations allow the actuation voltage for all three types of subpixels to be substantially equalized.
The mechanical layer for a green, low gap subpixel 12c can be made the stiffest by adding the dielectric layers 1505a, 1505b and 1505c to the reflective layer 1440 in the process of block 1160 (see
In block 1170 of
In block 1175, the mech cuts and slot cuts are formed (see
The black mask 1200 and the active areas 1227 may be seen in
However, as noted above, M1 layer 1230 is also involved in conducting electrical signals.
After the slot cuts 1610 and the mech cuts 1750 are formed in block 1175, the sacrificial material 1305 may be released in block 1180 (see
In block 1185, final processing and packaging operations may be performed. For example, individual displays may be singulated. Processors, driver controllers, etc., may be electrically connected with the routing area. The resulting display devices may be incorporated into a portable device, e.g., a device such as that described below with reference to
The display device 40 includes a housing 41, a display 30, an antenna 43, a speaker 45, an input device 48, and a microphone 46. The housing 41 can be formed from any of a variety of manufacturing processes, including injection molding, and vacuum forming. In addition, the housing 41 may be made from any of a variety of materials, including, but not limited to: plastic, metal, glass, rubber, and ceramic, or a combination thereof. The housing 41 can include removable portions (not shown) that may be interchanged with other removable portions of different color, or containing different logos, pictures, or symbols.
The display 30 may be any of a variety of displays, including a bi-stable or analog display, as described herein. The display 30 also can be configured to include a flat-panel display, such as plasma, EL, OLED, STN LCD, or TFT LCD, or a non-flat-panel display, such as a CRT or other tube device. In addition, the display 30 can include an interferometric modulator display, as described herein.
The components of the display device 40 are schematically illustrated in
The network interface 27 includes the antenna 43 and the transceiver 47 so that the display device 40 can communicate with one or more devices over a network. The network interface 27 also may have some processing capabilities to relieve, e.g., data processing requirements of the processor 21. The antenna 43 can transmit and receive signals. In some implementations, the antenna 43 transmits and receives RF signals according to the IEEE 16.11 standard, including IEEE 16.11(a), (b), or (g), or the IEEE 802.11 standard, including IEEE 802.11a, b, g or n. In some other implementations, the antenna 43 transmits and receives RF signals according to the BLUETOOTH standard. In the case of a cellular telephone, the antenna 43 is designed to receive code division multiple access (CDMA), frequency division multiple access (FDMA), time division multiple access (TDMA), Global System for Mobile communications (GSM), GSM/General Packet Radio Service (GPRS), Enhanced Data GSM Environment (EDGE), Terrestrial Trunked Radio (TETRA), Wideband-CDMA (W-CDMA), Evolution Data Optimized (EV-DO), 1xEV-DO, EV-DO Rev A, EV-DO Rev B, High Speed Packet Access (HSPA), High Speed Downlink Packet Access (HSDPA), High Speed Uplink Packet Access (HSUPA), Evolved High Speed Packet Access (HSPA+), Long Term Evolution (LTE), AMPS, or other known signals that are used to communicate within a wireless network, such as a system utilizing 3G or 4G technology. The transceiver 47 can pre-process the signals received from the antenna 43 so that they may be received by and further manipulated by the processor 21. The transceiver 47 also can process signals received from the processor 21 so that they may be transmitted from the display device 40 via the antenna 43. The processor 21 may be configured to receive time data, e.g., from a time server, via the network interface 27.
In some implementations, the transceiver 47 can be replaced by a receiver. In addition, the network interface 27 can be replaced by an image source, which can store or generate image data to be sent to the processor 21. The processor 21 can control the overall operation of the display device 40. The processor 21 receives data, such as compressed image data from the network interface 27 or an image source, and processes the data into raw image data or into a format that is readily processed into raw image data. The processor 21 can send the processed data to the driver controller 29 or to the frame buffer 28 for storage. Raw data typically refers to the information that identifies the image characteristics at each location within an image. For example, such image characteristics can include color, saturation, and gray-scale level.
The processor 21 can include a microcontroller, CPU, or logic unit to control operation of the display device 40. The conditioning hardware 52 may include amplifiers and filters for transmitting signals to the speaker 45, and for receiving signals from the microphone 46. The conditioning hardware 52 may be discrete components within the display device 40, or may be incorporated within the processor 21 or other components.
The driver controller 29 can take the raw image data generated by the processor 21 either directly from the processor 21 or from the frame buffer 28 and can re-format the raw image data appropriately for high speed transmission to the array driver 22. In some implementations, the driver controller 29 can re-format the raw image data into a data flow having a raster-like format, such that it has a time order suitable for scanning across the display array 30. Then the driver controller 29 sends the formatted information to the array driver 22. Although a driver controller 29, such as an LCD controller, is often associated with the system processor 21 as a stand-alone integrated circuit (IC), such controllers may be implemented in many ways. For example, controllers may be embedded in the processor 21 as hardware, embedded in the processor 21 as software, or fully integrated in hardware with the array driver 22.
The array driver 22 can receive the formatted information from the driver controller 29 and can re-format the video data into a parallel set of waveforms that are applied many times per second to the hundreds, and sometimes thousands (or more), of leads coming from the display's x-y matrix of pixels.
In some implementations, the driver controller 29, the array driver 22, and the display array 30 are appropriate for any of the types of displays described herein. For example, the driver controller 29 can be a conventional display controller or a bi-stable display controller (e.g., an IMOD controller). Additionally, the array driver 22 can be a conventional driver or a bi-stable display driver (e.g., an IMOD display driver). Moreover, the display array 30 can be a conventional display array or a bi-stable display array (e.g., a display including an array of IMODs). In some implementations, the driver controller 29 can be integrated with the array driver 22. Such an implementation is common in highly integrated systems such as cellular phones, watches and other small-area displays.
In some implementations, the input device 48 can be configured to allow, e.g., a user to control the operation of the display device 40. The input device 48 can include a keypad, such as a QWERTY keyboard or a telephone keypad, a button, a switch, a rocker, a touch-sensitive screen, or a pressure- or heat-sensitive membrane. The microphone 46 can be configured as an input device for the display device 40. In some implementations, voice commands through the microphone 46 can be used for controlling operations of the display device 40.
The power supply 50 can include a variety of energy storage devices as are well known in the art. For example, the power supply 50 can be a rechargeable battery, such as a nickel-cadmium battery or a lithium-ion battery. The power supply 50 also can be a renewable energy source, a capacitor, or a solar cell, including a plastic solar cell or solar-cell paint. The power supply 50 also can be configured to receive power from a wall outlet.
In some implementations, control programmability resides in the driver controller 29 which can be located in several places in the electronic display system. In some other implementations, control programmability resides in the array driver 22. The above-described optimization may be implemented in any number of hardware and/or software components and in various configurations.
The various illustrative logics, logical blocks, modules, circuits and algorithm processes described in connection with the implementations disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. The interchangeability of hardware and software has been described generally, in terms of functionality, and illustrated in the various illustrative components, blocks, modules, circuits and processes described above. Whether such functionality is implemented in hardware or software depends upon the particular application and design constraints imposed on the overall system.
The hardware and data processing apparatus used to implement the various illustrative logics, logical blocks, modules and circuits described in connection with the aspects disclosed herein may be implemented or performed with a general purpose single- or multi-chip processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, or, any conventional processor, controller, microcontroller, or state machine. A processor also may be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. In some implementations, particular processes and methods may be performed by circuitry that is specific to a given function.
In one or more aspects, the functions described may be implemented in hardware, digital electronic circuitry, computer software, firmware, including the structures disclosed in this specification and their structural equivalents thereof, or in any combination thereof. Implementations of the subject matter described in this specification also can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions, encoded on a computer storage media for execution by, or to control the operation of, data processing apparatus.
The various illustrative logics, logical blocks, modules, circuits and algorithm processes described in connection with the implementations disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. The interchangeability of hardware and software has been described generally, in terms of functionality, and illustrated in the various illustrative components, blocks, modules, circuits and processes described above. Whether such functionality is implemented in hardware or software depends upon the particular application and design constraints imposed on the overall system.
The hardware and data processing apparatus used to implement the various illustrative logics, logical blocks, modules and circuits described in connection with the aspects disclosed herein may be implemented or performed with a general purpose single- or multi-chip processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, or, any conventional processor, controller, microcontroller, or state machine. A processor also may be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. In some implementations, particular processes and methods may be performed by circuitry that is specific to a given function.
In one or more aspects, the functions described may be implemented in hardware, digital electronic circuitry, computer software, firmware, including the structures disclosed in this specification and their structural equivalents thereof, or in any combination thereof. Implementations of the subject matter described in this specification also can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions, encoded on a computer storage media for execution by, or to control the operation of, data processing apparatus.
If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. The processes of a method or algorithm disclosed herein may be implemented in a processor-executable software module which may reside on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that can be enabled to transfer a computer program from one place to another. A storage media may be any available media that may be accessed by a computer. By way of example, and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that may be used to store desired program code in the form of instructions or data structures and that may be accessed by a computer. Also, any connection can be properly termed a computer-readable medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. Additionally, the operations of a method or algorithm may reside as one or any combination or set of codes and instructions on a machine readable medium and computer-readable medium, which may be incorporated into a computer program product.
Various modifications to the implementations described in this disclosure may be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other implementations without departing from the spirit or scope of this disclosure. Thus, the claims are not intended to be limited to the implementations shown herein, but are to be accorded the widest scope consistent with this disclosure, the principles and the novel features disclosed herein.
For example, the concepts described herein could be applied to almost any type of passively-addressed display that has dummy pixels, such as passively-addressed organic light-emitting diode (OLED) displays or passively-addressed field emission displays. If the passively-addressed display has pixel-like edge structures outside the active area and is a two-terminal device, for example, vias could be formed in the pixel-like edge structures. The concepts described herein may be very useful in OLEDs for various reasons, including power and wear issues. It would be desirable to include OLED edge pixels in order to avoid edge process effects. It would also be desirable for OLED edge pixels to be completely dark, which could be accomplished by forming dummy pixels generally as described herein.
The word “exemplary” is used exclusively herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other implementations. Additionally, a person having ordinary skill in the art will readily appreciate, the terms “upper” and “lower” are sometimes used for ease of describing the figures, and indicate relative positions corresponding to the orientation of the figure on a properly oriented page, and may not reflect the proper orientation of the IMOD (or any other device) as implemented.
Certain features that are described in this specification in the context of separate implementations also can be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation also can be implemented in multiple implementations separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.
Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Further, the drawings may schematically depict one more example processes in the form of a flow diagram. However, other operations that are not depicted can be incorporated in the example processes that are schematically illustrated. For example, one or more additional operations can be performed before, after, simultaneously, or between any of the illustrated operations. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products. Additionally, other implementations are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results.
