BRIEF DESCRIPTION OF THE DRAWING FIGURES
The above and/or other aspects of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawing figures, wherein;
FIG. 1 is a simplified block diagram of a duplexer according to an exemplary embodiment of the present invention;
FIG. 2 is a cross-sectional view of an FBAR according to an exemplary embodiment of the present invention;
FIG. 3 is a simplified block diagram of first and second BPFs of FIG. 1;
FIG. 4 is a block diagram of an exemplary first BPF of FIG. 1;
FIG. 5 is a graph showing a simulation result of filtering characteristic of the first BPF of FIG. 4;
FIG. 6 is a block diagram of another exemplary embodiment of the first BPF of FIG. 1;
FIG. 7 is a block diagram of an exemplary embodiment of the second BPF of FIG. 1;
FIG. 8 is a graph showing a simulation result of filtering characteristic of the second BPF of FIG. 7;
FIG. 9 is a diagram showing impedance characteristic of the second BPF to the first BPF of FIG. 1;
FIG. 10 is a block diagram of a duplexer constructed as a single chip set according to an exemplary embodiment of the present invention;
FIG. 11 is a block diagram of a related art duplexer constructed using a plurality of FBARs;
FIG. 12 is a diagram showing a function of the phase shifter of FIG. 11; and
FIG. 13 is another diagram showing a function of the phase shifter of FIG. 11.