Disclosed is a dyadic sensor to sense an analyte, the dyadic sensor comprising: an analyte gate; a transition metal dichalcogenide layer disposed on the analyte gate and comprising a transition metal dichalcogenide; a source electrode disposed on the two-dimensional active layer and in electrical communication with the two-dimensional active layer; a drain electrode disposed on the two-dimensional active layer and in electrical communication with the two-dimensional active layer and in electrical communication with the source electrode via the two-dimensional active layer; and a control gate disposed on the two-dimensional active layer and controlling the communication of electrical current in the two-dimensional active layer between the source electrode and the drain electrode, wherein the electrical current communicated in the two-dimensional active layer is changed in response to a change in an electrical charge present at the analyte gate due to the analyte.
Also disclosed is a process for sensing an analyte, the process comprising: providing the dyadic sensor; subjecting the source electrode and the drain electrode with a first potential difference comprising a drain voltage; subjecting the control gate with a gate voltage; and monitoring a drain current to sense a presence of the analyte at the analyte gate.
The following descriptions should not be considered limiting in any way. With reference to the accompanying drawings, like elements are numbered alike.
A detailed description of one or more embodiments is presented herein by way of exemplification and not limitation.
It has been discovered that a dyadic sensor includes a field effect transistor (FET) having an analyte gate and a control gate that provides a reduction in noise and improved sensitivity as compared with a convention FET. The dyadic sensor detects, identifies, or to characterizes an analyte and generates an electronic signal in response to a presence of the analyte proximate to the analyte gate. The electronic signal can be, e.g., a change in a drain current across a two-dimensional active layer of the dyadic sensor. The change in the drain current can be proportional to the charge of the analyte. The electronic signal can be scaled to provide a gain characteristic of dyadic sensor to provide a high signal-to-noise ratio for sensing the analyte.
The dyadic sensor senses a change in an electric charge at an analyte gate due to the electric charge of an analyte. In an embodiment, with reference to
In an embodiment, dyadic sensor 100 includes gate insulating layer 24 interposed between control gate 2 and two-dimensional active layer 6 such that control gate 2 is bounded at channels surface 22 by wall 18 of source electrode 8, wall 20 of drain electrode 10, and control gate surface of two-dimensional active layer 6. Here, control gate 2 includes free surface 25. Moreover, two-dimensional active layer analyte gate surface 14 that opposes channel surface 12 of analyte gate 4. Further, analyte gate 4 includes analyte surface 10 on which analyte 58 can interact.
In an embodiment, with reference to
In an embodiment, with reference to
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In an embodiment, dyadic sensor 100 includes an improved semiconductor/insulating interface structure formed by inclusion of two-dimensional active layer 6 in which two-dimensional active layer 6 can include a two-dimensional (2D) atomic crystal layer, Such a structure may be used, for example in a field effect device, e.g., a thin film transistor. Other embodiments include a method for forming such a structure and for forming a field effect device such as a thin film transistor structure in dyadic sensor 100.
Dyadic sensor 100 advantageously provide greater carrier mobility, lower power consumption due to reduction in leakage current, high temperature stability (e.g., up to 500° C.), lower cost as compared, e.g., with a conventional crystalline silicon field effect transistor. In an embodiment, a 10× to 20× greater mobility (e.g., up to and greater than 500 cm2/Vs) or 2 orders of magnitude lower power consumption due to the reduction in leakage current is provided.
In an embodiment, dyadic sensor 100 includes substrate 30 that can be any suitable dielectric or semiconductor material, e.g., silicon, glass, plastic, silicon, silicon on insulator, sapphire, and the like. Substrate 30 can be selected to support an interface between electronic and biological components as well as provide mechanical support for components of dyadic sensor 100. In an embodiment, substrate 30 includes a regular shaped surface. Exemplary substrates 30 include silicon, silicon dioxide on silicon, Al2O3 on Si, HfO2 on Si, sapphire, silicon carbide, and the like. In an embodiment, substrate 30 is thermally grown silicon dioxide on silicon with a part of the underlying silicon removed to form analyte chamber 34. In an embodiment, substrate 30 includes silicon dioxide on silicon.
A thickness of substrate 30 can be from 100 nanometers (nm) to 1 centimeters (cm), specifically from 500 nm to 1 millimeter (mm), and more specifically from 1000 nm to 500 micrometers (μm).
Analyte gate 4 is provided in dyadic sensor 100 for changing drain current ID due to interaction with analyte 58. Exemplary materials for analyte gate 4 includes a dielectric material such as Al2O3, Hf2O2, SiO2, hexagonal boron nitride, and the like. In an embodiment, analyte gate 4 includes analyte surface 10 that can include be a chemical interface to promote adhesion of analyte 58 thereto. Analyte surface 10 improves selectivity of dyadic sensor 100 for analyte 58.
A thickness of analyte gate 4 can be from 1 nm to 300 nm, specifically from 1 nm to 30 nm, and more specifically from 2 nm to 10 nm.
It is contemplated that analyte gate contact 40 can be disposed on analyte gate 4. Exemplary materials for analyte gate 4 include silicon dioxide on silicon, Al2O3 on Si, HfO2 on Si, sapphire, silicon carbide, and the like, Analyte gate extension 50 can be connected to analyte gate contact 40. In this manner, analyte gate contact 40 or analyte gate extension 50 can interact (e.g., contact) analyte 58 and communicated a change in electrical charge to analyte gate 4, wherein analyte gate 4 produces a change in drain current ID between source electrode 8 and drain electrode 10. Further, electrical pads (e.g., 80, 82) can be disposed on substrate 30 and in electrical contact with analyte gate contact 40 or analyte gate extension 50. It should be appreciated that analyte gate contact 40 or analyte gate extension 50, pads (80, 82) are electrically conductive and can include an electrical conductor such as a metal, e.g., titanium, gold, silver, aluminum, nickel, chrome, and the like, or a combination thereof.
A thickness of analyte gate contact 40 and analyte gate extension 50 independently can he from 20 nm to 300 nm, specifically from 50 nm to 200 nm, and more specifically from 50 nm to 100 nm.
Source electrode 8 and drain electrode 10 are disposed on two-dimensional active layer 6 to produce drain current ID that changes due to application of gate voltage VG to control gate 2 and a presence of analyte 58 at analyte gate 4, analyte gate contact 40, or analyte gate extension 50, It should be appreciated that source electrode 8 and drain electrode 10 are electrically conductive and can include an electrical conductor such as a metal, e.g., titanium, gold, silver, aluminum, nickel, chrome, and the like, or a combination thereof. A thickness of source electrode 8 and drain electrode 10 independently can be from 20 nm to 300 nm, specifically from 50 nm to 200 nm, and more specifically from 50 nm to 100 nm.
Control gate 2 is disposed on two-dimensional active layer 6 to control production of drain current ID via application of gate voltage VG to control gate 2 or presence of analyte 58 at analyte gate 4, analyte gate contact 40, or analyte gate extension 50. It should be appreciated that control gate 2 is electrically conductive and can include an electrical. conductor such as a metal, e.g., titanium, gold, silver, aluminum, nickel, chrome, and the like, or a combination thereof. A thickness of control gate 2 can be from 20 nm to 300 nm, specifically from 50 nm to 200 nm, and more specifically from 50 nm to 100 nm.
Gate insulating layer 24 is interposed between control gate 2 and two-dimensional active layer 6 to electrically isolate control gate 2 from two-dimensional active layer 6. It is contemplated that gate insulating layer 24 can be interposed between control gate 2 and drain electrode 10, control gate 2 and source electrode 8, or a combination thereof for electrical isolation. In some embodiments, gate insulating layer 24 is a high dielectric constant (“high-k”) insulator layer. in some embodiments, the high-k insulator layer has a high-k value from 10 to 40 e0. In some embodiments, the high-k insulator layer has a high k-value greater than 40 e0. Exemplary material for gate insulating layer 24 includes an electrical insulator such as Al2O3, Hf2O2, SiO2, hexagonal boron nitride, and the like, or a combination thereof. A thickness of gate insulating layer 24 can be from 1 nm to 300 nm, specifically from 1 nm to 30 nm, and more specifically from 2 nm to 10 nm.
Two-dimensional active layer 6 is interposed. between control gate 2 and analyte gate 4. Two-dimensional active layer 6 can he a 2D atomic crystal layer with a crystalline atomic plane produced either from a bottom-up synthesis process (e.g. Van-der-Waals epitaxial growth), extracted, cleaved, or the like from a constituent bulk crystal. In some embodiments, an individual crystalline atomic plane is cleaved from a bulk homogeneous crystal structure. In some embodiment, two-dimensional active layer 6 is provided by cleaving a heterogeneous crystal. structure. The cleaving process can be accomplished, e.g., by mechanical exfoliation, chemical exfoliation, or a combination thereof. The crystalline atomic plane of two-dimensional active layer 6 has a generally two-dimensional (2D) structure in x- and y-directions and a very small depth in the z-direction relative to its dimensions in the x-y plane (i.e., Dx, Dy>>Dz). The 2D atomic crystals includes transition metal dichalcogenide (TMD) that provides a semiconducting structure and according semiconducting electrical properties. Additional 2D atomic crystals include black phosphorous, graphene oxide, indium selenide, silecene, and the like, or a combination thereof.
TMD can be arranged in an atomically thin monolayer having a chemical formula MX2, wherein M a transition metal, and X is a chalcogenide of a chalcogen (e.g., O, S, Se, Te, and the like) from group 16 of the periodic table of elements. M can be, e.g., a transition metal of Group 3 (e.g., Sc, Y, and the like), Group 4 (e.g., Ti, Zr, Hf, and the like), Group 5 (e.g., V, Nb, Ta, and the like), Group 6 (e.g., Cr, Mo, W, and the like), Group 7 (e.g., Mn Re, and the like), Group 8 (e.g., Fe, Ru, Os, and the like), Group 9 (e.g., Co, Rh, Ir, and the like), Group 10 (e.g., Ni, Pd, Pt, and the like), Group 11 (e.g., Cu, Ag, Au, and the like), Group 12 (e.g., Zn, Cd, Hg, and the like), and the like, or a combination thereof. Alloyed forms of TMDs can be included in two-dimensional active layer 6 and can include a chemical formula MmM′1-mX2, wherein M and M′ are different transition metals, and 0<m<1; MXXX′2-x, wherein X and X′ are different chalcogenides, and 0<x<2; and MmM′1-mXXX′2-xwhere M and M′ are different transition metals, X and X′ are different chalcogenides, and 0<m<1, and 0<x<2. Doped forms of TMDs can be included in two-dimensional active layer 6 and can include alkali metal-doped forms of TMDs. More generally, M can be any combination of one or more transition metals, X can be any combination of one or more of S, Se, and Te, and the chemical formula can be represented as MXy, where y is 2 or about 2. In some embodiments, TMD in two-dimensional active layer includes transition metal M that is a Group 6 transition metal (e.g., Mo or W).
Exemplary semiconducting transition metal dichalcogenides for two-dimensional active layer 6 include molybdenum disulfide (MoS2), tungsten disulfide (WS2), niobium disulfide (NbS2), tantalum disulfide (TaS2), vanadium disulfide (VS2), rhenium disulfide (ReS2), tungsten selenide (WSe2), molybdenum selenide (MoSe2), niobium selenide (NbSe2), or the like. Without wishing to be bound by theory, transition metal dichalcogenides having group 4 and 6 transition metals (e.g., Mo, Hf, W) exhibit superconducting, semiconducting or insulating properties, depending on the band-gap of the material. The unfilled transition-metal d-band determines the band-gap, the dielectric constant, and mobility of the transition metal dichalcogenides.
Two-dimensional active layer 6 can be a single monolayer, double monolayer, triple monolayer, or the like. It is contemplated that a thickness of gate insulating layer 24 can be from 1 nm to 300 nm, specifically from 1 nm to 30 nm, and more specifically from 2 nm to 10 nm.
In an embodiment, with reference to
In an embodiment, as shown in panel B of
Dyadic sensor 100 has numerous beneficial uses, including sensing analyte 58. In an embodiment, process for sensing an analyte includes providing dyadic sensor 100; subjecting source electrode 8 and drain electrode 10 with a first potential difference comprising drain voltage VD; subjecting control gate 2 with gate voltage VG; and monitoring drain current ID to sense a presence of analyte 58 at analyte gate 4. As used herein, “sensing” can include detection of the presence of one or more analytes, measurements of the interaction between two or more analytes, detecting conformational or structural changes in one or more analytes, detecting chemical changes that lead a change in net charge of one or more analytes. The process can further include controlling a frequency of gate voltage VG with frequency driver 98, wherein monitoring drain current ID includes detecting drain current ID at the frequency of gate voltage VG. The process also can include controlling an amplitude of gate voltage VG with control loop feedback controller 102. In some embodiments, the process includes providing error signal 99 from frequency driver 98 to control loop feedback controller 102; and providing control signal 97 from control loop feedback controller 102 to control the amplitude of gate voltage VG, wherein control signal 97 changes in response to a change in error signal 99. Acquisition of the drain current ID can be accomplished by a parameter analyzer, ammeter, analog to digital convertor, or oscilloscope. Additionally, a set point can be supplied to control loop feedback controller 102 by a digital input or analog voltage source.
Dyadic sensor 100 has numerous advantageous and beneficial properties. In an aspect, dyadic sensor 100 is a dyadic sensor, wherein drain current ID through two-dimensional active layer 6 changes in response to and depends upon volt gate VG applied to control gate 2 and the charge present at analyte gate 4. Moreover, dyadic sensor 100 can be an asymmetric sensor, wherein control gate 2 is a different material than analyte gate 4. In an embodiment, control gate 2 is electrically conductive, and analyte gate 4 is dielectric. It is contemplated that dyadic sensor 100 can be a symmetric sensor, wherein control gate 2 is a same material as analyte gate 4. Further, dyadic sensor 100 provides sensitive detection and quantification of analytes due to the presence of a separate control gate 2, wherein dyadic sensor 100 can be disposed at a point of optimal sensitivity, in an absence of decreasing sensitivity from adsorption of analyte 58 to the surface of analyte gate 4.
Advantageously, unexpectedly, and surprisingly, dyadic sensor 100 is a dual gate article and includes control gate 2 to control two-dimensional active layer 6 and also includes analyte gate 4 that can be a thin membrane layer disposed over analyte chamber 34 (a fluidic chamber for flow or disposal of analyte 58 on analyte gate 4). Beneficially, analyte gate contact 40 can be disposed on analyte gate 4 and can be a second metal gate electrode that is superior to a conventional chem FET or floating gate FET, which adsorb molecules on a metal top gate. Because chem FET or floating gate FET has a thick gate dielectric, the chem FET or floating gate FET has a loss of sensitivity over time. Dyadic sensor 100 overcomes these problems with conventional FETs and decreases effects of already adsorbed layers of analyte on analyte gate 4 by changing the top gate voltage in a presence of the adsorbed layers.
Additionally, dyadic sensor 100 selectively senses inter-molecular interactions in a composition that includes a plurality of analytes 58 and senses a selected analyte selectively, e.g., via adsorbant 110 disposed on analyte gate 4, wherein adsorbant 110 interact (e.g., bind) to a selected analyte with a selected specificity (e.g., high specificity, low specificity, and the like).
The articles and processes herein are illustrated further by the following Examples, which are non-limiting.
A dyadic sensor was fabricated by first defining the control gate using photolithography, followed by depositing 20 nm of gate insulating material, A2O3, using an atomic layer deposition (ALD) process. Single crystal monolayer MoS2 was exfoliated onto the control gate insulator. This was followed by ebeam lithography to define and metallize source and drain contacts with 2 nm of Ti and 50 nm Au using e-beam deposition. Deposition of 20 nm of Al2O3 with ALD followed to define the analyte gate. Finally, an analyte gate contact extension was patterned with e-beam lithography and then metallized with 2 nm of Ti and 50 nm Au using e-beam deposition.
Dyadic sensors in the array described in Example 1 were operated by placing the devices in a probe station and probing the source, drain, and control gate contacts. I-V curves were measured using a semi-conductor parameter analyzer to sweep the drain voltage and step the gate voltage to obtain the plots in
Dyadic sensors in the array described in Example 1 were used to sense an analyte by placing a droplet with known analyte concentration directly in contact with the analyte gate contact. At the end of the measurement period, the analyte gate contact was rinsed with a buffer solution consisting of 1M NaCl and 30 mM of TRIS-EDTA at pH 7.2 to remove the analyte.
To one of the dyadic sensors in the array described in Example 1, a receptor protein was attached to the analyte gate as an adsorbant as shown in
While one or more embodiments have been shown and described, modifications and substitutions may be made thereto without departing from the spirit and scope of the invention. Accordingly, it is to be understood that the present invention has been described by way of illustrations and not limitation. Embodiments herein can be used independently or can be combined.
Reference throughout this specification to “one embodiment,” “particular embodiment,” “certain embodiment,” “an embodiment,” or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, appearances of these phrases (e.g., “in one embodiment” or “in an embodiment”) throughout this specification are not necessarily all referring to the same embodiment, but may. Furthermore, particular features, structures, or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art from this disclosure, in one or more embodiments.
All ranges disclosed herein are inclusive of the endpoints, and the endpoints are independently combinable with each other. The ranges are continuous and thus contain every value and subset thereof in the range. Unless otherwise stated or contextually inapplicable, all percentages, when expressing a quantity, are weight percentages. The suffix “(s)” as used herein is intended to include both the singular and the plural of the term that it modifies, thereby including at least one of that term (e.g., the colorant(s) includes at least one colorants). “Optional” or “optionally” means that the subsequently described event or circumstance can or cannot occur, and that the description includes instances where the event occurs and instances where it does not. As used herein, “combination” is inclusive of blends, mixtures, alloys, reaction products, and the like.
As used herein, “a combination thereof” refers to a combination comprising at least one of the named constituents, components, compounds, or elements, optionally together with one or more of the same class of constituents, components, compounds, or elements.
All references are incorporated herein by reference.
The use of the terms “a” and “an” and “the” and similar referents in the context of describing the invention (especially in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. “Or” means “and/or.” Further, the conjunction “or” is used to link objects of a list or alternatives and is not disjunctive; rather the elements can be used separately or can be combined together under appropriate circumstances. It should further be noted that the terms “first,” “second,” “primary,” “secondary,” and the like herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The modifier “about” used in connection with a quantity is inclusive of the stated value and has the meaning dictated by the context (e.g., it includes the degree of error associated with measurement of the particular quantity).
This application claims the benefit of U.S. Provisional Patent Application Ser. Nos. 62/307,406, filed Mar. 11, 2016, the disclosure of which is incorporated herein by reference in its entirety.
This invention was made with United States Government support from the National Institute of Standards and Technology. The Government has certain rights in the invention.
Number | Date | Country | |
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62307406 | Mar 2016 | US |