Patent Application
20160036321
This application relates to bypass capacitors, and more particularly to a dynamic bypass capacitor.
A digital circuit such as a microprocessor or a system-on-a-chip (SOC) includes numerous transistors that alternate between dormant and switching states. The digital circuits are powered by power rails supplying power supply voltages maintained by corresponding regulators. The regulators function to maintain the power supply voltages on the power rails. But digital circuits may make abrupt current demands when a large number of transistors switch states. The power supply voltage provided by a power rail may then sag unacceptably despite the action of its regulator in promoting a stable power supply voltage.
To keep the power supply voltages from dipping unacceptably, the power rails may be tied to decoupling capacitors that provide additional power to the digital circuits when needed and may recharge at a later time when power demand subsides. A decoupling capacitor, unlike a conventional regulator, can supply the instantaneous current demands when numerous transistors suddenly change state and conduct current. In this sense, the decoupling capacitor decouples the power supply from the abrupt power demands made by the digital circuits. A decoupling capacitor may also be denoted as a bypass capacitor since the device receiving instantaneous power from a bypass capacitor is bypassing the primary power source (a battery driving a power regulator that in turn drives the power rail coupled to the bypass capacitor).
Although bypass capacitors are routinely provided for modern integrated circuits, their use may aggravate power demands. In particular, it is conventional for an SOC to include various power domains that may be powered down independently during idle or standby modes of operation. The collapsing of a power rail for a particular power domain wastes the charge stored in the corresponding bypass capacitor. This power consumption issue may be better appreciated with reference to
Accordingly, there is a need in the art for improved power management techniques with regard to the use of bypass capacitors.
A dynamic bypass capacitor is provided having a bypass capacitance that increases during an active mode for a digital core and decreases during an idle mode for the digital core.
These and other advantageous features may be better appreciated through the following detailed description.
Embodiments of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.
To prevent the conventional waste of charge from a bypass capacitor when the corresponding power rail is collapsed (discharged to ground), a dynamic bypass capacitor is provided. The dynamic bypass capacitor stores a first amount of charge during an active mode of operation when the corresponding power rail is powered. The dynamic bypass capacitor stores a second amount of charge during an idle mode of operation when the corresponding power rail is discharged. The second amount of charge is less than the first amount. In this fashion, the dynamic bypass capacitor stores more charge during the active mode and less charge during the idle mode. Although some charge must be discharged to ground when the dynamic bypass capacitor switches to the idle state, the remaining charge is preserved, thereby markedly increasing battery life (for battery-powered embodiments) and reducing power demands accordingly.
An example system 200 is shown in
First bypass capacitor 210 couples to power rail 125 through switch 201, which is controlled by a power management circuit 220. First bypass capacitor 210 couples to a first input port 225 for SOC 205 that in turn couples to switch 201. Power rail 125 couples to a second input port 230 for SOC 205 that in turn couples to second bypass capacitor 215 and to a power regulator 110. Power regulator 110 is configured to charge power rail 125. Power regulator 110 thus charges first bypass capacitor 210 only when switch 201 is closed. In one embodiment, power domain 105 comprises a digital core 105 such as a microprocessor core. Power management circuit 220 controls switch 201 to open or close depending upon an operating mode for digital core 105. For example, digital core 105 may be configured to operate in an idle mode of operation or in an active mode of operation. Should SOC 205 comprise a cellular telephone SOC, the active mode of operation may correspond to a wakeup period within a discontinuous receive (DRX) cycle in which SOC 205 would then check for messages or calls. In such an embodiment, the idle mode would then correspond to the inactive period during the remainder of the DRX cycle.
In one embodiment, dynamic capacitor 209 may be deemed to comprise a means for loading a power rail with a first bypass capacitance during an idle mode for a digital core and for loading the power rail with a second bypass capacitance during an active mode for the digital core, wherein the second bypass capacitance is greater than the first bypass capacitance.
During a transition from an idle mode into an active mode, power management circuit 220 may command power regulator 110 to raise the power supply voltage VDD on power rail 125 to an operating level. Alternatively, power regulator 110 may be part of a power management integrated circuit (PMIC) (not illustrated) that would command power regulator 110 to increase power supply voltage VDD to the operating level. Second bypass capacitor 215 would then be charged by this increased level for the power supply voltage VDD. In conjunction with this transition, power management circuit 220 controls switch 201 to close so that first bypass capacitor 210 is also coupled to power rail 125. Since first bypass capacitor 210 was already charged to this increased level in a previous active mode before floating during the subsequent idle mode, first bypass capacitor 210 need not be recharged as compared to second bypass capacitor 215. Referring back to
Digital core 105 will eventually transition from the active mode to the idle mode. Power management circuit 220 then commands switch 201 to open to decouple first bypass capacitor 210 from power rail 125. In addition, power management circuit 220 and/or a corresponding PMIC controls power regulator 110 to lower the power supply voltage VDD on power rail 125 to an idle mode level that is lower than the operating level used during the active mode. Some charge on second bypass capacitor 215 is then discharged to accommodate this lower voltage on power rail 125 during the idle mode. However, all the charge stored on first bypass capacitor 210 during the active mode is retained in the idle mode (absent any leakage) because first bypass capacitor 210 floats during the idle mode due to the decoupling from power rail 125 by opened switch 201.
The capacitance C2 for second bypass capacitor 215 may be sufficient to accommodate the expected instantaneous current demand by digital core 105 during the idle mode of operation. In such an embodiment, the capacitance C1 for first bypass capacitor 210 may then equal C minus C1, where C is the capacitance sufficient to accommodate the expected instantaneous current demand by digital core 105 during the active mode operation. In one embodiment, capacitance C1 may equal capacitance C2.
It will be appreciated that numerous alternative embodiments may be made to system 200. For example, if power rail 125 may be collapsed (discharged) during the idle mode, then there would be no need for second bypass capacitor 215. In such an embodiment, a capacitance C1 for first bypass capacitor 210 would then equal C, the bypass capacitance for the active mode of operation. In addition, switch 201 may be implemented by a transistor (or transistors) such as a PMOS or NMOS transistor having its gate driven by power management circuit 220. Power regulator 110 may comprise a linear dropout regulator or a switching regulator such as a buck converter. An example method of power management using a dynamic bypass capacitor will now be discussed.
As those of some skill in this art will by now appreciate and depending on the particular application at hand, many modifications, substitutions and variations can be made in and to the materials, apparatus, configurations and methods of use of the devices of the present disclosure without departing from the spirit and scope thereof. In light of this, the scope of the present disclosure should not be limited to that of the particular embodiments illustrated and described herein, as they are merely by way of some examples thereof, but rather, should be fully commensurate with that of the claims appended hereafter and their functional equivalents.
