Claims
- 1. An integrated circuit device comprising:a high voltage power supply; and a rail to rail input/output operational amplifier comprising: a dynamic cascode bias generator to provide a first bias voltage to control a first set of cascode transistors and a second bias voltage to control cascode transistors, said first bias voltage to increase towards a power supply voltage in response to a first common mode input voltage increasing above a first reference value and said second bias voltage to decrease towards a ground potential in response to a second common mode input voltage decreasing below a second reference value; an N type differential amplifier coupled to said dynamic cascode bias generator, said N type differential amplifier to have said first common mode input voltage across its inputs; and a P type differential amplifier coupled to said dynamic cascode bias generator, said P type differential amplifier to have said second common mode input voltage across its inputs.
- 2. The integrated circuit device of claim 1 wherein said N type differential amplifier comprises:a first and second N type cascode transistors coupled to said dynamic cascode bias generator; and an N type differential pair coupled to said first and second N type cascode transistors, said N type differential pair comprising of a first N type input transistor to receive an inverting input and a second N type input transistor to receive a non-inverting input.
- 3. The integrated circuit device of claim 1 wherein said P type differential amplifier comprises:a first and second P type cascode transistors coupled to said dynamic cascode bias generator; and a P type differential pair coupled to said first and second P type cascode transistors, said P type differential pair comprising of a first P type input transistor to receive said inverting input and a second P type input transistor to receive said non-inverting input.
- 4. The integrated circuit device of claim 2 wherein said dynamic cascode bias generator generates a first bias voltage to said first and second N type cascode transistors.
- 5. The integrated circuit device of claim 4 wherein said bias voltage has a fixed value in a first mode and said bias voltage increases towards upper range of a power supply voltage rail in a second mode.
- 6. The integrated circuit device of claim 3 wherein said dynamic cascode bias generator generates a first bias voltage to said first and second P type cascode transistors.
- 7. The integrated circuit device of claim 6 wherein said bias voltage has a fixed value in a first mode and said bias voltage decreases towards lower range of a power supply voltage rail in a second mode.
- 8. An operational amplifier comprising:a dynamic cascode bias generator to generate a bias voltage having a fixed value in a first mode and increasing towards upper range of a power supply voltage rail in a second mode; and an N type differential amplifier coupled to said dynamic cascode bias generator, said N type differential amplifier comprising: a first and second N type cascode transistors coupled to receive said bias voltage from said dynamic cascode bias generator; and an N type differential pair coupled to said first and second N type cascode transistors, said N type differential pair comprising of a first N type input transistor to receive an inverting input and a second N type input transistor to receive a non-inverting input.
- 9. The operational amplifier of claim 8 further comprising a common mode input signal coupled to said first N type input transistor and to said second N type input transistor, said common mode input signal to vary from a first voltage level to a second voltage level.
- 10. The operational amplifier of claim 9 wherein said first voltage level is below a midpoint between an upper power supply rail and a lower power supply rail.
- 11. The operational amplifier of claim 10 wherein said second voltage level is above said midpoint between said upper and said lower power supply rails.
- 12. The operational amplifier of claim 11 wherein said dynamic cascode bias generator generates variable voltages when said common mode input signal is outside a cascoding range.
- 13. The operational amplifier of claim 12 wherein said cascoding range ranges from said midpoint between said upper and said lower power supply rails to said lower power supply rail.
- 14. An operational amplifier comprising:a dynamic cascode bias generator to generate a bias voltage having a fixed value in a first mode and decreasing towards lower range of a power supply voltage rail in a second mode; and a P type differential amplifier coupled to said dynamic cascode bias generator, said P type differential amplifier comprising: a first and second P type cascode transistors coupled to receive said bias voltage from said dynamic cascode bias generator; and an P type differential pair coupled to said first and second P type cascode transistors, said P type differential pair comprising of a first P type input transistor to receive an inverting input and a second P type input transistor to receive a non-inverting input.
- 15. The operational amplifier of claim 14 further comprising a common mode input signal coupled to said first P type input transistor and to said second P type input transistor, said common mode input signal to vary from a first voltage level to a second voltage level.
- 16. The operational amplifier of claim 15 wherein said first voltage level is above said midpoint between said upper and said lower power supply rails.
- 17. The operational amplifier of claim 16 wherein said second voltage level is below a midpoint between an upper power supply rail and a lower power supply rail.
- 18. The operational amplifier of claim 17 wherein said dynamic cascode bias generator generates variable voltages when said common mode input signal is outside a cascoding range.
- 19. The operational amplifier of claim 18 wherein said cascoding range ranges from said midpoint between said upper and said lower power supply rails to said upper power supply rail.
Parent Case Info
This patent application is a Continuation of U.S. patent application Ser. No. 09/675,196, entitled “Dynamic Cascoding Technique For Operational Amplifiers”, filed Sep. 29, 2000.
US Referenced Citations (6)
Foreign Referenced Citations (1)
Number |
Date |
Country |
3-292007 |
Dec 1991 |
JP |
Continuations (1)
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Number |
Date |
Country |
Parent |
09/675196 |
Sep 2000 |
US |
Child |
10/062867 |
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US |