Claims
- 1. A dynamic circuit, comprising:
- an input means for receiving an input signal, comprising:
- a first transistor having a first electrode, a second electrode, and a control electrode coupled to the input signal;
- a second transistor having a first electrode coupled to the second electrode of the first transistor, a second electrode, and a control electrode coupled to the input signal;
- a clock means for receiving a clock signal, comprising:
- a third transistor having a first electrode coupled to the second electrode of the second transistor, a second electrode coupled to a ground reference voltage, and a control electrode coupled to the clock signal;
- a fourth transistor having a first electrode coupled to a first power reference voltage, a second electrode coupled to the second electrode of the first transistor, and a control electrode coupled to the clock signal; and
- a feedback means for generating an output signal, comprising:
- an inverter having an input coupled to the second electrode of the fourth transistor and an output for providing the output signal; and
- a filth transistor having a first electrode coupled to a second power reference voltage, a second electrode coupled to a first electrode of the first transistor, and a control electrode coupled to the output of the inverter.
- 2. The dynamic circuit of claim 1 wherein a dynamic node of the dynamic circuit is a connection between the second electrode of the first transistor and the first electrode of the second transistor.
- 3. The dynamic circuit of claim 2 wherein the dynamic node is discharged to a first voltage level when the input signal has a second voltage level.
- 4. The dynamic circuit of claim 3 wherein a ratio between a width of the first transistor and a width of the third transistor determines the second voltage level.
- 5. A dynamic circuit, comprising:
- an input means for receiving an input signal, comprising:
- a first transistor having a first electrode, a second electrode, and a control electrode coupled to the input signal;
- a second transistor having a first electrode coupled to the second electrode of the first transistor, a second electrode coupled to a first reference ground voltage, and a control electrode coupled to the input signal; and
- a third transistor having a first electrode coupled to a first power reference voltage, a second electrode coupled to the first electrode of the first transistor, and a control electrode;
- a clock means for receiving a clock signal, comprising:
- a fourth transistor having a first electrode, a second electrode coupled to the second electrode of the first transistor, and a control electrode coupled to the clock signal;
- a fifth transistor having a first electrode coupled to a second power reference voltage, a second electrode coupled to the first electrode of the fourth transistor, and a control electrode coupled to the clock signal; and
- a feedback means for generating an output signal, comprising:
- an inverter having an input coupled to the second electrode of the fifth transistor and an output coupled to the control electrode of the third transistor for providing the output signal; and
- a sixth transistor having a first electrode coupled to a third power reference voltage, a second electrode coupled to a first electrode of the fourth transistor, and a control electrode coupled to the output of the inverter.
- 6. The dynamic circuit of claim 5 wherein the dynamic circuit performs a logical AND function.
- 7. A dynamic circuit, comprising:
- an input means for receiving an input signal, comprising:
- a first transistor having a first electrode, a second electrode, and a control electrode coupled to the input signal;
- a second transistor having a first electrode coupled to the second electrode of the first transistor, a second electrode coupled to a first reference ground voltage, and a control electrode coupled to the input signal; and
- a third transistor having a first electrode coupled to a first power reference voltage, a second electrode coupled to the first electrode of the first transistor, and a control electrode,
- a clock means for receiving a clock signal, comprising:
- a fourth transistor having a first electrode coupled to a second power reference voltage, and a control electrode coupled to the clock signal, and
- a feedback means for generating an output signal, comprising:
- an inverter having an input coupled to a second electrode of the fourth transistor and an output coupled to the control electrode of the third transistor for providing the output signal; and
- a fifth transistor having a first electrode coupled to a third power reference voltage, a second electrode coupled to the input of the inverter, and
- a control electrode coupled to the output of the inverter; and
- a sixth transistor having a first electrode coupled to the input of the inverter, a second electrode coupled to the first electrode of the second transistor and a control electrode coupled to the clock signal.
CROSS-REFERENCE TO RELATED APPLICATION
Related subject may be found in the commonly assigned, co-pending U.S. patent application, which is incorporated by reference herein:
Ser. No. 08/547,269, entitled "DYNAMIC CMOS CIRCUITS WITH NOISE IMMUNITY" and issued as U.S. Pat. No. 5,650,733 on Jul. 22, 1997, which was filed Oct. 24, 1995.
US Referenced Citations (9)
Foreign Referenced Citations (3)
Number |
Date |
Country |
59-49020 |
Mar 1984 |
JPX |
63-10913 |
Jan 1988 |
JPX |
2-119443 |
May 1990 |
JPX |
Non-Patent Literature Citations (1)
Entry |
U.S. Patent Application Serial No., entitled "Dynamic CMOS Circuits with Noise Immunity" (Attorney Docket No. BU9-95-066). |